Abstract: A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).

Abstract: Nonvolatile memory elements and memory devices including the nonvolatile memory elements. A nonvolatile memory element may include a memory layer between two electrodes, and the memory layer may have a multi-layer structure. The memory layer may include a base layer and an ionic species exchange layer and may have a resistance change characteristic due to movement of ionic species between the base layer and the ionic species exchange layer. The ionic species exchange layer may have a multi-layer structure including at least two layers. The nonvolatile memory element may have a multi-bit memory characteristic due to the ionic species exchange layer having the multi-layer structure. The base layer may be an oxygen supplying layer, and the ionic species exchange layer may be an oxygen exchange layer.

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8?y?2.0) are stacked together.

Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

Abstract: A resistance change element including: a lower electrode formed on at least one of a semiconductor and insulating substrate; a resistance change material layer formed on the lower electrode and including a transition metal oxide as a major component; and an upper electrode formed on the resistance change material layer. The resistance change material layer is formed of a nickel oxide containing nickel vacancy and having a higher oxygen concentration than a stoichiometric composition, and has a stacked structure with different composition ratios.

Abstract: The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.

Abstract: A device contains a first layer (420), a second layer (440); and a membrane (430) between the first and second layers (420, 440). Mobile ions (425) are in at least one of the first and second layers (420, 440), and the membrane (430) is permeable to the ions. Interfaces of the conductive membrane (430) with the first layer (420) and the second layer (440) are such that charge of a polarity of the ions (425) collects at the interfaces.

Abstract: A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.

Abstract: A nanoscale switching device is provided. The device comprises: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having a non-conducting portion comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field and a source portion that acts as a source or sink for the dopants; and an oxide layer either formed on the first electrode, between the first electrode and the active region or formed on the second electrode, between the second electrode and the active region. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided.

Abstract: A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.

Abstract: Provided are a resistive random access memory device and a method of manufacturing the same. The resistive random access memory device includes a switching device and a storage node connected to the switching device, and the storage node includes a first electrode and a second electrode and a resistance change layer formed of Cu2-XO between the first electrode and the second electrode.

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

Abstract: A type of resistance random access memory structure having the function of diode rectification includes a first electrode, a second electrode and a resistance conversion layer. The resistance conversion layer is disposed between the first electrode and the second electrode; and it includes a first oxidized insulating layer which is adjacently connected to the first electrode; a second oxidized insulating layer which is adjacently connected to the second electrode; as well as an energy barrier turning layer disposing between the first oxidized insulating layer and the second oxidized insulating layer. An energy barrier high can be adjusted and controlled to change the resistance by voltage between the energy barrier turning layer and the first oxidized insulating layer. A fixed energy barrier is formed between the second oxidized insulating layer and the energy barrier turning layer, so that the resistance random access memory element features the function of diode rectification.

Abstract: A nonvolatile memory element includes a variable resistance layer located between a lower electrode and an upper electrode and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer includes at least two layers: a first variable resistance layer including a first transition metal oxide; and a second variable resistance layer including a second transition metal oxide and a transition metal compound. The second transition metal oxide has an oxygen content atomic percentage lower than an oxygen content atomic percentage of the first transition metal oxide, the transition metal compound contains either oxygen and nitrogen or oxygen and fluorine, and the second transition metal oxide and the transition metal compound are in contact with the first variable resistance layer.

Abstract: Provided is a nonvolatile memory element which inhibits deterioration of a oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element. A nonvolatile memory element (12) includes a first electrode layer (105) formed above a substrate (100), a variable resistance layer (106) disposed on the first electrode layer (105), and a second electrode layer (107) disposed on the variable resistance layer (106), and the variable resistance layer (106) has a two-layer structure in which a oxygen- and/or nitrogen-deficient tantalum oxynitride layer (106a) and a tantalum oxide layer (106b) are stacked.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: A nonvolatile memory element includes: a first electrode layer; a second electrode layer; and a variable resistance layer which is placed between the electrode layers, and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrode layers. The variable resistance layer is formed by stacking a first oxide layer including an oxide of a first transition metal and a second oxide layer including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer is larger than a dielectric constant of the first oxide layer; and (2) a band gap of the second oxide layer is smaller than a band gap of the first oxide layer.

Abstract: In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first electrode and the second electrode, and an auxiliary layer between the memory layer and the second electrode. The auxiliary layer provides a multi-bit memory characteristic to the memory layer.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include first, second and third conductive lines disposed at different vertical levels to define two intersections, and two memory cells disposed at the two intersections, respectively. The first and second conductive lines may extend parallel to each other, and the third conductive line may extend to cross the first and second conductive lines. The first and second conductive lines can be alternatingly arranged along the length of third conductive line in vertical sectional view, and the third conductive line may be spaced vertically apart from the first and second conductive lines.

Abstract: The present invention belongs to the technical field of memory storage and specially relates to a NiO-based resistive random access memory system (RRAM) and a preparation method thereof. The RRAM is comprised of a substrate and a metal-insulator-metal (MIM) structure, wherein the electrodes are metal films, such as copper, aluminum, etc., capable of being applied to the interconnection process, and the resistive switching insulator is an Al2O3/NiO/Al2O3 laminated dielectric film. The MIM structure in the invention shows stable switching between the bi-stable resistance states as well as memory features; compared with the RRAM that only uses a single NiO-based dielectric film, the storage window is increased, and the resistance stability is improved. Therefore, the NiO-based RRAM has a good prospect in actual application. The present invention further provides a method for preparing the abovementioned memory storage system.

Abstract: A nonvolatile memory element may include, but is not limited to: a first electrode; a second electrode; and a resistive switching material disposed between the first electrode and the second electrode, wherein at least one of the first electrode or the second electrode includes at least one of a metal cation or metalloid cation having a valence state, oxidation state or oxidation number and wherein the resistive switching material includes at least one of a metal cation or a metalloid cation having the same valence state oxidation state or oxidation number as the at least one of a metal cation or metalloid cation of the at least one of the first electrode or the second electrode.

Abstract: In a variable resistance nonvolatile storage element, an electrode suitable for a variable resistance operation and formed of a metallic nitride layer containing Ti and N is provided. In a nonvolatile storage device including: a first electrode; a second electrode; and a variable resistance layer which is sandwiched between the first electrode and the second electrode and in which a resistance value changes to two different resistance states, at least one of the first electrode and the second electrode is an electrode including a metallic nitride layer containing at least Ti and N, and a mole ratio (N/Ti ratio) between Ti and N in at least a part of the metallic nitride layer, the part being in contact with the variable resistance layer is 1.15 or more and a film density is 4.7 g/cc or more.

Abstract: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

Abstract: A nonvolatile memory element according to the present disclosure includes: a variable resistance element including a first electrode layer, a second electrode layer, and a variable resistance layer which is located between the first electrode layer and the second electrode layer and has a resistance value that reversibly changes based on an electrical signal applied between the first electrode layer and the second electrode layer; and a fixed resistance layer having a predetermined resistance value and stacked together with the variable resistance element. The variable resistance layer includes (i) a first transition metal oxide layer which is oxygen deficient and (ii) a second transition metal oxide layer which has a higher oxygen content atomic percentage than the first transition metal oxide layer. The predetermined resistance value ranges from 70? to 1000? inclusive.

Abstract: In accordance with an embodiment, a non volatile semiconductor memory device includes a substrate, a first electrode, a functional film, and a second electrode. The first electrode is provided on the substrate. The functional film is located on the first electrode and serves as a storage medium. The second electrode is provided on the functional film or in the functional film, and has a convex curved upper surface.

Abstract: Nonvolatile memory devices including a first interlayer insulating film and a second interlayer insulating film separated from each other and are stacked sequentially, a first electrode penetrating the first interlayer insulating film and the second interlayer insulating film, a resistance change film along a top surface of the first interlayer insulating film, side surfaces of the first electrode, and a bottom surface of the second interlayer insulating film, and a second electrode between the first interlayer insulating film and the second interlayer insulating film.

Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

Abstract: A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided.

Abstract: A neuron device includes a bottom electrode, a top electrode, and a layer of metal oxide variable resistance material sandwiched between the bottom electrode and the top electrode, in which the neuron device is switched to a normal state upon application of reset pulse, and is switched to an excitation state upon application of stimulus pulses. The neuron device has a comprehensive response to different amplitude, different width of a stimulus voltage pulse and different number of a sequence of stimulus pulses, and provides functionalities of a weighting section and a computing section. The neuron device has a simple structure, excellent scalability, quick speed, low operation voltage, and is compatible with the conventional silicon-based CMOS fabrication process, and thus suitable for mass production. The neuron device is capable of performing many biological functions and complex logic operations.

Abstract: Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.

Abstract: A large-capacity and inexpensive nonvolatile semiconductor memory device that prevents a leak current and is operated at high speed is implemented with a nonvolatile variable resistive element. A memory cell array includes the nonvolatile variable resistive elements each including a variable resistor composed of a metal oxide film to cause a resistance change according to an oxygen concentration in the film, an insulation film formed on the variable resistor, first and second electrodes to sandwich the variable resistor, and a third electrode opposite to the variable resistor across the insulation film. A writing operation is performed by applying a voltage to the third electrode to induce an electric field having a threshold value or more, in a direction perpendicular to an interface between the variable resistor and the insulation film, and a resistance state of the variable resistor is read by applying a voltage between the first and second electrodes.

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.

Abstract: A resistive random access memory cell over a substrate includes a memory stack structure and a sidewall spacer. The memory stack structure is over the substrate and includes a first electrode layer, a second electrode layer, and a metal oxide layer between the first electrode layer and the second electrode layer. The metal oxide layer has a sidewall. The sidewall spacer is adjacent to the sidewall and has a composition including silicon, carbon, and nitrogen.

Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

Abstract: Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.

Abstract: A memristor includes a substrate having a plurality of protrusions, wherein each of the plurality of protrusions extends in a first direction, a first electrode provided over at least one of the plurality of protrusions, wherein the first electrode conforms to the shape of the at least one protrusion such that the first electrode has a crest, a switching material positioned upon the first electrode; and a second electrode positioned upon the switching material such that a portion of the second electrode is substantially in line with the crest of the first electrode along the first direction, wherein an active region in the switching material is operable to be formed between the crest of the first electrode and the portion of the second electrode that is substantially in line with the crest of the first electrode.

Abstract: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0?x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal portion, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.