Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

Abstract: A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.

Abstract: According to one embodiment of the present invention, an integrated circuit includes a memory cell that includes at least two resistivity changing layers being stacked above each other, each resistivity changing layer serving as a separate data storage layer and having individual data storing properties.

Abstract: Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.

Abstract: The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.

Abstract: A method of forming a layer of material on a sidewall of a via with good thickness control. The method involves forming a layer of material with a conventional deposition process. The material formed on a field region surrounding the via is removed with a sputter etch process. Another layer of material is deposited thereon, wherein the sputter etch-deposition cycle is repeated as necessary to achieve a desired sidewall thickness. With this method, the thickness of the material deposited on the sidewall is linearly dependent on the number of process cycles, thus providing good thickness control. The method may be used to form a resistance variable material, e.g., a phase-change material, on a via sidewall for use in a memory element.

Abstract: An integrated circuit includes a first electrode and a dielectric material layer contacting a first portion of the first electrode. The integrated circuit includes a spacer material layer contacting a sidewall portion of the dielectric material layer and a second portion of the first electrode. The second portion is within the first portion. The integrated circuit includes resistivity changing material contacting the spacer material layer and a third portion of the first electrode. The third portion is within the second portion. The integrated circuit includes a second electrode contacting the resistivity changing material.

Abstract: A phase change memory cell includes a phase change region of a phase change material, a heating element of a resistive material, arranged in contact with the phase change region and a memory element formed in said phase change region at a contact area with the heating element. The contact area is in the form of a frame that has a width of sublithographic extent and, preferably, a sublithographic maximum external dimension. The heating element includes a hollow elongated portion which is arranged in contact with the phase change region.

Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Abstract: Provided are a resistive random access memory device and a method of manufacturing the same. The resistive random access memory device includes a switching device and a storage node connected to the switching device, and the storage node includes a first electrode and a second electrode and a resistance change layer formed of Cu2-XO between the first electrode and the second electrode.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystal line structure.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. A second phase change memory structure is on the first phase change memory structure and electrically connected to the first phase change memory structure, wherein the first or second phase change memory structure includes a cup-shaped heating electrode. A first insulating layer covers a portion of the cup-shaped heating electrode along a first direction. A first electrode structure covers a portion of the first insulating layer and the cup-shaped heating electrode along a second direction. The first electrode structure includes a pair of phase change material sidewalls on a pair of sidewalls of the first electrode structure and covering a portion of the cup-shaped heating electrode.

Abstract: A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by one of the conductive layers. A first electrode structure with a first sidewall and a second sidewall is formed on the stacked structure. A plurality of heating electrodes is placed on the conductive layers and adjacent to the first sidewall and the second sidewall of the first electrode structure. A pair of phase change material spacers is placed on the first sidewall and the second sidewall of the first electrode structure. The phase change material sidewalls cover the plurality of heating electrodes.

Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory device as described above.

Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

Abstract: A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exposed surface. Further, the method may also include forming a layer of phase change material coupled to the exposed surface of the electrode. Various semiconductor devices and additional methods of manufacturing memory cells are also provided.

Abstract: Provided is a non-volatile memory device including a variable resistance material and method of fabricating the same. The non-volatile memory device may include a lower electrode, an intermediate layer on the lower electrode including one material selected from the group consisting of HfO, ZnO, InZnO, and ITO, a variable resistance material layer on the intermediate layer, and an upper electrode on the variable resistance material layer. A memory device having multi-level bipolar switching characteristics based upon the size of the device may be provided.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A memory element which stably performs operations such as data recording and which has a stable structure with respect to heat is provided. A memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and second electrode 6, in which the ion source layer 3 contains any of elements selected from Cu, Ag and Zn, and any of elements selected from Te, S and Se, and the memory layer 4 is made of any of tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide and zirconium oxide, or is made of mixed materials thereof.

Abstract: A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.

Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.