Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.

Abstract: A semiconductor memory device comprising: first and second wirings arranged in a matrix; and a memory cell being provided at an intersecting point of the first and second wirings and including a resistance change element and an ion conductor element connected to each other in a cascade arrangement between the first and second wirings.

Abstract: A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: Disclosed is a semiconductor storage device including a first electrode formed by being embedded in an insulating film formed on a substrate, a second electrode formed to be opposed to the first electrode, a storage layer formed between the first electrode and the second electrode, the storage layer being on a side of the first electrode, an ion source layer formed between the storage layer and the second electrode, and a diffusion prevention layer formed of a manganese oxide layer between the insulating film and the first electrode.

Abstract: Provided are a doped phase change material and a phase change memory device including the phase change material. The phase change material, which may be doped with Se, has a higher crystallization temperature than a Ge2Sb2Te5 (GST) material. The phase change material may be InXSbYTeZSe100?(X+Y+Z). The index X of indium (In) is in the range of 25 wt %?X?60 wt %. The index Y of antimony (Sb) is in the range of 1 wt %?Y?17 wt %. The index Z of tellurium (Te) is in the range of 0 wt %<Z?75 wt %.

Abstract: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain mode in which gain is induced in the current passing between the load and reference terminals; (2) a conductivity modulation mode in which the conductivity of the chalcogenide material between the load and reference terminals is modulated; (3) a current modulation mode in which the current or current density between the load and reference terminals is modulated; and/or (4) a threshold modulation mode in which the voltage required to switch the chalcogenide material between the load and reference terminals from a resistive state to a conductive state is modulated. The devices may be used as interconnection devices or signal providing devices in circuits and networks.

Abstract: A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.

Abstract: A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant conce

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

Abstract: A phase change memory (PCM) device includes a substrate, bottom electrodes disposed in the substrate, a first dielectric layer disposed on the substrate, second dielectric layers, third dielectric layers, cup-shaped thermal electrodes, top electrodes, and PC material spacers. In the PCM device, each cup-shaped thermal electrode contacts with each bottom electrode. Second and third dielectric layers are disposed over the substrate in different directions, wherein each of the second and third dielectric layers covers a portion of the area surrounded by each cup-shaped thermal electrode, and the third dielectric layers overlay the second dielectric layers. The top electrodes are disposed on the third dielectric layers, wherein a plurality of stacked structure composed of the third dielectric layers and the top electrodes are formed thereon.

Abstract: The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (2) comprising the bottom electrode (10), providing on the substrate a dielectric layer (4) comprising a recess (7) containing the metal for forming the resistive layer (11), providing on the substrate a dielectric layer (5) comprising an opening (8) exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.

Abstract: Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and an upper electrode formed on the second phase change layer.

Abstract: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between the third terminal (9) and a second terminal (8) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the third terminal (9) and the second terminal (8). Given pulse voltages are applied between the first terminal (7) and the third terminal (9) and between the third terminal (9) and the second terminal (8) to reversibly change the resistance values of the first and second variable resistors (5, 6), thereby recording one bit or multiple bits of information.

Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

Abstract: A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage layers may contact first sidewalls of each of the at least one first semiconductor layer. A plurality of second semiconductor layers of a second conductivity type, opposite to the first conductivity type, may be interposed between the first sidewalls of each of the at least one first semiconductor layer and the plurality of first resistance variation storage layers. A plurality of bit line electrodes may be connected to each of the plurality of first resistance variation storage layers.

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: A nonvolatile memory device includes: a substrate; a stacked structure member including a plurality of dielectric films and a plurality of electrode films alternately stacked on the substrate and including a through-hole penetrating through the plurality of the dielectric films and the plurality of the electrode films in a stacking direction of the plurality of the dielectric films and the plurality of the electrode films; a semiconductor pillar provided in the through-hole; and a charge storage layer provided between the semiconductor pillar and each of the plurality of the electrode films. At least one of the dielectric films includes a film generating one of a compressive stress and a tensile stress, and at least one of the electrode films includes a film generating the other of the compressive stress and the tensile stress.

Abstract: The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

Abstract: An element structure for a resistance variable type nonvolatile storage device is provided in which enables a reduction in variation in operating voltage and in a leakage current in an off state of an element. The nonvolatile storage device is characterized by including a lower electrode, an upper electrode, and a laminated structure in which at least one amorphous insulating layer and at least one resistance variation layer are laminated between the lower electrode and the upper electrode.

Abstract: A resistive memory device includes: a substrate, an insulation layer arranged over the substrate, a first electrode plug penetrating the insulation layer from the substrate, having a portion protruded out of an upper portion of the insulation layer, and having peaks at edges of the protruded portion, a resistive layer disposed over the insulation layer and covering the first electrode plug, and a second electrode arranged over the resistive layer.

Abstract: A switchable resistive device has a multi-layer thin film structure interposed between an upper conductive electrode and a lower conductive electrode. The multi-layer thin film structure comprises a perovskite layer with one buffer layer on one side of the perovskite layer, or a perovskite layer with buffer layers on both sides of the perovskite layer. Reversible resistance changes are induced in the device under applied electrical pulses. The resistance changes of the device are retained after applied electric pulses. The functions of the buffer layer(s) added to the device include magnification of the resistance switching region, reduction of the pulse voltage needed to switch the device, protection of the device from being damaged by a large pulse shock, improvement of the temperature and radiation properties, and increased stability of the device allowing for multivalued memory applications.

Abstract: An electric element includes: a first electrode; a second electrode; and a variable-resistance film connected between the first electrode and the second electrode. The variable-resistance film includes Fe3O4 as a constituent element and has a crystal grain size of 5 nm to 150 nm.

Abstract: A memory element comprises a first electrode, a second electrode, and a resistance variable film 2 which is disposed between the first and second electrodes to be connected to the first and second electrodes, a resistance value of the resistance variable film 2 varying based on voltage applied between the first and second electrodes, the resistance variable film 2 includes a layer 2a made of Fe3O4 and a layer 2b made of Fe2O3 or a spinel structure oxide which is expressed as MFe2O4 (M: metal element except for Fe); and the layer 2a made of Fe3O4 is thicker than the layer 2b made of Fe2O3 or the spinel structure oxide.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A resistance RAM (ReRAM) device and method of manufacturing the same are presented. The ReRAM exhibits an improved set resistance distribution and an improved reset resistance distribution. The ReRAM device includes a lower electrode contact that has at least one carbon nano-tube; and a binary oxide layer formed over the lower electrode contact. The binary oxide layer is for storing information in accordance to two different resistance states of the binary oxide layer.

Abstract: Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material.

Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (RRAM) that use techniques to provide a memory device with more predictable operation. In particular, forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or through the use of an anneal in a reducing environment. One or more of these techniques may be applied, depending on desired application and results.

Abstract: An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than one bit of information in the resistive memory element.

Abstract: A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the diffusion of metal; a second layer made of porous material on the said first layer; a third layer of metallic material allowing to realize a contact electrode susceptible to spread within the said formed porous material of the second layer. Diffusion of metallic ions within the said second layer is controlled by the joint action of an electric field and temperature. A manufacturing process is also described.

Abstract: A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction.

Abstract: In a resistance change memory (ReRAM) storing data by utilizing change in resistance of a resistance change element, a lower electrode (ground-side electrode) of the resistance change element is formed of a transition metal such as Ni, and an upper electrode (positive polarity-side electrode) is configured of a noble metal such as Pt. In addition, a transition metal oxide film between the lower electrode and the upper electrode is formed of an oxide film (NiOx film) of a transition metal that is of the same kind as the transition metal constituting the lower electrode, for example.

Abstract: A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.

Abstract: A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.

Abstract: In a semiconductor memory comprising a matrix of memory cells each composed of one transistor and one chalcogenide layer as a memory element, no chalcogenide layer is disposed at a joint between an upper electrode wire connected to the chalcogenide layer and another wiring layer.

Abstract: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain mode in which gain is induced in the current passing between the load and reference terminals; (2) a conductivity modulation mode in which the conductivity of the chalcogenide material between the load and reference terminals is modulated; (3) a current modulation mode in which the current or current density between the load and reference terminals is modulated; and/or (4) a threshold modulation mode in which the voltage required to switch the chalcogenide material between the load and reference terminals from a resistive state to a conductive state is modulated. The devices may be used as interconnection devices or signal providing devices in circuits and networks.

Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

Abstract: A memory using a tunnel barrier is disclosed. A memory element includes a tunneling barrier and two conductive materials. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is irreversibly formed for one time programmable memory. The tunneling barrier can be formed by mobile ions combining with complementary ions. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity, multiple states can be created in the memory cell.

Abstract: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix.

Abstract: A phase change material may be formed within a trench in a first layer to form a damascene memory element and in an overlying layer to form a threshold device. Below the first layer may be a wall heater. The wall heater that heats the overlying phase change material may be formed in a U-shape in some embodiments of the present invention. The phase change material for the memory element may be elongated in one direction to provide greater alignment tolerances with said heater and said threshold device.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.

Abstract: A memory device utilizes a phase change material as the storage medium. The phase change material includes at least one of Ge, Sb, Te, Se, As, and S, as well as a nitride compound as a dopant. The memory device can be a solid-state memory cell with electrodes in electrical communication with the phase change medium, an optical phase change storage device in which data is read and written optically, or a storage device based on the principle of scanning probe microscopy.

Abstract: A non-volatile memory semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a PN junction diode formed over a semiconductor substrate. Insulating films may be formed over the PN junction diode and patterned to have via holes. A resistive random access memory including a first metal pattern may be in contact with a first region of the PN junction diode. An oxide film pattern may be formed over the first metal pattern and a second metal pattern formed over the oxide film pattern. The first metal pattern, the oxide film pattern and the second metal pattern may be formed in the via holes.

Abstract: A nonvolatile memory element in which Rb1-yMbyMnO3 having higher insulation properties than Ra1-xMaxMnO3 is inserted between the Ra1-xMaxMnO3 and a metal having a shallow work function or a low electronegativity in order to improve resistance change properties and switching properties and to control the resistance change properties. (In the formulas, Ra and Rb represent rare earth elements and are solid solutions of one or more types of rare earth elements. Average ionic radius of the Rb is smaller than that of the Ra. Ma and Mb represent alkaline earth metals and are solid solutions of one or more types of alkaline earth metals. 0<x, y<1).

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract: A method of fabricating a solid state electrolytes memory device is provided. An insulator layer is formed on a substrate. A conductive layer is formed on the insulator layer. At least two openings partially overlapped and capable of communicating with each other are formed in the conductive layer, so that the conductive layer forms at least a pair of tip electrodes. Thereafter, solid state electrolytes are filled in the openings.

Abstract: The switching element of the present invention is of a configuration that includes: a first electrode (14) and a second electrode (15) provided separated by a prescribed distance; a solid electrolyte layer (16) provided in contact with the first electrode (14) and the second electrode (15); a third electrode (18) that can supply metal ions and that is provided in contact with the solid electrolyte layer (16); and a metal diffusion prevention film (17) that covers points of the surface of the solid electrolyte layer (16) that are not in contact with the first electrode (14), the second electrode (15) or the third electrode (18). This configuration prevents the adverse effect of metal ions upon other elements.