Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.

Abstract: In one aspect, a circuit includes a switching regulator configured to provide power to a load, a current regulator circuit coupled to the load and a response circuit configured to provide a control signal to the switching regulator in response to electrical changes of the current regulator circuit. The control signal changes non-linearly with respect to the electrical changes at the current regulator circuit. In another aspect, a circuit includes an adaptive regulation voltage circuit configured to provide a regulation voltage to a first input of an amplifier to maintain operability of a current regulator circuit. The adaptive regulation voltage circuit replicates electrical characteristics of the current regulator circuit.

Abstract: A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.

Abstract: An LED lamp driven by alternating current includes at least a first constant-current supplying device, at least a second constant-current supplying device and at least an LED load. A terminal of the first constant-current supplying device is connected to the first connecting terminal of the AC power source. A terminal of the second constant-current supplying device is connected to the second connecting terminal of the AC power source. The LED load is connected between the first constant-current supplying device and the second constant-current supplying device in series. Through the current limiting function of the first constant-current supplying device and the second constant-current supplying device, the LED lamp may be protected.

Abstract: An electronic device includes a functional unit and a current compensation unit. The functional unit operates based on a power supplied by an external host through power supply lines and generates a control signal based on an amount of power consumption of the functional unit. The current compensation unit compensates a change in a power supply current based on the control signal, where the power supply current is a current flowing through the power supply lines.

Abstract: A limiter circuit includes a voltage rail having an input and an output, the input receiving an applied input voltage, a switching device in electrical communication with the voltage rail to selective control an electric current flowing through the output of the voltage rail, limiter capacitor in electrical communication with the input of the voltage rail and the switching device, wherein the limiter capacitor and the switching device are in parallel electrical communication between the input and an electrical ground, and a first resistor interposed between the limiter capacitor and the electrical ground, wherein an impedance of the resistor and the limiter capacitor define a time constant for the charging the limiter capacitor, and wherein the time constant of the limiter capacitor controls a voltage applied to the switching device and a current flowing through the output of the voltage rail.

Abstract: An output compensator for a regulator is provided that can improve the dynamic response of a regulator, and which does not require the redesigning of the power conversion stage or control stage of the regulator, but simple circuit connection of the compensator circuit to the output stage of the regulator. The compensator senses an output signal at a passive component at an output of the regulator; generates a compensating signal based on a difference signal, the difference being a difference between a level of a reference signal for the regulator and the sensed output signal; and applies the compensating signal to the passive output component to reduce the difference between the level of the reference signal and the sensed output signal. The passive output component may be, for example, a capacitor or an inductor, depending on the operation of the regulator.

Abstract: A power interface is proposed, which keeps an adjustable power supply circuit in a conducting state even if the average current consumption of an attached load is below the adjustable power supply circuit's holding current requirement. The power interface makes use of the dynamic properties of adjustable power supply circuits. Due to the recovery time of the adjustable power supply circuit, it will stay in the conducting state even if there is no current flowing for a short while. The power interface makes use of this effect by interrupting and re-establishing a current flow from the adjustable power supply circuit.

Abstract: A current injector circuit comprises a clock modulating circuit, a first current injector, a feedback circuit, a first input modulating circuit and a second current injector. The clock modulating circuit receives a clock, a control signal, and an output. The first current injector has an input coupled to the clock modulating circuit, and an output coupled to a power supply terminal for providing a first current. The feedback circuit is coupled between the power supply terminal and another input of the clock modulating circuit. The feedback circuit is for providing the control signal for controlling the clock modulating circuit. The first current injector provides the first current in response to the clock modulating circuit. The first input modulating circuit receives an input signal, the control signal, and an output. The second current injector has an input coupled to the first input modulating circuit, and an output for providing a second current.

Abstract: A circuit arrangement (1) for the regulation of a current (IL) through a load (RL) comprises: a resistance (RS), through which a load current (IL) flows and across which a voltage (VS) drops, which serves as a control variable (X) for the regulation of the load current (IL), a tapping point (P) for a reference voltage (Vref), which serves as a command variable (W) for the regulation of the load current (IL), and a differential amplifier for the amplification of the control deviation (W?X) between command variable (W) and control variable (X).

Abstract: A current sensing circuit can prevent operation error due to a rush current and/or a shifted sense ratio. The circuit includes a power MOSFET, a series combination of a sense resistor and a sense MOSFET, which are connected in parallel to the power MOSFET Qph, a delay circuit for delaying the edges of drive signal, by first delay time, a delay circuit for delaying the edges of the drive signal by a second delay time, logic for combining signals and a current sensing circuit for sensing an electric current of the sense MOSFET based on an electric current of the sense resistor.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A gate drive circuit for a controllably conductive device, such as a triac, includes a trigger circuit for conducting a gate current through a control input of the controllably conductive device, and a sense circuit operable to generate a control signal representative of the magnitude of the gate current. The controllably conductive device is adapted to be coupled in series between an AC power source and an electrical load for controlling the amount of power delivered to the electrical load. The controllably conductive device is operable to change from a non-conductive state to a conductive state in response to the gate current being conducted through the control input. A controller is operable to control the controllably conductive device via the gate drive circuit and to determine, in response to the magnitude of the gate current through the control input of the controllably conductive device, whether the controllably conductive device is presently conducting current to the load.

Abstract: A boosting circuit includes a charge pump circuit; and a power supply circuit configured to supply a power supply voltage to the charge pump circuit. The power supply circuit includes an N-channel transistor connected with a power supply terminal of the charge pump circuit; and a current control circuit configured to control current flowing between the N-channel transistor and the charge pump circuit through the power supply terminal.

Abstract: A self-oscillating switch circuit for amplitude modulation dimming for dimming a LED load. The self-oscillating switch circuit comprises a high-power input terminal (S2) for supplying a first power to the load and a low-power input terminal (S1) for supplying a second power to the load. The switch circuit further comprises a power switch semi-conductor device (Q1) configured for controlling a load current from at least one of the high-power input terminal (S2) and the low-power input terminal (S1) to the output terminal. A control semi-conductor device (Q2) is configured to control the power switch semi-conductor device (Q1) in response to a sensing voltage.

Abstract: A power conversion circuit includes a variable voltage converter (VVC) with a stabilizing means for stabilizing its output voltage. The stabilizing means can be in the form of a diode that clamps the VVC output voltage to the VVC input voltage so that the output voltage does not drop below the input voltage when a load imposes a sudden power demand. The stabilizing means also enables a bypass mode in which transient power can be provided from a power source to an inverter without current flow through the VVC inductor or switches. When embodied as a diode, the stabilizing means can increase the maximum power that can be transferred by the power conversion circuit, improve the power response of the circuit, minimize control instability, and reduce power losses.

Abstract: This switching power supply provides a stable output. In the switching power supply, at least pairs of secondary side coils are connected to each of the center tap rectifier circuits and the secondary side coils of each of the center tap rectifier circuits are disposed in the core portions (cores) of mutually different transformers.

Abstract: A converter circuit includes first and second input terminals for receiving an input current from a current source, a first capacitor connected between the first and second input terminals, a second capacitor having a first terminal which is connected to the second input terminal and a second terminal forming a positive voltage node. First and third semiconductor components are connected in series between the first input terminal and the positive voltage node to form a first node. A series connection of a first inductive component, a first diode and a second inductive component is connected between the second input terminal and the first node. A third capacitor and a third inductive component are included, as are first and second output terminals. The first and the third semiconductor components are configured to control the voltage between the first and second input terminals.

Abstract: A programmable voltage reference includes a temperature compensated current source and a voltage reference circuit. The temperature compensated current source includes an output configured to provide a reference current. The voltage reference circuit includes an input coupled to the output of the temperature compensated current source and a reference output. The voltage reference circuit includes a self-cascode metal-oxide semiconductor field-effect transistor structure that includes a first device that is diode-connected and operates in a weak inversion saturation region and a second device that operates in a weak inversion triode region. A length of the second device is selectable. The voltage reference circuit is configured to provide a reference voltage on the reference output based on the reference current.

Abstract: A voltage converter and a voltage conversion method is disclosed. The voltage converter includes input terminals configured to receive an input voltage. Output terminals are configured to provide an output voltage and an output current. At least one first converter stage is connected between the input terminals and the output terminals, comprising at least one unipolar transistor, and configured to provide a first output current. At least one second converter stage is connected between the input terminals and the output terminals, comprising at least one bipolar transistor, and configured to provide a second output current. A control circuit is configured to control the first output current and the second output current such that there is a first output current range in which the first output current is higher than the second output current.

Abstract: Disclosed is an electronic circuit with a first load terminal, a second load terminal, a supply terminal configured for having a charge storage arrangement connected thereto, and a load transistor, a current sense circuit with a sense transistor, and a start-up circuit with a start-up transistor.

Abstract: Disclosed herein are a DC-DC boost converter circuit, which is capable of preventing power loss and stabilizing switching elements by implementing soft switching and improving efficiency by adding a charge pumping function, and a method for driving the same. The DC-DC boost converter circuit, in which an inductor and an output diode are connected in series and an output capacitor and a load are connected to an output port of the output diode in parallel, includes an output stabilization circuit in which first and second switching elements, a transformer, a plurality of boost capacitors, and a plurality of diodes are connected in series/parallel between the inductor and the output diode.

Abstract: The present disclosure relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE?VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Abstract: One disclosed embodiment is a power conversion circuit including a power conversion bridge between a bus voltage and ground, including a switched node for supplying current to an output circuit. A driver section is configured to drive the power conversion bridge that includes a first section and a second section, the first section being between a negative supply voltage and ground, and the second section being between the switched node and a derived voltage below the switched node, the derived voltage being derived from the negative voltage. In one embodiment, the power conversion bridge includes a high side III-nitride switch and a low side III-nitride switch connected with the high side III-nitride switch to from a half-bridge. In one embodiment, the high side and low side III-nitride switches are depletion mode devices.

Abstract: A voltage regulator includes a source port configured to be coupled to a power source and a load port configured to be coupled to a load. The voltage regulator also includes a constant current source circuit in electrical communication with the source port and the load port configured to regulate current flowing between the source port and the load port. Current flows in both a positive direction and a negative direction between the source port and the load port, and the constant current source circuit regulates the current that flows in the positive direction and the current that flows in the negative direction.

Abstract: A current sense circuit includes a power transistor, a first level shifter, an operational transconductance amplifier (OTA), a second level shifter, and a dummy transistor. The power transistor has a first terminal and a power control terminal coupled to a control voltage. The first level shifter is coupled to the first terminal and pulls up a voltage of the first terminal to an operating voltage. The OTA is coupled to the first level shifter and converts the operating voltage into an operating current. The second level shifter is coupled to the OTA and pulls down the operating voltage to the voltage of the first terminal. The dummy transistor has a dummy control terminal with the control voltage, and a third terminal coupled to the second level shifter and having the same voltage as the voltage of the first terminal.

Abstract: A constant current control circuit is disclosed. Pads are connected with a common power supply terminal. Shunt resistors are located outward of a region containing Pch type MOS transistors. A temperature increase of the shunt resistors due to a temperature increase of the MOS transistors can be suppressed by the above structure. In particular, when the MOS transistor of one circuit system is driven, the shunt resistor of another circuit system is distant from the driving MOS transistor, and thus, it is possible to further suppress the temperature increase of the distant shunt resistor. Moreover, a power supply terminal can be provided as a single common terminal, and the number of terminals can be reduced.

Abstract: A current source circuit has a voltage application terminal that is applied with a prescribed voltage; an output terminal that outputs the current; a first MOS transistor of which a source is connected to the voltage application terminal; a second MOS transistor of which a source is connected to a drain of the first MOS transistor and a drain is connected to the output terminal; a third MOS transistor of which a source is connected to the voltage application terminal; a fourth MOS transistor of which a source is connected to a drain of the third MOS transistor and a drain is connected to the output terminal. The current source circuit, in a state where the bias voltage is applied to the first input terminal such that the predetermined current flows into the first and fourth MOS transistors, controls turning ON/OFF of the second MOS transistor and the third MOS transistor so as to synchronize according to the switch voltage applied to the second input terminal.

Abstract: A voltage generating apparatus including a voltage generator and a current splitter is provided. The voltage generator has an output node, and generates a first output voltage from the output node. The first output voltage rises when the temperature rises and the current flowing from the output end of the voltage generator is fixed. And the first output voltage drops when the temperature is fixed and the current flowing from the output node of the voltage generator rises. The current splitter is used for increasing the current flowing through the current splitter when the temperature rises. Therefore, the rise of the first output voltage of the voltage generator will be restrained, and the temperature compensation can be achieved.

Abstract: A circuit includes a supply voltage and a control current line including two resistors. A sink current line branches off from the control current line between the resistors. A current sink transistor has an emitter that is connected to the sink current line and a collector that is connected to ground via a first further resistor. At least one reference transistor has an emitter that is connected to its base, to the supply voltage via a second further resistor and to the base of the current sink transistor. The collector of the reference transistor is connected to ground or to an emitter of a further reference transistor, which is switched in a manner similar to the first reference transistor.

Abstract: A voltage converter to convert a high voltage to a low voltage is provided. The voltage converter comprises: a current mirror, a current bias, a plurality of loads and a low voltage output. The current mirror comprises a first PMOS and a second PMOS, wherein the source of the first PMOS and the second PMOS receive a high voltage input which is a supply voltage of the current mirror, and the gate of the first PMOS is connected to the drain of the first PMOS. The current bias is connected between the drain of the first PMOS and a ground potential. The plurality of loads are parallel connected between the drain of the second PMOS and the ground potential. And the low voltage output connected to the drain of the second PMOS.

Abstract: Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor.

Abstract: A communication device, includes a CMOS type inverter configured to transfer a signal, the signal being transferred and received between an electronic device and a control part able to communicate with the electronic device whose electric power supply is a rechargeable battery; and a regulator configured to generate a regulated voltage, the regulated voltage being formed by decreasing an electric power supply voltage of the electronic device, wherein the regulator includes a depletion type NMOS transistor where a drain is connected to a high electric potential side of the electric power supply voltage and a gate and a source are mutually connected, and a capacitive element having an electrode connected to the source side and another electrode connected to a low electric potential side of the electric power supply voltage, wherein a voltage of the capacitive element is supplied across both ends of the inverter.

Abstract: Embodiments of the invention concern a circuit for pulling a potential at a node towards a feed potential which is present at a potential feed. The circuit has a first transistor with a controllable conductive path and in addition a resistive element. The controllable conductive path of the first transistor and the resistive element are coupled in series between the potential feed and the node. Furthermore, the circuit has a control element configured to control the first transistor so that a resistance of the controllable conductive path of the first transistor can be changed depending on a voltage drop at the resistive element. Furthermore, a method for pulling a potential at a node towards a feed potential and an integrated circuit with a pad which is pulled to the feed potential in the absence of an information carrying signal which is received or send by a functional circuitry of the integrated circuit.

Abstract: Disclosed are a circuit and a method for adaptively biasing a voltage regulator with minimal output overshoot. The circuit includes an adaptive bias current mirror circuit further including a first transistor and a second transistor, the first transistor and the second transistor having source nodes coupled to a drain node of the first transistor. The circuit includes a common node coupled to the source node of the first transistor and the source node of the second transistor, wherein a source degenerate resistor is coupled to the adaptive bias current mirror circuit and is coupled to the common node and wherein the source degenerate resistor is configured to limit an output peak current of the voltage regulator circuit.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: Provided is a constant current circuit capable of supplying a stable constant current. Even when K values of NMOS transistors vary due to manufacturing fluctuations in semiconductor devices, a voltage generated across a resistor is always a threshold voltage difference between the NMOS transistors, and thus hardly varies. Even when the K values of the NMOS transistors vary due to a change in temperature, the voltage generated across the resistor is always the threshold voltage difference between the NMOS transistors, and thus hardly varies.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: A current source contains a first switching element which is provided with a control input and is embodied and arranged in such a way that an output flow on an output side of a current source can be adjusted according to a control signal at the control input. The current source also contains a reference resistance that is electrically coupled to a first switching element in such a way that a potential difference above the reference resistance represents the output flow. The adjustment signal of a regulator unit depends on the voltage difference above the reference resistance, is the control signal of the first switching element, and contains a time function element which limits a first value of the output flow to a maximum duration and then reduces the value of the output flow.

Abstract: An arrangement having a first converting element configured to convert an input current linearly into an auxiliary current, a second converting element configured to convert the auxiliary current into an output voltage, and a separating element configured to separate slow changes of the auxiliary current from fast changes of the auxiliary current, wherein the first, second, and separating elements are arranged as a dynamic control loop regulating the input current with the slow changes.

Abstract: Apparatus and methods of controlling operating states of multi-stable electronic circuits are disclosed. In one aspect, an apparatus includes a bandgap reference circuit having an operating state and a latched off state. The bandgap reference circuit includes an amplifier to provide a bandgap reference voltage when the bandgap reference circuit is in the operating state. A state control circuit is also included and is coupled to sense an output signal of the bandgap reference circuit. The state control circuit is also coupled to provide a drive signal to an input of the amplifier in response to the sensed output signal. The drive signal is coupled to cause the bandgap reference circuit to avoid the latched off state.

Abstract: A reference current bias circuit includes a self-bias circuit configured to provide a bias current to an amplifier; a basic bandgap circuit coupled to inputs of the amplifier; a startup circuit configured to support an initial operation of the amplifier; a temperature compensator configured to include a first mirroring unit for mirroring current according to a positive temperature coefficient characteristic from the basic bandgap circuit; and a second mirroring unit for mirroring current according to a negative temperature coefficient characteristic from the basic bandgap circuit, and to provide a reference current by combining the current of the first mirroring unit and the current of the second mirroring unit; and a reference current mirroring unit configured to generate reference current biases based on the reference current from the temperature compensator.

Abstract: A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (IREF).

Abstract: A disclosed voltage comparison circuit for detecting a voltage difference of two input signals includes one or more differential amplifier circuits, each of which has a differential pair of first and second input transistors each having an electrode to which a corresponding one of the input signals is input, a constant current circuit configured to generate constant current according to a control signal and supply the constant current to the first and second input transistors, and a first resistor connected between the constant current circuit and the first input transistor; and a current control circuit configured to control a value of the first constant current. The current control circuit controls the value so that a voltage difference between both ends of the first resistor becomes equal to a predetermined value.

Abstract: An output circuit includes a bias circuit that operates when a power supply voltage equal to or larger than a predetermined voltage is applied, a differential amplifier circuit that outputs signals according to input differential signals upon receiving a bias current or bias voltage generated when the bias circuit is operated, an output stage circuit that receives differential signals according to an output from the differential amplifier circuit and outputs output signals according to the differential signals, the output stage circuit having fewer number of stages of elements connected in series than the bias circuit, and a pull-down circuit that forcibly sets a level of one of the differential signals received by the output stage circuit to a ground voltage to fix the level of the output signals output from the output stage circuit when the bias current or the bias voltage generated by the bias circuit is not supplied.

Abstract: Embodiments of methods and apparatus for modulating a power source are disclosed. In some embodiments, a method may comprise predicting, by a current control logic, a potential voltage transient on a power supply bus, and modulating, by the current control logic, a current source, based at least in part on said predicting, to control the predicted voltage transient. Additional variants and embodiments may also be disclosed and claimed.

Abstract: A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path connected in series with a resistor between the power supply voltage and ground. This startup current is conducted via a diode-connected MOS transistor in a first leg of a current mirror. Temperature compensation is maintained by a reference leg in the current mirror that includes a bipolar transistor having an emitter area N times larger than that of a bipolar transistor in a second leg of the current mirror, to establish a temperature-compensated current in the reference leg. A compensation capacitor connected between the collector and base of a bipolar transistor in the first leg suppresses oscillation, and can be modest in size due to the Miller effect.

Abstract: A digital control switching power supply unit converts an input voltage into a desired output voltage using a digitally controlled pulse width modulation (PWM) signal according to a switching cycle. The power supply unit includes an analog-to-digital converter (ADC). The ADC converts a result of a comparison between an output voltage and a reference voltage to a digital signal during a conversion cycle. The ADC includes a circuit for outputting a phase difference between a switching cycle and the conversion cycle, and a delay circuit. The delay circuit generates a delay output current based on a result of the comparison and the phase difference and determines the conversion time delay according to the delay output current. The delay circuit also generates a delay reference current based on the reference voltage and the phase difference and determining the duration of the conversion cycle according to the delay reference current.

Abstract: Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.

Abstract: Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal.