Abstract: A current-generator circuit is for generation of an output current of a value that is configurable as a function of a configuration signal. The circuit may have a first reference resistor element traversed by an intermediate current, the value of which is a function of a reference current, for supplying a first reference voltage. The circuit may also include a resistive divider stage receiving the configuration signal and supplying a second reference voltage as a function of the first reference voltage and of the configuration signal. A second reference resistor element supplies, as a function of the second reference voltage (Vref2), the output current on the output terminal. The value of resistance of the second reference resistor element may be matched to a respective value of resistance of the first reference resistor element.

Abstract: There are provided a level shifter circuit and a gate driver circuit including the same. The level shifter circuit includes: a plurality of switching devices connected to a predetermined DC power supply through a resistor and operated by different driving signals; a gain conversion unit operated by first signals output from the plurality of switching devices, respectively, and generating second signals having a level within a predetermined range of the first signals; and a noise removal unit connected to at least one output terminal among the plurality of switching devices to prevent malfunctioning of the gain conversion unit, wherein the gain conversion unit inputs the second signals to a high side gate driver circuit through an inverter circuit.

Abstract: A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup.

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract: High linearity is essential in audio circuitry. As sampling rates for audio applications are needed, high speed and high linearity are needed in analog and mixed signal portions of audio circuitry such as in current mirrors. A current mirror employs two current paths in an output. The first current path is driven by a fast acting transistor through a resistor. The second current path is driven by a differential amplifier coupled to another transistor through another resistor. The second current path is used to maintain linearity by causing the voltage across both transistors to be the same.

Abstract: A driving circuit is disclosed that has low power consumption and supplies a current to a load. The driving circuit includes a constant current circuit section to generate and output a predetermined constant current, a current mirror circuit section to generate a current proportional to an input current supplied from the constant current circuit section and supply the current to the load, and a constant voltage supplying circuit section to generate a constant voltage and supply the constant voltage to a series circuit of the load and an output transistor of the current mirror circuit. The constant voltage supplying circuit section gene-rates the constant voltage so that an output voltage of the current mirror circuit section equals an input voltage of the current mirror circuit section.

Abstract: A temperature sensing device includes a bandgap voltage generator, N mirror current sources, a temperature voltage generator, and a temperature calculating unit. The mirror current sources mirror N mirror currents according to a positive temperature coefficient current. The temperature voltage generator sets the conducting number M of the mirror current sources based on a control signal, so as to generate a temperature voltage. The temperature calculating unit gradually counts the control signal and compares a potential of the temperature voltage with a potential of a reference voltage generated by the bandgap voltage generator after counting the control signal, so as to calculate and obtain temperature information. Thus, the temperature sensing device controls the conducting number M of the mirror current sources to generate the temperature voltage instead of applying serially-connected resistors, so as to reduce a circuit area of the temperature sensing device and reduce noise.

Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.

Abstract: A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. In another aspect, a voltage reference circuit output is coupled to an NMOS gate in saturation mode connected to another voltage reference circuit.

Abstract: The present invention discloses precharge circuits and methods for DC-DC boost converters. In one embodiment, a precharge method for a DC-DC boost converter having a current mirror circuit that includes a reference transistor and a power transistor, can include: (i) maintaining a reference current flowing through the reference transistor as substantially constant; (ii) maintaining a drain-source voltage of the reference transistor and a drain-source voltage of the power transistor as substantially equal; and (iii) obtaining a substantially constant mirror current by reflecting the reference current through the power transistor to operate as a precharging current of a precharge circuit.

Abstract: A current mirror circuit includes an input portion configured to conduct a bias current, and a first current source circuit coupled to the input portion and configured to generate the bias current, and vary the bias current over a range of currents based on a first group of weightings associated therewith. The current mirror circuit also includes an output portion configured to conduct an operational current, wherein the output portion is coupled to the input portion, and a second current source circuit coupled to the output portion and configured to generate the operational current, and vary the operational current over a range of currents based on a second group of weightings associated therewith. The first group of weightings and the second group of weightings are different.

Abstract: A bootstrap circuit for a voltage converter includes a bootstrap capacitor, a stable current module for generating a stable output current according to a stable output voltage, a current mirror module having a first branch circuit for generating a current signal according to the stable output current, and a charge module including a cascode transistor module including a plurality of transistors serially connected and a charge resistor for generating a conduction voltage according to the current signal, and an output circuit coupled to the current mirror module and the cascode transistor module for outputting the conduction voltage to charge the bootstrap capacitor.

Abstract: A constant current circuit includes a depletion type MOS transistor, a first current mirror circuit, and a second current mirror circuit. The first and second current mirror circuits each include first and second MOS transistors where a gate of the first and second MOS transistors is connected to a drain of the first MOS transistor. A third MOS transistor has a gate connected to one terminal of a resistor and to the drain of the first MOS transistor of the first current mirror circuit, a source connected to a ground terminal, and a drain connected to an output terminal of the second current mirror circuit.

Abstract: An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

Abstract: An adjustable shunt regulator circuit has two current paths in parallel, with each current path having a bipolar transistor therein with the bases of the bipolar transistors of the two current paths connected in common. One of the current paths has a high impedance node. A MOS transistor has a gate connected to the high impedance node, and a source and a drain. A resistor divide circuit is connected in parallel to the source and drain of the MOS transistor and provides the output of the regulator circuit. The resistor divide circuit has a first resistor connected in series with a second resistor at a first node. A feedback connects the first node to the bases of the bipolar transistors connected in common of the two current paths.

Abstract: A semiconductor integrated circuit includes constant current circuit, starter circuit and power supply start-up circuit. In the constant current circuit, first current mirror circuit includes first and second transistors, and second current mirror circuit includes third and fourth transistors that are connected to first and second nodes. In the starter circuit, a potential of first node controls sixth transistor, seventh transistor is connected to third node, gate electrode of the seventh transistor is at ground potential, a capacitance element is connected to fourth node, and a potential of fourth node controls fifth transistor, which supplies start-up current to the constant current circuit via second node. In the power supply start-up circuit, source electrode of eighth transistor is fixed at power supply voltage, gate electrode is at ground potential, and drain electrode supplies power to the other circuits.

Abstract: There is provided a bias circuit including a power amplifier in which influence of variation of a gate length L is reduced and variation of a gain among products is low. Two NPN- and PNP-type current mirror circuits 101 (NPN type) and 102 (PNP type) are inserted on an input side of a bias circuit 103. It is designed that a gate length of a transistor Q1 on an output side of the current mirror circuit 101 is longer than that of the other transistor. In this manner, even when an error is generated, influence of the error can be suppressed to be small.

Abstract: A method and circuit for providing a switched current source output has a precharge mode, in which a charge storage device is charged to a reference voltage, and the gate of an output transistor is discharged. In a discharge mode, the charge storage device is discharged to the gate of the output transistor to raise the gate voltage by an amount depending on the charge flow.

Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.

Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Abstract: The load driving device disclosed in the specification includes a controller to generate a first control signal based on an input signal, a first output transistor to supply an output current to a load according to the first control signal, a first dividing circuit to output a first divided voltage by dividing a voltage across a first primary electrode and a second primary electrode of the first output transistor by a first transistor and a second transistor connected in serial, a first voltage generating circuit to output a first reference voltage, and a first comparator to supply a first over current detection signal to the controller based on the first reference voltage and the first divided voltage.

Abstract: A system and a method are disclosed for using driving capacitors to dynamically bias an amplifier in a stage of a pipeline analog-to-digital converter (ADC). The drain of the amplifier is connected to a sink transistor, and the driving capacitors are used to raise or lower the voltage at the gate of the sink transistor. The driving capacitors can be used in this manner to rapidly power the amplifier on and off to save power and/or to selectively boost the drain current of the amplifier to improve the response time of the pipeline ADC stage.

Abstract: Apparatus for voltage regulation circuits and related operating methods are provided. An exemplary voltage regulation circuit includes a voltage regulation arrangement that provides a regulated output voltage based on an input voltage reference, a phase compensation arrangement coupled to the voltage regulation arrangement and configured to increase a phase margin of the voltage regulation arrangement, and detection circuitry coupled to the phase compensation arrangement. The detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current that is less than a threshold value.

Abstract: Provided is a constant current circuit capable of low current consumption operation, which is prevented from repeating a start-up state and a zero steady state and entering an oscillating state when power is activated. When power is activated, until a node (A) reaches a start-up state, an excitation current is continued to be supplied to a node (B), to thereby reliably start up the constant current circuit in a short period of time without repeating the start-up state and the zero steady state.

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract: A current mirror apparatus includes an input stage receiving an input current, Iin, and no additional bias current. The apparatus includes at least one output stage coupled to mirror the input current as an output current Iout. The input and output stages include insulated gate transistors. A minimum required voltage drop (Vin) across the input stage is approximately 2Von+2Vth, wherein Vth is a threshold voltage of a selected one of the insulated gate transistors, wherein Von is a drain-to-source saturation voltage of the selected transistor. A minimum required voltage drop (Vout) across the output stage is approximately 2Von.

Abstract: In aspects of the invention, a photocoupler output signal receiving circuit includes a first constant current circuit, connected between an input terminal and the high potential side of a direct current power source, that discharges current, a second constant current circuit, connected between the input terminal and the low potential side of the direct current power source, that takes in current, and switching elements that operate the first and second constant current circuits in a complementary way, wherein the switching elements are operated so that current is taken in by the second constant current circuit after a photocoupler is turned on, and are operated so that current is discharged by the first constant current circuit after the photocoupler is turned off, and a discharge current value in a current discharge period is reduced after a certain period elapses from the start of discharging.

Abstract: A temperature compensated bandgap reference circuit includes a bandgap voltage generator having a temperature dependent signal output and a correction circuit coupled to the output of the bandgap voltage generator and generating a second order quadratic signal which is complementary to the signal output.

Abstract: A temperature independent type reference current generating device and methods thereof. A temperature independent type reference current generating device may include a first reference current generator generating a first reference current having a first element decreasing according to a temperature, a second reference current generator generating a second reference current having a second element increasing according to the temperature, and/or mirroring and outputting a second reference current and/or a mirrored second reference current. A temperature independent type reference current generating device may include a first current mirror mirroring a first reference current and/or outputting a mirrored first reference current, and a second current mirror adding a mirrored first reference current and a mirrored second reference current, and/or mirroring a result of an addition to output a mirrored result as an output reference current.

Abstract: Provided is a constant current circuit in which an enhancement N-channel transistor can operate in a weak-inversion state even at high temperatures. A constant current circuit includes a current mirror circuit, a constant-current generation block circuit, and an off-leak circuit, wherein the off-leak circuit is constituted by a first enhancement N-channel transistor having a gate and a source connected to an earth terminal and a drain connected to an output of the constant current circuit. This suppresses an increase in a gate-to-source voltage of the enhancement N-channel transistor which generates a constant current, thereby maintaining its operation in a weak-inversion state.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A circuit for providing a reference voltage can be widely used in audio applications. However, at startup an abrupt start in the reference signal can cause undesirable audible artifacts. A circuit employing feedback of a reference voltage to control the charging of a capacitor which provides the reference voltage can be used to provide a smooth startup to the reference voltage. The circuit contains a differential pair for steering a fixed current source from one path to another as the reference voltage increases. The steered current can then be mirrored into one ore more current mirrors where the newly mirrored current can be squeezed to zero when the difference between a desired reference voltage and the reference voltage approaches zero. This newly mirrored current can be used to charge a capacitor which is used to provide the reference voltage.

Abstract: Disclosed is a low voltage detection circuit. The low voltage detection circuit includes, a voltage comparison circuit, an output stage, an electric current circuit, and a judgment circuit. When the voltage comparison circuit detects that the voltage of the detection target is a predetermined voltage value or less, an output state of the output stage is promptly changed. When the voltage comparison circuit detects that the voltage of the detection target is a predetermined voltage value or more, the output state of the output stage is changed after a delay time obtained by the electric current circuit.

Abstract: In a circuit and method for correcting a delay variation of a subthreshold CMOS circuit operating in a subthreshold region, a power supply voltage controlling circuit is provided for supplying a controlled output voltage to a subthreshold digital CMOS circuit as a controlled power supply voltage. The subthreshold digital CMOS circuit includes CMOS circuits each having a pMOSFET and an nMOSFET and operating in a subthreshold region with a predetermined delay time, and further includes a minute current generator circuit generating a predetermined minute current based on a power supply voltage, and a controlled output voltage generator circuit generating a controlled output voltage for correcting a variation in the delay time based on a generated minute current and supplying the controlled output voltage to the subthreshold digital CMOS circuit as a controlled power supply voltage including a change in each threshold voltage of the pMOSFET and the nMOSFET.

Abstract: A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.

Abstract: A low noise reference voltage circuit without using an amplifier inside is capable of transforming a current IPTAT in positive proportion to absolute temperature into a voltage VPTAT in positive proportion to absolute temperature, and outputting it to a ring oscillator. The low noise reference voltage circuit improves a degradation of noise performance compared with a conventional band-gap reference voltage circuit and is in characteristic of low noise and higher PSRR.

Abstract: A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.

Abstract: A startup circuit for starting up a self-supplied voltage regulator which initiates startup by applying a voltage from a voltage supply to the startup circuit thus causing a voltage at an output node to rise. This rise will start the operation of the differential amplifier of the voltage regulator. When the voltage at the output node has reached the desired final output voltage, the startup circuit disconnects from the voltage regulator. The criterion for switching off the startup circuit is determined by a comparator which compares the output current capability of the voltage regulator with its output current plus the startup current. Inputs to the differential amplifier, such as the reference voltage, derive their power from the output node.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: A semiconductor device and a layout method of the same reduce a mismatch in a semiconductor device. The semiconductor device includes a first transistor unit providing a first path of current and a second transistor unit designed in a mirror structure to the first transistor unit and providing a second path of current. The layout of the second transistor unit has a shape identical to the first transistor unit and shifted in a first direction. The layout of the semiconductor device reduces a mismatch of the transistors occurring when masks are combined, and thereby reduces their offset.

Abstract: A reference voltage generation circuit includes a current-mirror circuit formed of a plurality of MOS (Metal Oxide Semiconductor) transistors each having a source terminal connected to a power source and a gate terminal connected to with each other; and a plurality of transistors each connected to a drain terminal of each of the MOS transistors of the current-mirror circuit for controlling the current-mirror circuit, so that an output current of the current-mirror circuit is converted to a voltage to be output as a reference voltage. Each of the MOS transistors of the current-mirror circuit has the drain terminal connected to a collector terminal of each of the transistors. Accordingly, when a voltage of the power source varies, it is possible to maintain a collector voltage of each of the transistors at a specific level and a collector current of each of the transistors constant.

Abstract: This current-voltage converter(22) with a current reflector, the input current including a fixed component and a variable component, includes: an input (24) for the current to be converted; an output (26) for the converted voltage; a resistor (36) for current-voltage conversion arranged between the output (26) and the ground, the input (24) being connected to the output (26) for the circulation of the current to be converted in the resistor (36); and a current reflector circuit (38) including two constant current sources (40, 42) , each connected between the output (26) and a respective reference voltage (32, 34). This converter (22) also includes a cascode stage (44, 46) , mounted in series with each constant current generator (40, 42) in order to impose a constant potential difference on the terminals of each constant current generator (40, 42) regardless of the output voltage.

Abstract: A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: A circuit includes a first PMOS transistor and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.

Abstract: A clock generation circuit is provided, having a bandgap reference circuit, a frequency controlled resistor, a comparison circuit and a voltage controlled oscillator. The bandgap reference circuit generates a first voltage. The frequency controlled resistor is coupled to a first node to provide a second voltage. The comparison circuit generates a first current according to a difference between the first voltage and the second voltage. The voltage controlled oscillator outputs first, second and third output clocks according to a third voltage on a second node, wherein the third voltage is generated according to the first current, and the second and third output clocks are fed back to the frequency controlled resistor such that the frequency controlled resistor converts the first current into the second voltage according to the second and third output clocks.

Abstract: A current mirror circuit exhibits improved current matching by applying a switching signal to ground path switches in series with transistors in both a reference path and an output path of the current mirror. The switching signal may comprise a high-frequency signal, which may be phase modulated. A plurality of matched, parallel-connected output transistors may be selectively enabled by qualifying the switching signal applied to each corresponding series-connected ground path switches by decoded digital modulation data. In one embodiment, the modulation data is decoded to thermometer-coded representation. In one embodiment, the switching signal path is identical to the reference and output circuits.

Abstract: A temperature compensated current source forms an uncompensated source current that is proportional to a reference voltage applied to an impedance, wherein the impedance varies with temperature. A temperature compensation current is formed that is proportional to absolute temperature (IPTAT). The uncompensated source current and the temperature compensation current is combined to form a temperature compensated source current and provided as an output of the current source.