Abstract: A system for analyzing electronic devices includes an input station, a transport apparatus, an electric machine interface station, an electric machine interface, a support structure and first and second thermal components. The input station receives a plurality of electronic devices and the transport apparatus transports each of the electronic devices from the input station to the electric machine interface station. The electric machine interface engages the electronic device when the electronic device is at the electric machine interface station, and is disengageable from the electronic device for the electronic device to be transportable by the transport apparatus away from the electric machine interface station. The first and second thermal components are located on opposing sides of the electronic device when the electronic device is at the electric machine interface station to simultaneously transfer heat to or from the electronic device.

Abstract: A nest (1) comprising, a fix part (3), and a movable part (5), wherein the fix (part 3) and movable part (5) are configured to cooperate so as to define a (pocket 7) which can receive at least a part of an electrical component (25), wherein the movable part (5) is moveable between a first position and a second position, wherein in the first position the pocket (7) is open so that at least part of the electrical component can be moved into the pocket (7), and in the second position the pocket (7) is closed so that the at least part of the electrical component (25) positioned in the pocket is secured within the pocket, wherein the nest (1) further comprises a biasing means (9) which is arranged to bias the movable part (5) towards its second position. There is further provided a nest assembly, a component handling assembly, and a table comprising said nest.

Abstract: An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die (157) and surrounding scribe grid (156) to a test head (155) which is positioned over a wafer (160) in alignment with a die under test (163) and surrounding scribe grid (161, 165), such that one or more optical deflection mirrors (152, 154) in the test head scribe grid (156) are aligned with one or more optical deflection mirrors (162, 164) in the scribe grid (161, 165) for the die under test (163) to enable optical die probe testing on the die under test (163) by directing a first optical test signal (158) from the production test die (157), through the first and second optical deflection mirrors (e.g., 152, 162) and to the first die.

Abstract: A testing device is disclosed, including a system circuit board, a first chip component, a supporting structure, a circuit board and an interposer. The system circuit board has a surface where the first chip component is disposed. The first chip component is connected to the system circuit board. The supporting structure is disposed on the surface and surrounds the first chip component; the circuit board is fixed on the supporting structure and keeps distance from the first chip component. The circuit board has a connector for connecting to a chip component that is to be tested. The interposer is located between the circuit board and the first chip component. The circuit board is connected to the first chip component via the interposer. The first chip component need not connect to the chip component to be tested, so is less liable to be damaged by the frequent testing.

Abstract: A method for temporary electrical contacting of a component arrangement with a plurality of contact surfaces is described. A connection support includes a plurality of connection surfaces, on which contact protrusions are disposed. The connection support and component arrangement are brought together in such a way that the connection surfaces and the associated contact surfaces overlap in a top view and the contact protrusions form an electrical contact with respect to the contact surfaces in order to achieve electrical contacting of the component arrangement. Subsequently the connection support and the component arrangement are separated from each other.

Abstract: Providing a test head capable of suppressing a probe card from bending. The test head 40 comprises: a test head main body 51 having a frame 51; an interface apparatus 60 electrically connecting a probe card 20 and the test head main body 50 with each other; and a brake unit 80 positioned between the probe card 20 and the frame 51 to transmit a pressing force F applied to the probe card 20 to the frame 51.

Abstract: The device for checking electronic cards includes a base in which conductive nails are arranged pointing upwards, and a cover, also fitted with nails pointing downwards in the closed cover position. The cover is mobile in horizontal translation between an open position and an intermediate position. The device can also include a vertical translation mechanism capable of bringing the nails arranged in the cover closer to the nails arranged in the base so as to allow contact of the nails on the two faces of an electronic card. The invention also relates to a method of opening and a method of closing such a device.

Abstract: A substrate evaluation apparatus and method which includes a substrate storage portion accommodating a substrate, first and second fastening portions are arranged in the substrate storage portion and are each fastened to a side of the substrate, a driving portion driving the first and second fastening portions, and a measurement portion measuring electrical characteristics of the substrate through application of an electrical signal to the substrate.

Abstract: An IC current measuring apparatus is provided between an IC and a substrate. The IC current measuring apparatus electrically connects each of a plurality of IC-facing terminals and a different one of a plurality of substrate-facing terminals. Especially, resistances are each inserted into a path between an IC terminal targeted for measurement and a substrate terminal corresponding thereto. Furthermore, the IC current measuring apparatus is provided with terminals each used to measure a voltage between both ends of an inserted resistance corresponding thereto. Accordingly, a measurer who measures current flowing through an IC-facing terminal can measure the current flowing through the IC-facing terminal by providing the IC current measuring apparatus between the IC targeted for measurement and the substrate and measuring a voltage between both ends of an inserted resistance corresponding to the IC terminal through which current he/she wishes to measure flows.

Abstract: A jig for use in a semiconductor test includes: a base on which a probe pin and an insulating material are placed, the insulating material surrounding the probe pin in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are placed. The stage is capable of holding a test object on a surface of the stage facing the base. When the base and the stage move in a direction in which they go closer to each other while the test object is placed on the stage, the probe pin comes into contact with an electrode formed on the test object and the insulating material comes into contact with the test object.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: [Problem] A test carrier able to secure a high air-tightness is provided. [Solution] A test carrier 10 comprises a cover member 50A and a base member 20A which are bonded together while sandwiching a die 90 between them. ultraviolet rays can pass through the cover member 50A.

Abstract: A method for testing a plurality of semiconductor devices arranged on a strip may include forming an array of semiconductor devices on a frame, wherein contact pads of adjacent semiconductor devices are shorted, partially cutting the strip to electrically isolate individual semiconductor devices in the array, placing the strip on an adhesive tape configured to withstand low temperatures (e.g., below ?20° C. or below ?50° C.), arranging the strip and tape on a test chuck, exposing the test chuck, strip, and tape to temperatures below an ambient temperature and testing the plurality of semiconductor devices while exposed to a low temperature. In one embodiment a KAPTON™ film is used as the adhesive tape.

Abstract: A switch probe for use in a substrate inspection device to inspect a substrate includes a first tubular element, a first rod element partially accommodated in the first tubular element, and pressed into the first tubular element when the certain part is mounted for substrate inspection, a second tubular element fixed in the first tubular element, a second rod element partially accommodated in the second tubular element which is inside the first tubular element, and contacting with the first rod element when the first rod element is pressed into the first tubular element, and a fixing mechanism configured to temporarily fix the second rod element in a position so that the second rod element does not contact with the first rod element even when the first rod element is pressed into the first tubular element.

Abstract: The invention relates to a base element (ST1, ST2, ST3) for receiving an overvoltage protective module (M1, M2, M3) for use in a bus system, having a first bus connection arrangement (BK1) for contacting a first bus potential (L1), a second bus connection arrangement (BK2) for contacting a second bus potential (L2), a third bus connection arrangement (BK3) for contacting a signal bus (L3), wherein the signal bus in a first state indicates the occurrence of a fault and in a second state indicates the non-occurrence of a fault, wherein a fault indicates a missing or incorrectly received or faulty overvoltage protective module (M1, M2, M3), wherein the first and second bus potential are to be used to supply arrangements on the overvoltage protective module (M1, M2, M3), wherein the base element further comprises an electronic monitoring arrangement (UE1), wherein the electronic monitoring arrangement (UE1) identifies whether an overvoltage protective module (M1, M2, M3) is received, wherein, if an overvoltage pr

Abstract: A test assembly (12) for testing a device (10) having a heat spreader (20), a package substrate (18) having a substrate ground (18G), and a grounding conductive segment (44A), includes (i) an input conductive segment (38) that is electrically connected to the heat spreader (20), (ii) a test board (28) having a board ground (30), and (iii) a control system (34) that is electrically coupled to the input conductive segment (38) and the board ground (30). During testing, the device (10) is positioned so that the substrate ground (18G) is electrically connected to the board ground (30). Additionally, the control system (34) directs a test current to one of the input conductive segment (38) and the board ground (30) to test the effectiveness of the grounding conductive segment (44A) including a first electrical interface (45A).

Abstract: Systems and methods for simultaneous optical testing of a plurality of devices under test. These systems and methods may include the use of an optical probe assembly that includes a power supply structure that is configured to provide an electric current to a plurality of devices under test (DUTs) and an optical collection structure that is configured to simultaneously collect electromagnetic radiation that may be produced by the plurality of DUTs and to provide the collected electromagnetic radiation to one or more optical detection devices. The systems and methods also may include the use of the optical probe assembly in an optical probe system to evaluate one or more performance parameters of each of the plurality of DUTs.

Abstract: Disclosed is a test structure that can be used to characterize a specific interface resistance within a multi-layer conductive structure, such as a multi-layer ohmic contact. In the test structure first and second transmission line model (TLM) structures both incorporate a row of essentially identical contact pads separated by spaces with progressively increasing lengths. Conductive mesas, also with progressively increasing lengths, are positioned within the spaces between all but the initial pair of adjacent contacts pads. The first and second TLM structures differ only with respect to the presence of a single conductive layer on each of the conductive mesas. System, method and computer program product embodiments are able to extract resistance parameters associated with the first and second TLM structures, including conductive mesa to conductive layer interface resistances, based current-voltage measurements acquired from both of the TLM structures.

Abstract: An object of the invention is to provide an inspection device which has a function of preventing electric discharge so that an absorbed current is detected more efficiently. In the invention, absorbed current detectors are mounted in a vacuum specimen chamber and capacitance of a signal wire from each probe to corresponding one of the absorbed current detectors is reduced to the order of pF so that even an absorbed current signal with a high frequency of tens of kHz or higher can be detected. Moreover, signal selectors are operated by a signal selection controller so that signal lines of a semiconductor parameters analyzer are electrically connected to the probes brought into contact with a sample. Accordingly, electrical characteristics of the sample can be measured without limitation of signal paths connected to the probes to transmission of an absorbed current. In addition, a resistance for slow leakage of electric charge is provided in each probe stage or a sample stage.

Abstract: The present technology discloses a testing apparatus and a testing method for liquid crystal display (LCD). The apparatus comprises a testing chamber, at least one support device in the testing chamber and an adjusting device. The support device comprises a support stage located at the bottom of the testing chamber and a support rail located on a side wall of the testing chamber. The LCD is supported by the support stage and the support rail. The adjusting device is used to control the support rail to adjust angle of the LCD relative to the support stage.

Abstract: According to one embodiment, a stack includes first and second wiring structures and an inspection circuit. The inspection circuit includes a switching circuit having an input terminal, a drive terminal, and an output terminal electrically connected with a discharge mechanism. The inspection circuit is configured such that, in a state where a first electric connection is made in the first wiring structure and a second electric connection is made in the second wiring structure, at the time of applying charges to first and second electrodes, the charge applied to the second electrode flows to the drive terminal through the second wiring structure to bring the input terminal and the output terminal of the switching circuit into an electrically conducted state, and the charge applied to the first electrode flows to the discharge mechanism through the first wiring structure and the switching circuit.

Abstract: Disclosed is an apparatus for spinning a test tray and an in-line test handler including the above apparatus, wherein the apparatus may include a supporting unit for supporting a test tray transported between first and second chamber units facing in the different directions, wherein the first chamber unit is provided at a predetermined interval from the second chamber unit; a base unit to which the supporting unit is spinnably connected; and a spinning unit which spins the test tray so that semiconductor devices received in the test tray are tested at the same arrangement in each of the first chamber unit and the second chamber unit.

Abstract: A semiconductor chip panel includes a plurality of semiconductor chips embedded in an encapsulation material. At least part of the semiconductor chips comprise a first electrical contact element on a first main face and a second electrical contact element on a second main opposite to the first main face, respectively. One of the plurality of semiconductor chips is tested by establishing an electrical contact between a test contact device and the first electrical contact element and between an electrically conductive holder and the second contact element.

Abstract: Disclosed are a testing device and a testing method thereof. The testing device includes a frame, a flexible multi-layer substrate and at least one electrical testing point. The frame is positioned corresponding to a chip. At least one electrical connecting point is formed on a surface of the chip. The flexible multi-layer substrate is fixed in the frame. The electrical testing point is corresponding to the electrical connecting point and formed on an upper surface of the flexible multi-layer substrate for contacting the electrical connecting point and performing an electrical test to the chip. Furthermore, the electrical connecting point or the electrical testing point is a bump.

Abstract: Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

Abstract: Embodiments of interfaces are disclosed. One such interface has a plurality of connector assemblies, each connector assembly in a single opening of a plurality of openings passing completely through the interface. Each connector assembly has first and second connectors that are electrically and physically coupled to each other.

Abstract: A test device for testing a printed circuit board (PCB) includes a base and a measuring device. The measuring device includes a testing pin and is capable of measuring any desired point of the PCB on condition that the pin makes contact with the point at an included angle between the pin and a back surface of the PCB which is larger than a predetermined angle. The distance between the base and the PCB satisfies: H>L tan ?, where H is the vertical distance between the PCB and the base, L is the maximum length of an orthogonal projection of the pin on the PCB when the pin is contacting the point, and ? is the predetermined angle.

Abstract: A signal processing section included in a semiconductor testing circuit supplies a test signal inputted from a tester via a signal line to a plurality of DUTs and generates a test result by synthesizing response signals transmitted from the plurality of DUTs on the basis of the test signal. A test result output section included in the semiconductor testing circuit makes a voltage level of the test result differ from a voltage level of the test signal inputted and outputs the test result to the tester via the signal line.

Abstract: In one embodiment, an automated test equipment (ATE) system includes a tester having a tester electronics module, an application specific electronics module, and a tester-to-device under test (DUT) interface mount. The tester electronics module has a first electronics interface configured to electrically connect to a tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module has a second electronics interface and a third electronics interface. The second and third electronics interfaces are configured to electrically connect to the tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module is configured to communicate with the tester electronics module via the second electronics interface, and with at least one DUT via the third electronics interface.

Abstract: An apparatus comprising a test circuit that is provided on a test substrate and tests the device under test; a sealing section that covers a region of the test substrate on which the test circuit is formed, and seals the test circuit to form a sealed space that is filled with a cooling agent; and a through-connector that passes through the sealing section and electrically connects the test circuit to an element provided outside the sealing section, such that the connection is not through the test substrate.

Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.

Abstract: A terminal end for a flat test probe having tapered cam surfaces providing a lead-in angle on the tail of the terminal end which extend to a sharp rear angle to engage detents or projections within a receptacle. The tapered cam surfaces and shape rear angles allow the probe to be inserted into the receptacle with minimal force to retain the flat test probe within the receptacle.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.

Abstract: A time dependent dielectric breakdown (TDDB) test structure of a semiconductor device includes: a first test cell having a first test pattern in which a dielectric layer is formed between two electrodes; a second test cell spaced apart from the first test cell and having a second test pattern in which a dielectric layer is formed between two electrodes; and a barrier region configured to prevent electrical interference from occurring between the first test cell and the second test cell during a TDDB test.

Abstract: An embodiment of a method for testing an integrated circuit comprises a first step for determining at least one of a group selected from whether or not the chuck top receiving the integrated circuit exists near a probe card which transmits and receives electrical signals to and from the integrated circuit, whether or not the integrated circuit is under testing, and whether or not the probe card has a given temperature, and a second step for adjusting power for heating to be supplied to a heating element provided in the probe card according to the determination result in the first step.

Abstract: A method for fabricating a semiconductor device comprising: a first process for attaching a first supporting substrate having a plurality of through holes to a semiconductor substrate having a first surface and a second surface, so that each of the through holes is opposed to a semiconductor device formed in the semiconductor substrate; a second process for contacting probes of an electric characteristic inspection apparatus with a first electrode formed on the first surface, and a second electrode formed on the second surface via the through hole; and a third process for measuring electric characteristic of the semiconductor device.

Abstract: A test bracket for testing a circuit board includes a base, two connection pieces, and a supporting member for supporting the circuit board. The base includes a board and two posts extending up from the board. The supporting member includes two poles and a number of ribs slidably connected between the poles. First ends of the connection pieces are respectively detachably connected to the posts of the base, and second ends of the connection pieces opposite to the first ends are respectively pivotably connected to the poles.

Abstract: The electronic device mounting apparatus 1 comprises: a first camera 123 for imaging a flexible board 74 of a base member 70 of a test carrier 60 to generate a first image information; an image processing apparatus 40 for detecting a position of an alignment mark 79 of the flexible board 74 from the first image information and calculating a print start position 782 of the first interconnect patterns 78 on the flexible board 74 on the basis of the position of the alignment mark 79; a printing head 122 for forming a first interconnect pattern 78 on the flexible board 74 from the print start position 782; and a second conveyor arm 21 for mounting a die 90 on the flexible board 74 on which the first interconnect pattern 78 is formed.

Abstract: The present idea refers to a needle head, its use in a probe arrangement, and a method for electrically contacting multiple electronic components. The needle head comprises a body with a lower surface, needle electrodes emerging from the lower surface, and multiple outlets arranged in the lower surface. A channel is arranged between an inlet in the body and the outlets for conveying a medium from the inlet to the outlets. By this means, electronic components arranged in close distance under the lower surface of the needle head are directly exposed to the medium which provides a test environment during a test of the electronic components.

Abstract: In a method for manufacturing a sensor chip a spacer (3) is arranged at the front side (11) of a substrate (1) at which front side (11) a sensing element (2) is arranged, too. Holes (14) are etched for building vias (15) extending through the substrate (1) between the front side (11) of the substrate (1) and its back side (12). After etching, the holes (14) are filled with conductive material to complete the vias (15). The spacer (3) provides protection to the sensing element (2) and the sensing chip throughout the manufacturing process.

Abstract: A semiconductor testing jig fixes a measurement target while it is held between a chuck stage and the measurement target. The semiconductor testing jig includes a base on which the measurement target is to be installed and which can be attached to the chuck stage. The base includes: a first main surface to become an installation surface for the measurement target; a second main surface opposite the first main surface and which is to contact the chuck stage; and a porous region containing a porous member. The porous region is provided selectively as seen in plan view, and penetrates through the base from the first main surface toward the second main surface.

Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: A mechanism to electrically evaluate signals within an encapsulated semiconductor device package without the need for redesigning the package substrate is provided. Test bond pads are provided on a top surface of a semiconductor device die being placed within the semiconductor device package. One or more wire bonds having an elevated loop height are formed on the test bond pads. After encapsulating the semiconductor device package, the package encapsulant is subject to a backgrind process to expose a portion of the test connection wire bonds. Only an amount of the package encapsulant sufficient to expose each test connection wire bond is removed, so that the remaining encapsulant will continue to have the same effect on the package as would be present in a production device. Test probes can then be applied to the exposed test connection wire bonds.

Abstract: Disclosed is a testing apparatus, including: a base having opposite upper and lower surfaces, and a plurality of electrical circuits formed in the base, each of the electrical circuits extending from the upper surface to the lower surface and bending backwards to the upper surface such that two terminal ends of the electrical circuit are located on the upper surface. While in a testing, an element is disposed on the upper surface of the base such that testing probes are placed on the electrical contact spots of both the element and the upper surface of the base, thus without resorting to double sided testing that testing probes are placed on the upper and lower surfaces of the element as mentioned in the prior art. Hence, the testing apparatus and testing method can simplify the testing process and prevent the element from damage caused by mechanical stresses of the testing probes.

Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.

Abstract: A voltage compensation assembly adapted for apparatus having a prober for contacting the electronic elements on a substrate is described. The voltage compensation assembly includes a controller connected to the prober and adapted for active voltage compensation, and a voltage measuring unit connected to the controller and for measuring a voltage on the substrate.

Abstract: A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.

Abstract: A current sensor including electromagnetic conversion elements to detect magnetic fields generated when current flows through a current path under test, a chassis that stores the electromagnetic conversion elements and includes a channel to which the current path under test is disposed, and an installation member securable to the chassis, with the installation member including two arm units and a connecting unit to movably connect each end of the two arms, in which hook units are provisioned on the outer side of the two arm units, and holes are provisioned on the channel of the chassis to engaged with the hook units of the installation member, and when the current path under test and the installation member is disposed in the channel, the current path under test is securely supported, and at the same time the hook units and the holes are engaged.