Dut Socket Or Carrier Patents (Class 324/756.02)
  • Patent number: 11933815
    Abstract: A test fixture includes a signal test board, a circuit routing, and a branch routing. The signal test board includes a first surface and a second surface. The first surface has a first pin and a test point. The second surface has a second pin. The circuit routing is located in the signal test board and configured to connect the first pin and a corresponding second pin. A portion of the circuit routing includes an upper routing connected with one first pin, a lower routing connected with one second pin, and a via-hole routing connected with two ends of the upper routing and the lower routing. One end, connected with the via-hole routing, of the upper routing is located in a projection area of the corresponding test point. The branch routing is located in the signal test board and configured to connect the test point with a corresponding upper routing.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: March 19, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Maosong Ma, Xinwang Chen, Zhangqin Zhou
  • Patent number: 11828798
    Abstract: The test apparatus tests a wafer under test on which devices under test each including magnetoresistive memory or a magnetic sensor are formed. In a test process, the wafer under test is mounted on a stage. A test probe card is configured such that it can make probe contact with the wafer under test in the test process. A wafer connection HiFix is arranged between the test probe card and a test head. A magnetic field application apparatus is provided to the wafer connection HiFix. In the test process, the magnetic field application apparatus applies a magnetic field BEX to the wafer under test.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 28, 2023
    Assignees: ADVANTEST CORPORATION, TOEI SCIENTIFIC INDUSTRIAL CO., LTD.
    Inventors: Naoyoshi Watanabe, Shigeyuki Sato, Ryoichi Utsumi
  • Patent number: 11763959
    Abstract: The purpose of the present disclosure is to provide electro-conductive particles and a signal-transmitting connector having same, wherein the electro-conductive particles are improved to prevent the phenomenon of irregular scrub between the electro-conductive particles and to have improved signal delivery characteristics. Electro-conductive particles according to the present disclosure are provided on a signal-transmitting connector having multiple electroconductive portions supported by an insulating portion made of an elastic insulating material to be spaced apart from each other such that the signal-transmitting connector can be connected to an electronic component and can transmit electric signals.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 19, 2023
    Assignee: TSE CO., LTD.
    Inventors: Chang Su Oh, Bo Hyun Kim, Sung Ho Yoon
  • Patent number: 11545517
    Abstract: The present application provides a chip package structure and an electronic device, which could reduce a chip package thickness and implement ultra-thinning of chip package. The chip package structure includes a chip, a substrate, a lead and a lead protection adhesive; the lead is configured to electrically connect the chip and the substrate; the lead protection adhesive is configured to support the lead, where a highest point of the lead protection adhesive is not higher than a highest point of an upper edge of the lead.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: January 3, 2023
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Haoxiang Dong
  • Patent number: 11513151
    Abstract: A test handler includes a pusher which includes a pusher end which comes into contact with a DUT (Device Under Test) to transfer heat, and a pusher body which conducts heat to the pusher end, the pusher end separating a test tray for fixing the DUT and the pusher body from each other; a porous match plate including a pusher arrangement region in which the pusher body is placed, and a plurality of holes placed adjacent to the pusher arrangement region; a heater placed on an upper surface of the porous match plate to control temperature of the pusher; and an airflow input port placed on the heater to provide the airflow to the plurality of holes, in which the airflow passes through the plurality of holes and passes through a separated space between the test tray and the pusher body.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong Seok Kim, Suk Byung Chae, Dong Soo Lee, Sang Ho Jang
  • Patent number: 11442099
    Abstract: The present application discloses a testing device of array substrates and a testing method. The testing device of array substrates includes: a machine and testing interfaces, the testing interfaces being disposed on the machine; and testers disposed above the machine. There are at least two sets of testers, and the testers synchronously operate according to a preset scheme.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 13, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Bei Zhou Huang
  • Patent number: 11422155
    Abstract: An apparatus for testing an Integrated Circuit (IC) to be installed on a product substrate of a Multi-Chip Module (MCM) is disclosed. The apparatus includes a test substrate including (i) a first surface configured to receive the tested IC and at least an additional IC, (ii) a second surface that is opposite the first surface and is configured to receive electrical contacts, and (iii) first electrical traces for conveying electrical signals between the tested IC, the additional IC and the electrical contacts. The apparatus further includes a second electrical trace, which is formed in the test substrate instead of the additional IC and is configured to electrically connect between two of the first electrical traces.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 23, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Konstantin Turchin, Israel Dadon, Ido Bourstein
  • Patent number: 11327111
    Abstract: A chip testing system and an environment control apparatus are provided. The chip testing system includes the environment control apparatus, a central control device, and a chip testing device. The environment control apparatus includes an apparatus body and a pressing device. When the chip testing device is disposed in an accommodating chamber of the apparatus body, and the central control device controls the pressing device to press a plurality of side surfaces of a plurality of chips carried by the chip testing device, the central control device controls the chip testing device to perform a testing operation to the chips. After the chip testing device performs the testing operation to the chips, a plurality of movable members of the pressing device protrude from a contacting surface of the pressing device and push the chips to separate the chips and the contacting surface.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 10, 2022
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11302621
    Abstract: A chip package structure and an electronic equipment may reduce probability of short circuit failure during chip packaging and improve chip reliability. The chip package structure includes: a chip, a substrate, and a lead; the chip is disposed above the substrate; wherein the chip includes a pin pad and a test metal key, and the lead is configured to electrically connect the pin pad and the substrate; the test metal key is disposed in an edge region of the chip that is not under the lead.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: April 12, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Haoxiang Dong
  • Patent number: 11287468
    Abstract: An electronic component handling apparatus includes: a thermostatic chamber in which a socket disposed, the socket electrically being connectable to a device under test (DUT) including a first antenna; a moving device that moves the DUT and presses the DUT against the socket; an anechoic chamber disposed adjacent to the thermostatic chamber; a second antenna disposed inside the thermostatic chamber; and a first window that transmits radio waves radiated from the first or second antenna. The thermostatic chamber has a first opening on a wall surface of the thermostatic chamber. The anechoic chamber has a radio wave absorber and a second opening that opens toward a transmission direction of the radio waves from or to the second antenna. The thermostatic chamber and the anechoic chamber are connected to each other to make the first opening and the second opening face each other.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 29, 2022
    Assignee: ADVANTEST Corporation
    Inventors: Natsuki Shiota, Aritomo Kikuchi
  • Patent number: 11266015
    Abstract: An electrical contact assembly that uses an elastomer strip for each row of individual contacts. Each contact comprises a rigid bottom pin and a flexible top pin with a pair of arms which extend over and slide along sloped surfaces of the bottom contact. The elastomer strip is located between rows of the bottom and top pins. A bottom socket housing is provided with grooves which receive each elastomer strip. A row of top pins is then placed over each elastomer strip, and through ducts in the bottom socket housing. Bottom pins are then snapped into place in between the pair of arms.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 1, 2022
    Assignee: JF MICROTECHNOLOGY SDN. BHD.
    Inventors: Wei Kuong Foong, Kok Sing Goh, Shamal Mundiyath, Eng Kiat Lee, Grace Ann Nee Yee
  • Patent number: 11150270
    Abstract: Disclosed is a test device for testing electric characteristics of an object to be tested. The test device comprises a test circuit board comprising an insulating base substrate formed with a printed circuit, a plurality of signal contact points connected to the printed circuit and applying a test signal to the object to be tested, and a substrate shielding portion formed in a thickness direction of the base substrate between the plurality of signal contact points; and a test socket comprising a plurality of signal pins to be in contact with the plurality of signal contact points, and a conductive block supporting the plurality of signal pins without contact. With this, a secure noise shield is made between lines for applying a test signal when a high-frequency and high-seed semiconductor is subjected to the test, thereby improving reliability of the test.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 19, 2021
    Inventors: Geun-su Kim, Jae-hwan Jeong
  • Patent number: 11125809
    Abstract: A chip testing device for being transferred among a plurality of working stations includes a circuit board, a control set, and a plurality of connection terminals. The circuit board is provided with a plurality of electrical connection sockets disposed thereon each for carrying a chip. The control set includes a plurality of testing modules disposed on the circuit board. The connection terminals are disposed on the circuit board. When the connection terminals are connected to an external power supply device, the testing modules are connected to the electrical connection sockets, and each of the testing modules is able to test the chip on the electrical connection socket connected thereto.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 21, 2021
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11088051
    Abstract: A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more cantilever members, and the leadframe assembly has microwave structures and a flexible ground plane. The socket assembly further includes an elastomeric spacer adjacent the leadframe assembly, the elastomeric spacer having one or more holes receiving the spring probes therethrough.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 10, 2021
    Assignee: XCERRA CORPORATION
    Inventors: Valts Treibergs, Mitchell Nelson, Jason Mroczkowski
  • Patent number: 10823779
    Abstract: A substrate manufacturing apparatus includes a test apparatus including a test handler module for performing a test process on a substrate. The test handler module may include a conveyor unit to transfer a substrate, a handler unit for performing a test process on the substrate, and a transfer unit for transferring the substrate between the conveyor unit and the handler unit. The conveyor unit may include a feed conveyor and a discharge conveyor spaced apart from the feed conveyor.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: November 3, 2020
    Assignees: Samsung Electronics Co., Ltd., Semes Co., Ltd.
    Inventors: Youngchul Lee, Semin Kwon, JinHwan Lee, Jea-Muk Oh, Kyungsook Lee, Nam-Hong Lee
  • Patent number: 10826630
    Abstract: An inventive measuring device comprises a measuring unit, a communication unit and a control unit. The measuring unit is adapted to wirelessly receive a measuring signal transmitted by a device under test. The control unit is adapted to derive at least one measuring device, especially a signal level, from the received measuring signal. The communication unit is adapted to only wirelessly transmit the at least one measuring result to a central measuring unit, not being part of the measuring device.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: November 3, 2020
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Adam Tankielun
  • Patent number: 10687414
    Abstract: A circuit board has a base layer composed of multiple layers, and the base layer includes a connector to which a wire harness carrying a signal is coupled, the connector being fixed to a slot for mounting, and a plurality of GND plane patterns arranged in a plurality of layers and electrically coupled to each other through at least one via. Each one of the multiple layers of the base layer includes one of the plurality of GND plane patterns. In and around an area in which the connector is disposed, each one of the plurality of GND plane patterns is provided for a respective one of the multiple layers. The at least one via is arranged around the area in which the connector is disposed. The base layer includes a frame, and at least one via is arranged in the frame.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 16, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventor: Daisuke Fujioka
  • Patent number: 10680727
    Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 9, 2020
    Assignee: MediaTek Inc.
    Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu, Nan-Cheng Chen
  • Patent number: 10611568
    Abstract: A material handling system has a vertical lift two vertically aligned carriages that are independently positionable on a vertical support structure by respective drive systems. A processor subsystem selects one of the two carriages to move an article from at least one in-feed conveyor to a selected level of an automated storage and retrieval system (AS/RS). The processor subsystem concurrently positions the other carriage to avoid a collision.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 7, 2020
    Assignee: INTELLIGRATED HEADQUARTERS, LLC
    Inventors: Douglas K. Schack, Ralf Buerkle, Jonathon Cleary, Charles Christopher Lingamfelter
  • Patent number: 10613138
    Abstract: According to the present invention there is provided a method of handling devices comprising the steps of, receiving a tray on which devices to be tested are supported, into a flipping station; positioning the tray under a boat, so that the devices which are supported on the tray are sandwiched between the tray and a surface of the boat which can support devices, to form a first stack; flipping the first stack, so that the tray is positioned over the boat, to cause the devices to fall, under the influence of gravity, away from the tray to become supported on the surface of the boat, thereby transferring the devices from the tray to the surface of the boat; moving the boat to a testing station and testing the devices on the boat; receiving the boat of tested devices into the flipping station; positioning a tray over the boat, so that the devices which are supported on the surface of the boat are sandwiched between the surface of the boat and tray to form a second stack; flipping the second stack so that the bo
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 7, 2020
    Assignee: RASCO GMBH
    Inventors: Christian Wammetsberger, Andreas Wiesböck, Klaus Ilgenfritz, Dieter Schmid, Max Schaule, Alex Waldauf
  • Patent number: 10572427
    Abstract: A system and method of operation of a device programming system includes a protocol emulation layer for translating data storage commands from an initial protocol to the protocol of the programmable devices. The protocol emulation layer simplifies the data access and control of the programmable devices by allowing the reuse of existing code bases for legacy devices.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 25, 2020
    Assignee: Data I/O Corporation
    Inventors: Anthony Rosensprung, Andrew Wygle, Benjamin Michael Deagen
  • Patent number: 10555418
    Abstract: A component module includes a circuit board having a first base, a second base facing the first base, and a side section connected to the first and second bases. A wiring pattern is formed on at least one of a first facing surface of the first base that faces the second base, a second facing surface of the second base that faces the first base, and a side section facing surface of the side section that faces a direction in which the first and second bases extend. The component module further includes an electronic component that is in contact with at least one of the first facing surface, the second facing surface, and the side section facing surface. A sealing resin is formed in a region surrounded by the first facing surface, the second facing surface, and the side section facing surface so as to seal the electronic component.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masashi Yamaura
  • Patent number: 10553537
    Abstract: A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: February 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuji Takahashi, Chenche Huang, Chun-Ming Wang, Vincent Shih
  • Patent number: 10527646
    Abstract: An electrical contact assembly comprised of four identical modules arranged in a four-sided formation. Each module comprises of a bottom housing formed with two rows of through holes to allow a row of front and back contact pairs to be inserted, with separators in between each pair to prevent electrical conductance between the pairs. A top housing is then lowered onto the top of these contact pairs. With the aid of a key tool, the rows of contact pairs are inserted into through holes in the top housing. By virtue of different heights between the front and back rows of through holes, the front and back contact rows are inserted one first, and then the other. This allows for easier installation of an assembly with minimal tolerance accumulation.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 7, 2020
    Assignee: JF MICROTECHNOLOGY SDN. BHD.
    Inventors: Wei Kuong Foong, Kok Sing Goh, Shamal Mundiyath, Eng Kiat Lee
  • Patent number: 10379138
    Abstract: An adapter for receiving at least one integrated circuit with a Hall sensor in a housing. The adapter has a cavity for receiving the at least one integrated circuit in the housing, at least one opening connected with the cavity, and a magnetic-field generating apparatus for generating a magnetic field in the cavity. The adapter is used in a system for detecting the strength of a magnetic field.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: August 13, 2019
    Assignee: TDK—Micronas GmbH
    Inventors: Stefan Albrecht, Christian Schladebach, Dominik Zimmermann
  • Patent number: 10338100
    Abstract: Disclosed is a test socket for inspecting an electronic device that is particular about properties. The test socket for inspecting electric properties of a subject includes a plurality of probes configured to be retractable in an inspection direction; a probe supporter configured to support the plurality of probes so that first ends of the plurality of probes protrudes to contact with an object contact point of a subject; and a printed circuit board (PCB) configured to be placed beneath the probe supporter, be mounted with electronic parts, be formed with holes through which second ends of the plurality of probes pass, include at least one first pad with which at least one second end of the plurality of probes comes into contact and at least one second pad formed on an opposite side to the first pad, and be formed with electric paths extended from the first pad and the second pad and connected to the mounted electronic parts.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: July 2, 2019
    Assignee: LEENO INDUSTRIAL INC.
    Inventor: Sang-Duck Park
  • Patent number: 10317459
    Abstract: A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 11, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ish Chadha, Robert Bloemer
  • Patent number: 10320106
    Abstract: For an electrical component socket including a socket base having a frame shape to which a contact module is to be inserted and attached from below, an embodiment has an objective to allow contact pins to be in contact with a circuit board with stability. The electrical component socket is configured such that the upper-side plate is caused to ascend to an uppermost position by elastic force of urging means in a state where the contact module is not attached to the socket base. In a state where the contact module is attached to the socket base and disposed on the circuit board, the upper-side plate moves down toward a lower-side plate side against elastic force of the contact pins to be positioned at a predetermined base position, so that lower-side contact portions of the contact pins are brought into contact with the circuit board at a predetermined contact pressure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 11, 2019
    Assignee: ENPLAS CORPORATION
    Inventor: Yuki Ueyama
  • Patent number: 10254332
    Abstract: A for positioning a miniaturized piece includes a positioning structure that forms a first cavity designed to receive with play the miniaturized piece and a second cavity communicating with the first cavity. At least one electrical-contact terminal is provided facing the second cavity and is electrically coupleable to an electronic testing device designed to carry out an electrical test on the miniaturized piece. An actuator device causes a vibration of the positioning structure such that the vibration translates the miniaturized piece towards the second cavity until it penetrates at least in part into the second cavity.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: April 9, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabiano Frigoli, Giuseppe Ballotta, Massimo Greppi, Luca Giuseppe Falorni, Paolo Aranzulla
  • Patent number: 10241132
    Abstract: Disclosed a socket apparatus for a semiconductor device test, the apparatus including: body elements (100, 200) into which contacts (400) are inserted; movable elements (300, 500) on which a semiconductor device (IC) is seated; a socket cover (600) assembled to the movable elements (300, 500) and resiliently assembled to the body elements (100, 200); and a semiconductor device pressing part (700) pressing and fixing the semiconductor device (IC) seated on the movable elements (300, 500), wherein the semiconductor device pressing part (700) includes: a pusher plate (710) having an opening cam (711) and coming into surface contact with an upper surface of the semiconductor device (IC) and applies pressure thereto; a latch (720) of which ends are hingedly assembled to the socket cover (600) and the pusher plate (710); and a link (730) of which ends are hingedly assembled to the socket body (100) and the latch (720).
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 26, 2019
    Assignees: HICON CO., LTD.
    Inventors: Dong Weon Hwang, Jae Suk Hwang, Jae Baek Hwang
  • Patent number: 10201086
    Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Cheng-Hsiang Liu, Chang-Lun Lu, Jun-Cheng Liao, Cheng-Yi Chen
  • Patent number: 10126355
    Abstract: A probe test card for testing semiconductor devices includes a printed circuit board, a pair of electrically conductive probes extending towards one another and protruding away from the printed circuit board with a gap being disposed between ends of the pair of electrically conductive probes, and a coil affixed to and electrically connected to the printed circuit board and disposed directly over the gap. The probe test card is configured to generate a magnetic flux in the gap between the ends of the pair of electrically conductive probes upon the application of a current through the coil.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Juergen Bostjancic, Gerhard Raczynski, David Kammerlander, Gerhard Prechtl
  • Patent number: 10110325
    Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 23, 2018
    Assignee: MEDIATEK INC.
    Inventors: Yen-Liang Chen, Chun-Hsien Peng, Ying-Chou Shih, Yu-An Chen, Chun-Wei Yang
  • Patent number: 10101386
    Abstract: Semiconductor process excursions may be monitored by fabricating functional circuitry on a plurality of semiconductor devices and then testing the functional circuitry of the plurality of semiconductor devices using a sequence of test patterns. A cumulative failure curve may be determined that has points of discontinuity based on results of testing with the sequence of test patterns. A point of discontinuity magnitude at a selected location in the cumulative failure curve may be compared to an expected discontinuity magnitude. Process excursion analysis may be indicated when a point of discontinuity magnitude exceeds an expected magnitude threshold.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 16, 2018
    Inventors: Kenneth Michael Butler, John Michael Carulli, Jr.
  • Patent number: 10101382
    Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alex Paikin, Colin Johnson, Tathagata Chatterjee, Sameer Pendharkar
  • Patent number: 10037933
    Abstract: A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more cantilever members, and the leadframe assembly has microwave structures and a flexible ground plane. The socket assembly further includes an elastomeric spacer adjacent the leadframe assembly, the elastomeric spacer having one or more holes receiving the spring probes therethrough.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 31, 2018
    Assignee: Xcerra Corporation
    Inventors: Valts Treibergs, Mitchell Nelson, Jason Mroczkowski
  • Patent number: 9983229
    Abstract: A test socket is provided that includes a base material including an insulating elastic material and a conductive portion extending through the base material in a thickness direction of the base material, wherein the conductive portion includes a plurality of conductive particle structures arranged in the thickness direction of the base material, and each of the plurality of conductive particle structures includes a plurality of conductive particles having at least one insulating wire and/or at least one conductive wire extending from a surface of the conductive particle, bonded with a material having a functional group.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-won Han, Jong-woo Lee, Young-gi Min, Soon-won Lee, Yong-in Lee
  • Patent number: 9875954
    Abstract: A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more cantilever members, and the leadframe assembly has microwave structures and a flexible ground plane. The socket assembly further includes an elastomeric spacer adjacent the leadframe assembly, the elastomeric spacer having one or more holes receiving the spring probes therethrough.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 23, 2018
    Assignee: Xcerra Corporation
    Inventors: Valts Treibergs, Mitchell Nelson, Jason Mroczkowski
  • Patent number: 9847284
    Abstract: A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: December 19, 2017
    Assignee: Apple Inc.
    Inventor: Jun Zhai
  • Patent number: 9761524
    Abstract: A system for electroless deposition on a substrate is provided, including the following: a chamber; a substrate support configured to receive a substrate having a conductive layer disposed on a top surface of the substrate, the top surface of the substrate having an edge exclusion region and a process region, wherein the substrate support is configured to rotate the substrate; a solution container configured to hold an electroless deposition solution; a dispenser configured to provide a flow of the electroless deposition solution; a controller, the controller configured to direct the flow of the electroless deposition solution toward the edge exclusion region while the substrate is rotated, the flow being directed away from the process region, the electroless deposition solution plates metallic material over the conductive layer at the edge exclusion region, to produce an increased thickness of the metallic material that reduces electrical resistance.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: September 12, 2017
    Assignee: Lam Research Corporation
    Inventor: Artur Kolics
  • Patent number: 9742505
    Abstract: A testing device includes a connecting module and a processor electrically connected to the connecting module. The connecting module is electrically coupled with a plurality of communication devices under tests (DUTs) synchronously. The processor determines a schedule for the communication DUTs and tests the communication DUTs according to the schedule. A testing method is applied to the testing device to implement the operations.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 22, 2017
    Assignee: ALIFECOM TECHNOLOGY CORP.
    Inventors: Meng-Kai Su, Yi-Chung Shen, Shih-Hsiang Hu, Heng-Iang Hsu, Shu-Hua Kao, Daching Chen
  • Patent number: 9720034
    Abstract: A method of operating a semiconductor test device includes transferring a first device under test (DUT) from a load tray to a first load shuttle. The first DUT is transferred from the first load shuttle to a first test board and a second DUT is transferred from the load tray to a second load shuttle.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: August 1, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Suk Hyun Jung
  • Patent number: 9703623
    Abstract: An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: July 11, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Michael Decesaris, Luke D. Remis, John K. Whetzel
  • Patent number: 9638718
    Abstract: A system including an automated test equipment (ATE) and an interface board. The interface board includes a temperature monitor that compares a sensor temperature to a predetermined temperature. The associated temperature sensor may be located near one or more selected components on the device under test or the interface board. If the sensor temperature exceeds the predetermined temperature the temperature monitor turns off one or more power supplies of the ATE.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: May 2, 2017
    Assignee: Advantest Corporation
    Inventors: Ralf Haefner, Claus Ploetz
  • Patent number: 9599661
    Abstract: Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Patent number: 9575152
    Abstract: An MRI apparatus employs a magnet for establishing a B0 field, one or more imaging radiofrequency coils for creating a B1 field, and one or more nulling radiofrequency coils. The RF energy emitted by the nulling radiofrequency coils may be configured such that it disrupts the nuclear magnetic resonance signals emitted by nuclei excited by the B1 field. In addition, the nulling radiofrequency coils may be calibrated to be 180° out of phase such that the RF energy emitted by a pair of nulling radiofrequency coils is cancelled at a location between them.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 21, 2017
    Assignee: Fonar Corporation
    Inventor: Raymond V. Damadian
  • Patent number: 9575092
    Abstract: An embodiment of a device for positioning a miniaturized piece, including: a positioning structure, which forms a first cavity, designed to receive with play the miniaturized piece, and a second cavity communicating with the first cavity; at least one electrical-contact terminal, facing the second cavity and electrically coupleable to an electronic testing device, designed to carry out an electrical test on the miniaturized piece; and an actuator device, which causes a vibration of the positioning structure, the vibration being such that the miniaturized piece translates, in use, towards the second cavity, until it penetrates at least in part into the second cavity.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 21, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabiano Frigoli, Giuseppe Ballotta, Massimo Greppi, Luca Giuseppe Falorni, Paolo Aranzulla
  • Patent number: 9553379
    Abstract: An electrical connector includes a socket, a stiffener disposed around the periphery of the socket, and a load plate covering the socket. The load plate includes two opposite lateral sides, and a front side and a rear side connected to the two lateral sides, which define an opening for a chip module to pass through. The rear side includes a pivoting portion, such that the load plate is rotatable relative to the socket around the pivoting portion. Each lateral side includes a first pressing portion and a second pressing portion in front of the first pressing portion. When the chip module is installed onto the socket and the load plate is closed, the first and second pressing portion press the chip module, and distances from bottom surfaces of the first and second pressing portions to a top surface of the load plate is unequal.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 24, 2017
    Assignee: LOTES CO., LTD
    Inventors: Xu Jun Liu, Che Che
  • Patent number: 9523710
    Abstract: A nest includes a fix part, and a movable part, wherein the fix part and movable part are configured to cooperate so as to define a pocket which can receive at least a part of an electrical component, wherein the movable part is moveable between a first position and a second position, wherein in the first position the pocket is open so that at least part of the electrical component can be moved into the pocket, and in the second position the pocket is closed so that the at least part of the electrical component positioned in the pocket is secured within the pocket, wherein the nest further includes a biasing means which is arranged to bias the movable part towards its second position. There is further provided a nest assembly, a component handling assembly, and a table that includes the nest.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: December 20, 2016
    Assignee: ISMECA SEMICONDUCTOR HOLDING SA
    Inventors: Sylvain Vienot, Phillipe Viverge, Massimo Scarpella, Philippe Roy
  • Patent number: 9519023
    Abstract: The invention relates to a module for exchanging an approximately planar interface unit in a testing system for testing semiconductor elements. The module includes a base element, a holder, and guide elements. The guide elements are embodied so that the interface unit can be moved by means of a linear, translatory movement from an end position into an intermediate position and from the intermediate position into a removal position that is situated outside the testing system. The mechanism includes a lever mechanism that is controlled by a sliding guide and is supported so that it can move crosswise to the linear translation movement of the holder.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: December 13, 2016
    Assignee: Turbodynamics GmbH
    Inventors: Stefan Thurmaier, Benno Stigloher