Abstract: A wafer stage and a method of supporting a wafer for inspection. the wafer stage comprises a platform for supporting a wafer such that a backside of the wafer is suspended above a cavity of the platform; and a support structure disposed substantially within the cavity for supporting a portion of the wafer; wherein the wafer stage is adapted for relative movement of the platform with respect to the support structure for alignment of the wafer with respect to a probe.

Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.

Abstract: A testing circuit (100) in an integrated circuit (102) indirectly measures a voltage at a node of other circuitry (104) in the integrated circuit. The testing circuit includes a transistor (120) having a control electrode (121), a first conducting electrode (122) coupled to a first pad (150), a second conducting electrode (123) coupled to a terminal of a power supply, and one or more switches (131 and 133) for selectively coupling the control electrode to one of the node and a second pad (140). A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.

Abstract: A testing apparatus for performing an avalanche test comprises a wafer chuck configured to retain a wafer having a plurality of transistors, an inductor with a first end connected to a drain terminal of the transistor, a power source configured to provide a current to a second end of the inductor through a switch, a meter connected to a source terminal of the transistor through the wafer chuck, and a driver configured to synchronously control the operation of the switch and the operation of the transistor.

Abstract: A testing apparatus for performing an avalanche test includes a wafer chuck configured to retain a wafer having a plurality of transistors, wherein the wafer chuck includes an insulating body and a plurality of conductors embedded in the insulating body. In one embodiment of the present invention, the device holder includes a plurality of conductors having horizontal sides and longitudinal sides, a plurality of insulating horizontal lines positioned at the horizontal sides, and a plurality of insulating longitudinal lines positioned at the longitudinal sides and intersecting the horizontal lines.

Abstract: An embodiment of an electrical connecting apparatus includes a chip unit having a plurality of electronic components arranged on the upper side of a chip supporting body, a probe unit having a plurality of contacts arranged on the lower side of a probe supporting body, and a connecting unit arranged between the chip unit and the probe unit and having a connecting member supporting body and a plurality of connecting members electrically connecting the chip unit to the probe unit. The chip unit, the probe unit and the connecting unit are vacuum-coupled.

Abstract: An opener and a buffer table for a test handler are disclosed. The opener includes an opening plate, a plurality of pin blocks forming pairs, and at least one or more interval retaining apparatus for retaining an interval between the pin blocks forming a pair. Each of the pin blocks is movably coupled to the opening plate, and includes opening pins for releasing a holding state of a holding apparatus that holds semiconductor devices in a carrier board. Although semiconductor devices to be tested are altered in size and a carrier board loading with the semiconductor devices is thus replaced, the opener does not need to be replaced, thereby reducing the replacement cost and the waste of resources.

Abstract: Provided are an apparatus and a method of testing a semiconductor device. A horizontal maintaining unit provided inside a test head applies load to a probe card in a direction perpendicular to the probe card to hold the probe card in a horizontal state. Probe needles of the probe card are uniformly placed on a central region of pads of the semiconductor device, thereby providing an apparatus and a method of testing a semiconductor device capable of improving productivity and reducing a yield loss of a test process.

Abstract: Methods and apparatuses for modifying a stage position and measuring at least one parameter of a motor connected with a stage during a commanded stage position are described. In one embodiment of one aspect of the invention, the motor is configured to move the stage in a first direction in response to the at least one parameter and determine whether the at least one parameter is within a threshold range.

Abstract: An exemplary die carrier is disclosed. In some embodiments, the die carrier can hold a plurality of singulated dies while the dies are tested. The dies can be arranged on the carrier in a pattern that facilities testing the dies. The carrier can be configured to allow interchangeable interfaces to different testers to be attached to and detached from the carrier. The carrier can also be configured as a shipping container for the dies.

Abstract: In order to shorten testing time of a plurality of devices under test formed on a semiconductor wafer, a wafer tray used by a test apparatus performing the test is provided. The wafer tray includes a first flow passage for fixing the semiconductor wafer to the wafer tray using vacuum suction, a second flow passage for fixing the wafer tray to the test apparatus using vacuum suction, and a heater for heating a loading surface on which at least the semiconductor wafer is loaded. By using this wafer tray, the semiconductor wafer, which is the object being tested, can be smoothly attached to and detached from different test heads, and testing can be begun quickly after the semiconductor wafer is attached to a test head.

Abstract: A radio frequency (RF) testing apparatus, for testing device under test (DUT) comprising a receiving antenna, includes a pair of transmitting antennas transmitting wireless communication signals to the receiving antenna, a shielding box, a first filter and a second filter. The shielding box includes a transmitting box, a receiving box for receiving the DUT, a connecting box connecting between the transmitting box and the receiving box and a pair of transmitting antennas fixed on the transmitting box and suspending towards the connecting box. The connecting box includes a microwave absorption medium on the connecting box and communicates with the receiving box. The first filter is mounted on the connecting box and the transmitting box to electrically connect with the transmitting antenna. The second filter is mounted on the receiving box to electrically connect with the DUT.

Abstract: A test system may be provided in which devices under test are loaded into test trays. Each test tray may include clamps for retaining a device under test within the test tray. The test tray may be configured to transmit test tray identification information to facilitate tracking of the device under test associated with the test tray. The test tray may include engagement features configured to receive corresponding engagement features on a computer-controlled loading arm. The loading arm may be used to move the test tray and associated device under test to a test fixture for testing. A contact extending structure may be retained in the test tray and may be configured to mate with the device under test. Contact pads on the contact extending structure may be mated with corresponding contacts on the test fixture to form an electrical connection between the device under test and the test fixture.

Abstract: A test system may be provided in which devices under test (DUTs) are loaded into test trays. Test trays may be moved between test stations using a conveyor belt. The test system may include loading equipment for placing test trays on the conveyor belt at desired intervals. Each test tray may be tested using test stations positioned along the conveyor belt. A first group of test stations may be configured to test DUTs in their upright orientation, whereas a second group of test stations may be configured to test DUTs in their inverted orientation. Test tray flipping equipment may be interposed between the first and second groups of test stations. The flipping equipment may include a movable arm configured to receive an incoming tray, grab the tray, lift the tray from the conveyor belt, rotate the tray, and drop off the tray back onto the conveyor belt.

Abstract: A CPU 14 built in to a device 1 starts inspection processing in response to an I/F 17 having received an inspection start command from an external terminal 3, switches an inspection terminal 13, which is a redundant terminal 11, over to be an input terminal with a pull-up resistor, applies a predetermined voltage to the inspection terminal 13, detects the input voltage of the inspection terminal 13, and transmits the detected input voltage as an inspection result to the external terminal 3.

Abstract: A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages.

Abstract: A substrate inspection jig for use in inspection of an electrical property of a printed board to be inspected on which an electronic component is mounted includes a spacer which is mounted on the printed board to be inspected, a conductive plate which is connected to the spacer, and is disposed along an arrangement direction of electrode terminals of the electronic component to be inspected, and a fastener which fastens the spacer on the printed board to be inspected, wherein the plate is disposed above the printed board to be inspected so as to avoid contact with the printed board to be inspected, and a predetermined potential of the printed board to be inspected is set to the plate through the spacer or/and the fastener.

Abstract: A system for analyzing electronic devices includes a first cab, an input station, a transport apparatus, an electric machine interface station, and an electric machine interface. The first cab includes a holder having formations for removably receiving a first subset of electronic devices and a communications interface. The input station receives the first cab and the transport apparatus transports the first cab with the first subset of electronic devices from the input station to the electric machine interface station. The electric machine interface is positioned to engage communicatively with the communications interface of the first cab when the first cab is at the electric machine interface station, and is disengageable from the communications interface of the first cab for the first cab to be transportable by the transport apparatus away from the electric machine interface station. Heat conducts to or from the electronic devices while they are being analyzed.

Abstract: In one embodiment, a device interface board is provided which includes a printed circuit board with a DUT interface structure, such as socket, associated with a DUT side of the printed circuit board. A high frequency connector and electronic component are mounted in a cavity formed in a back side of the printed circuit board. A signal via through the printed circuit board couples the high frequency connector and electronic component with the DUT interface structure. An encapsulating structure may be provided, which covers the cavity while allowing a cable to connect to the high frequency connector.

Abstract: The present invention provides an inspection apparatus, which comprises probes for front side electrodes, probes for back side electrodes, and a chuck stage, wherein the probes for front side electrodes and the probes for back side electrodes are formed on the upper surface of the chuck stage, and the probe contact area electrically continues to the wafer holding area, and the probes for front side electrodes and the probes for back side electrodes are located leaving a distance in horizontal direction between them so that the probes for back side electrodes move relatively within the probe contact area when the probes for front side electrodes are moved relatively within the wafer under test by the movement of the chuck stage. According to the inspection apparatus of the present invention, it is possible to inspect characteristics of semiconductor devices having electrodes on both side of a wafer more accurately in wafer state.

Abstract: Circuit boards are provided that include a functional portion and at least one removable test point portion. The removable test point portion may include test points which are accessed to verify whether the functional portion is operating properly or whether installed electronic components are electrically coupled to the board. If multiple boards are manufactured together on a single panel (in which the individual boards are broken off), the test points can be placed on bridges (e.g., removable portions) that connect the individual boards together during manufacturing and testing. Configurable test boards are also provided that can be adjusted to accommodate circuit boards of different size and electrical testing requirements. Methods and systems for testing these circuit boards are also provided.

Abstract: An electronic device test fixture deploys a plurality of contact elements in a dielectric housing. The plumb arrangement of contact elements each include an armature or transversal configured to first depress and then slide laterally when urged downward by the external contacts of a device under test. The rotary movement of the transversal is optimized via the configuration of a surrounding forked regulator such that surface oxide deposition on the external device under test terminal is disrupted to reliably minimize contact resistance without damaging or unduly stressing the electrical junction of the device under test.

Abstract: A testing card for a USB port includes first USB contacting pins, a second USB contacting pin, a transmitting circuits, a voltage converting circuit, and a testing portion. The first USB contacting pins are connected to the USB port to receive a number of USB signals. The second USB contacting pin is connected to the USB port to receive a voltage signal from the USB port. The transmitting circuit is electrically connected to the first USB contacting pins to transmit the USB signals therefrom. The voltage converting circuit is electrically connected to the second USB contacting pin to convert the voltage signal to a predetermined level. The testing portion is electrically connected to the outputs of the transmitting circuit and the voltage converting circuit to receive the USB signals and the converted voltage signal.

Abstract: A wafer stage and a method of supporting a wafer for inspection. the wafer stage comprises a platform for supporting a wafer such that a backside of the wafer is suspended above a cavity of the platform; and a support structure disposed substantially within the cavity for supporting a portion of the wafer; wherein the wafer stage is adapted for relative movement of the platform with respect to the support structure for alignment of the wafer with respect to a probe.

Abstract: A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure.

Abstract: A test station may include a test host, a test unit, and a test enclosure. A device under test (DUT) having at least first and second antennas may be placed in the test enclosure during production testing. Radio-frequency test signals may be conveyed from the test unit to the DUT using a test antenna in the test enclosure. In a first time period during which the performance of the first antenna is being tested, the DUT may be oriented in a first position such that path loss between the first antenna and the test antenna is minimized. In a second time period during which the performance of the second antenna is being tested, the DUT may be oriented in a second position such that path loss between the second antenna and the test antenna is minimized. The DUT is marked as a passing DUT if gathered test data is satisfactory.

Abstract: A probe card according to the present invention includes a support plate for supporting probes that contact an object to be inspected, a circuit board, a holding member for holding a lower surface of an outer peripheral portion of the support plate, and an abutting member disposed between the lower surface of the outer peripheral portion of the support plate and the holding member and protruding upward to abut to the lower surface of the outer peripheral portion of the support plate. Accordingly, horizontal expansion of the support plate itself is allowed, and at the time of inspecting electrical characteristics of the object to be inspected, even though the temperature of the support plate is increased and the support plate expands, the support plate can expand in a horizontal direction, thereby suppressing vertical deformation of the support plate.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: There is disclosed an electronic testbed, an electronic testbed board, and a method for positioning receptacles for nails in the electronic testbed board. In an embodiment, the electronic testbed board includes a mounting through-hole for mounting a receptacle for a nail. The mounting through-hole is drilled to a suitably precise diameter for mounting the receptacle substantially perpendicular to the testbed board. One or more via-holes are located adjacent the mounting through-hole, and are adapted to allow an electrical connection between any conductive layers provided at the one or more via-holes. The receptacle may be mounted more accurately and the electronic test bed may be built more accurately by separating the functions of the via-holes and the mounting through-hole.

Abstract: A device under test (DUT) may be tested using a test station having a test host, a non-signaling tester, and a test cell. During testing, the DUT may be placed within the test cell, and the DUT may be coupled to the test host and the tester. In one suitable arrangement, the DUT may be loaded with a predetermined test sequence. The predetermined test sequence may configure the DUT to transmit test signals using different network access technologies without synchronizing with the tester. The tester may receive corresponding test signals and perform desired radio-frequency measurements. In another suitable arrangement, the tester may be loaded with the predetermined test sequence. The predetermined test sequence may configure the tester to generate test signals using different network access technologies without establishing a protocol-compliant data link with the DUT. The DUT may receive corresponding test signals and compute receive signal quality.

Abstract: A test device for testing a printed circuit board (PCB) includes a base and a measuring device. The measuring device includes a testing pin and is capable of measuring any desired point of the PCB on condition that the pin makes contact with the point at an included angle between the pin and a back surface of the PCB which is larger than a predetermined angle. The distance between the base and the PCB satisfies: H>L tan ?, where H is the vertical distance between the PCB and the base, L is the maximum length of an orthogonal projection of the pin on the PCB when the pin is contacting the point, and ? is the predetermined angle.

Abstract: Methods and systems for testing an integrated circuit during an assembly process are described. The integrated circuit is received from inventory. The integrated circuit is placed in a socket on a first circuit board for system-level testing. The system-level testing is performed prior to placement and permanent attachment of the integrated circuit onto a second circuit board. Provided the integrated circuit passes the system-level testing, the placement and permanent attachment of the integrated circuit to the second circuit board is the next step following the system-level testing in the assembly process.

Abstract: A test apparatus features an upper RF impermeable hood and lower RF impermeable hood, wherein each of the hoods have internal dividers. When in a closed position, the hoods and dividers create two or more RF impermeable chambers. The hoods are configured to enclose or sandwich a pallet supporting two or more printed circuit boards. One of the printed circuit boards is disposed in each chamber formed by the hoods and dividers.

Abstract: A test structure (200) in an integrated circuit (100) includes a probe pad (210) disposed at a surface of a die (102) of the integrated circuit, a transmission gate (202) for connecting portions of an electronic circuit within the integrated circuit in response to a momentary signal applied to the probe pad, a first inverter (221) having an input coupled to the probe pad and having an output coupled to a control input of the transmission gate, and a second inverter (222) having an input coupled to an output of the first inverter and having an output coupled to another control input of the transmission gate. The output of the second inverter is coupled to the input of the first inverter. Upon power-up, the transmission gate is open. After the momentary signal is applied to the probe pad, the transmission gate closes and remains closed until power is disconnected.

Abstract: A jig for use in a semiconductor test includes: a base on which a probe pin and an insulating material are placed, the insulating material surrounding the probe pin in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are placed. The stage is capable of holding a test object on a surface of the stage facing the base. When the base and the stage move in a direction in which they go closer to each other while the test object is placed on the stage, the probe pin comes into contact with an electrode formed on the test object and the insulating material comes into contact with the test object.

Abstract: A reinforcing member is formed at a top surface side of a probe card including a support plate for supporting a contactor and a circuit board. A plurality of long guide holes are formed in an outer peripheral portion of the reinforcing member. Fixing members fixed to a holding member and collars formed around outer circumferences of the fixing members are formed in the guide holes. A length in a longitudinal direction of each of the guide holes is greater than a diameter of each of the collars, and a central line in the longitudinal direction of each of the guide holes passes through a center of the reinforcing member. Due to the guide holes, horizontal expansion of the reinforcing member itself is allowed.

Abstract: A test section unit provided to a test head body includes a plurality of sockets to be attached with electronic devices to be tested and a performance board as a main substrate. All of the sockets are provided with the performance board without an intervening a socket board.

Abstract: A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.

Abstract: A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

Abstract: A terminal board is part of a terminal board assembly for terminating and testing of railroad wires. The board includes a first terminal block with a front post and a back post installed on a plane, along with a plurality of terminal blocks with front posts. A control test link, with an insulating material lining one of three holes, is installed on the front posts of terminal blocks. A test nut, connectable to the front post of the first terminal block, has a face with a depression formed therein to contact the test link when installed on the front post of the first terminal block over the insulating material. First wiring is attached on the plane's front, and second wiring is terminated on the plane's back. A surge protection component and the control test link are pre-installed on the front of the plane, providing for easy removal.

Abstract: A handler includes a table which supports an electronic device, a socket which is arranged to face the table, and a transport mechanism which transports the electronic device. The transport mechanism includes a contact head having a lead press with a recess for storing the electronic device, and a chuck sleeve which extends through the lead press, is arranged relatively movable from the lead press in a direction in which the chuck sleeve extends, and chucks the electronic device, an elevating mechanism which moves the contact head between the table and the socket, a pivot mechanism which pivots the contact head within the vertical plane, and a control unit which controls chucking and release of the electronic device by the chuck sleeve, and vertical movement and pivot of the contact head.

Abstract: A docking drive for a testing head comprising a plurality of locking mechanisms (10) each provided with an own locking drive (14, 21-28) comprises a synchronizing device (11, 12, 13) synchronizing the locking drives (14, 21-28) of the locking mechanisms (10). It may comprise a respective trapping device (15a, b) provided in a plurality of locking mechanisms (10) each retaining a locking element (50) to be locked in the respective locking mechanism (10) in a certain position. A locking element (50) of a docking system comprises a base (51), a locking section (55) and a connecting mechanism (52-54) provided between the base (51) and the locking section (55) and being manually releasable without tools. The locking section (55) may be resiliently supported opposite of the base (51). The locking element may comprise a first retaining section (56) for the trapping device (15) and a second retaining section (57) for a locking device (16).

Abstract: A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: A test apparatus features an upper RF impermeable hood and lower RF impermeable hood, wherein each of the hoods have internal dividers. When in a closed position, the hoods and dividers create two or more RF impermeable chambers. The hoods are configured to enclose or sandwich a pallet supporting two or more printed circuit boards. One of the printed circuit boards is disposed in each chamber formed by the hoods and dividers.

Abstract: An integrated test circuit includes pads of a padset for testing multiple device under test units (MDUTs). The MDUTs each include devices under test (DUTs). A first integrated test circuit metal layer is patterned to connect the pads to N MDUTs such that a first set of pads are employed for enabling testing of each MDUT and a second set of pads are designated for testing individual DUTs associated with the enabled MDUTs such that N parallel tests may be concurrently performed.

Abstract: A conveyor mountable carrier is adapted to test an electronic device that has electrical leads. The carrier includes a body having a clamping area defined by a base surface and at least one lateral stop surface. The body also defines a pneumatic channel for directing pressurized air toward the clamping area. A clamp is movably connected to the body and has an engaging portion that is positioned opposite the stop surface of the body. The clamp is moveable between an engaged position in which the electronic device is securable to the body and a disengaged position in which the electronic device is releasable from the body.