Dut Socket Or Carrier Patents (Class 324/756.02)
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Patent number: 8138777Abstract: A TCP-type semiconductor device has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film. Each lead has: a first terminal portion including a first end that is one end of the each lead and connected to the semiconductor chip; and a second terminal portion including a second end that is the other end of the each lead and located on the opposite side of the first terminal portion. I a terminal region including the second terminal portion of the each lead, the plurality of leads are parallel to each other along a first direction, the plurality of leads include a first lead and a second lead that are adjacent to each other, and the first lead and the second lead are different in a position of the second end in the first direction.Type: GrantFiled: October 15, 2009Date of Patent: March 20, 2012Assignee: Renesas Electronics CorporationInventor: Suguru Sasaki
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Publication number: 20120049877Abstract: A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.Type: ApplicationFiled: May 27, 2010Publication date: March 1, 2012Applicant: HSIO TECHNOLOGIES, LLCInventor: James Rathburn
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Patent number: 8125236Abstract: A main board according to example embodiments may include a substrate and at least one socket. The at least one socket may directly connect a memory module to the substrate in a direction parallel to the substrate. A memory mounting test system including the main board may occupy a smaller space, because the memory module is connected to the main board in a direction parallel to the main board.Type: GrantFiled: March 29, 2010Date of Patent: February 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Kuk Lee, Seung-Hee Lee
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Publication number: 20120025860Abstract: A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning portions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier.Type: ApplicationFiled: November 23, 2010Publication date: February 2, 2012Applicant: Global Unichip CorporationInventors: Yu-Min Sun, Chih-Feng Cheng
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Publication number: 20120025861Abstract: A test device is provided. The test device includes a first via which transmits a supply voltage, a second via which transmits a ground voltage, a test board including a plurality of test signal vias for transmitting a plurality of test signals, a capacitor disposed on an upper part of the test board and connected between the first via and the second via, and a test socket which electrically connects a device under test (DUT) with the test board. The test socket includes a first region including a flat lower surface bordering the test board, a second region including an uneven lower surface, a plurality of first contactors which are disposed in the first region and which are connected to the plurality of vias, and two second contactors which are disposed in the second region and which are connected to two terminals of the capacitor.Type: ApplicationFiled: August 2, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwan Wook PARK, Woo Seop KIM, Sung Bum CHO
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Patent number: 8085059Abstract: An RF chip test method is disclosed. The RF chip test method includes disposing an RF chip within a chip socket, with the RF chip having at least one RF pin and at least one non-RF pin, the chip socket having conductive elements, and the conductive elements contacting the RF pin and the non-RF pin; connecting the non-RF pin to a ground end and connecting the RF pin to an RF measuring instrument; measuring a S11 parameter of the RF pin using the RF measuring instrument; and comparing the S11 parameter with an allowable range so as to judge the contact condition between the RF pin and the conductive element.Type: GrantFiled: January 20, 2009Date of Patent: December 27, 2011Assignee: King Yuan Electronics Co., Ltd.Inventors: Hsuan-Chung Ko, Hsiu-Ju Chen
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Publication number: 20110304349Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.Type: ApplicationFiled: June 11, 2010Publication date: December 15, 2011Applicant: Texas Instruments IncorporatedInventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Margaret Simmons-Matthews, Jeff West
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Patent number: 8076952Abstract: A support block is provided with a plurality of through holes for supporting probes. The probes for signals, for power supply and for grounding are secured in the through holes of the support block and electrically interconnect electrode terminals of a device to be inspected, which is provided on one face side of the support block, and wiring terminals connected to an inspection unit, which is provided on the other face side of the support block. A device guide is integrally formed with or separately fixed to the one face side of the support block, and includes an opening having a square shape in a plan view for guiding the device to be inspected. A centering mechanism adjusts a position of the device to be inspected at a center position of the opening of the device guide.Type: GrantFiled: July 27, 2007Date of Patent: December 13, 2011Assignee: Yokowo Co., Ltd.Inventor: Takuto Yoshida
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Publication number: 20110298486Abstract: A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.Type: ApplicationFiled: August 15, 2011Publication date: December 8, 2011Applicant: KINGSTON TECHNOLOGY CORP.Inventors: Ramon S. Co, Kevin J. Sun
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Patent number: 8058888Abstract: A test apparatus for an electronic device package is provided, which includes a test socket having a first portion with a recess for receiving an electronic device package having external terminals arranged in a terminal configuration and a second portion. An interchangeable insert board is disposed between the first portion and the second portion and extended on the recess, which includes first contact pads arranged in a first pad configuration compatible with the terminal configuration and facing the recess and second contact pads arranged in a second pad configuration and disposed between the first and the second portions. Trace layers each electrically connects one of the first contact pads to one of the second contact pads. The contact pins each penetrates through the second portion and electrically connects to one of the second pads, wherein the contact pins are arranged in a pin configuration compatible with the second pad configuration.Type: GrantFiled: October 13, 2009Date of Patent: November 15, 2011Assignee: Nanya Technology CorporationInventor: Shun-Ker Wu
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Patent number: 8054095Abstract: A probe structure for an electronic device is provided. In one aspect, the probe structure includes an electrically insulating carrier having one or more contact structures traversing a plane thereof. Each contact structure includes an elastomeric material having an electrically conductive layer running along at least one surface thereof continuously through the plane of the carrier. The probe structure includes one or more other contact structures adapted for connection to a test apparatus.Type: GrantFiled: September 30, 2005Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Gareth Geoffrey Hougham, Ali Afzali, Steven Allen Cordes, Paul W. Coteus, Matthew J. Farinelli, Sherif A. Goma, Alphonso P. Lanzetta, Daniel Peter Morris, Joanna Rosner, Nisha Yohannan
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Publication number: 20110254945Abstract: An electronic device handling apparatus, which handles an electronic device under test having a first main surface provided thereon with first device terminals and a second main surface provided thereon with second device terminals, includes: a contact arm having a holding-side contact arm to which a first socket is attached and a suction pad which holds the electronic device under test; an alignment apparatus which positions the first socket and the electronic device under test; and the alignment apparatus which positions, with respect to a second socket, the electronic device under test being held by the suction pad and contacting the first socket, wherein the contact arm presses the second device terminals of the electronic device under test to the second socket.Type: ApplicationFiled: April 8, 2011Publication date: October 20, 2011Applicant: ADVANTEST CORPORATIONInventors: Aritomo KIKUCHI, Hiroto NAKAMURA
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Patent number: 8040148Abstract: This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.Type: GrantFiled: November 2, 2005Date of Patent: October 18, 2011Assignee: Taiyo Yuden Co., Ltd.Inventor: Masayuki Satoh
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Publication number: 20110248737Abstract: It is an object to use an additional circuit to increase speed and functioning of an existing test apparatus at a low cost. Provided is a test apparatus that is connected to a socket board corresponding to a type of device under test and tests the device under test. The test apparatus comprises a test head including therein a test module that tests the device under test; a function board that is connected to the test module in the test head via a cable and also connected to the socket board; and an additional circuit that is loaded on the function board and connected to the test module and the device under test.Type: ApplicationFiled: February 24, 2011Publication date: October 13, 2011Applicant: ADVANTEST CORPORATIONInventors: Satoshi TAKESHITA, Junji EBARA, Tomoyuki TAKAMOTO, Koei NISHIURA, Hidehiko YASUNO
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Patent number: 8035408Abstract: A memory module test socket can accept modules with bent or warped printed-circuit boards (PCBs). A support plate is mounted above a Personal Computer (PC) motherboard by standoffs. An extender card fits through a slot in the support plate. The bottom edge of the extender card is plugged into a motherboard memory module socket on the motherboard. The top of the extender card has an extender socket that sits atop the support plate. End guides are mounted to the support plate and clamp down the extender socket. Funnel guides formed in the end guides have a funnel shape to guide ends of a memory module for better alignment when inserted into the extender socket. A pusher plate with a triangular guide or a perpendicular rod applies a perpendicular force on the middle of a warped memory module to align the middle to the extender socket during insertion.Type: GrantFiled: December 10, 2010Date of Patent: October 11, 2011Assignee: Kingston Technology Corp.Inventor: Ramon S. Co
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Publication number: 20110227595Abstract: An interface member 52, being provided between a body part of a test head 5 to be used in an electronic device testing apparatus 10 and a socket board 51 having a socket 512 to be mounted with an electronic device 2 to be tested and a plurality of socket side connectors 514 electrically connected to the socket 512, for electrically connecting the body part of the test head 5 with the socket board 51: comprising IF side connectors 524 to be engaged with the socket side connectors 514, an upper frame 521 for supporting the IF side connector 524 and a frame-shaped lower frame 522 provided under the upper frame 521; wherein the upper frame 521 has a hole 521h formed thereon for allowing a plurality of IF side connectors 524 to pass through, a heat insulator 525 is provided between a plurality of IF side connectors 524 passing through the hole 521h, and inside the frame-shaped lower frame 522 is filled with a plurality of block-shaped heat insulators 526, wherein cables 524c of the IF side connectors 524 pass throType: ApplicationFiled: October 9, 2008Publication date: September 22, 2011Applicant: ADVANTEST CORPORATIONInventor: Satoshi Takeshita
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Patent number: 8022719Abstract: A carrier tray for use with a prober is arranged to allow the prober to measure or test not only semiconductor wafers but also semiconductor packages and accurately position each of different-shaped semiconductor packages. A carrier tray includes a lowermost tray and an uppermost tray interposing therebetween an intermediate tray. The lowermost and uppermost trays and are each of a circular shape having a diameter D1. A diameter D3 of the intermediate tray is smaller than the diameter D1. The intermediate tray is centrally formed with a screw hole portion in which a locking spacer screw is screwed. A semiconductor package is to be placed in a package holding pocket. With the locking spacer screw, the intermediate is slidable in an X and Y directions, so that the X and Y coordinates of the semiconductor package are determined uniquely relative to the carrier tray.Type: GrantFiled: December 9, 2009Date of Patent: September 20, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Tomita, Hiroyuki Tokuyama
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Patent number: 8011092Abstract: The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that compression of the sockets opens a clamping mechanism. A chip can be placed within a socket with a manipulator and aligned during compression of the socket. Subsequently, the compression of the socket can be released while the manipulator remains in contact with the chip to hold the chip in place until the clamping mechanism is retaining the chip in the socket. The chip can then be released from the manipulator. The invention also includes systems for utilizing removable nests to align various chip geometries within generic socket designs.Type: GrantFiled: September 11, 2008Date of Patent: September 6, 2011Assignee: Micron Technology, Inc.Inventors: Daniel P. Cram, A. Jay Stutzman
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Publication number: 20110204914Abstract: A system for connecting a test pin of automatic test equipment (ATE) to devices for testing includes a first handler for manipulating a first portion and a second handler for manipulating a second portion of devices. A first wire connected to first socket(s) and a second wire connected to second socket(s) are connected to a relay connected to the test pin. The first handler connects first portion devices to the first socket. The second handler connects second portion devices to the second socket. A controller connects the first handler, second handler, and relay, for switching the relay to the first wire for testing in first socket if the first handler has connected any first portion device, and to the second wire for testing in second socket if the second handler has connected any second portion device. The controller multiplexes two handlers, or dual manipulators, asynchronously for immediate switch of testing.Type: ApplicationFiled: February 7, 2011Publication date: August 25, 2011Inventor: Howard Roberts
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Patent number: 8004300Abstract: A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral sideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed.Type: GrantFiled: October 1, 2009Date of Patent: August 23, 2011Assignee: Circuit CheckInventors: Troy Fossum, David Kariniemi
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Publication number: 20110193584Abstract: A system for communicatively connecting devices for testing to respective test pins of a test head of an automatic test equipment (ATE). The system includes a tester interface device for communicative connection to the test pins of the ATE. The tester interface device includes a first connector and a second connector. The first connector is communicatively connected by the tester interface device to a first group of the test pins and the second connector is communicatively connected by the tester interface device to a second group of the test pins. The first group and the second group can be different test pins, same test pins, or combinations of some same and some different test pins. A first pogo pin block device of the system is communicatively connected to the first connector, and a second pogo pin block device communicatively connected to the second connector.Type: ApplicationFiled: February 7, 2011Publication date: August 11, 2011Inventor: Howard Roberts
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Publication number: 20110193585Abstract: A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Applicant: KINGSTON TECHNOLOGY CORP.Inventors: Ramon S. Co, Kevin J. Sun
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Patent number: 7994804Abstract: The electronic component tester includes: a socket configured to supply power to connection terminals for operating an electronic component; an electronic component mount member on which the electronic component is to be mounted; and a temperature adjusting member which is configured to come into contact with the electronic component mount member to keep the electronic component at a predetermined temperature. The electronic component mount member includes a heat transfer plate on which the electronic component is to be mounted and which is configured to come into contact with the temperature adjusting member, and an electronic component cover for covering the electronic component. The heat transfer plate includes through holes.Type: GrantFiled: October 15, 2009Date of Patent: August 9, 2011Assignee: Panasonic CorporationInventors: Takanori Miya, Isao Hayami, Shoichi Tanaka
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Publication number: 20110187400Abstract: In a semiconductor test apparatus, a first device is tested as a device under test in a state where the first device provided with a transmitter transmitting a signal and a second device provided with a receiver receiving the signal transmitted by the transmitter, are connected together. The transmitter includes an equalizer circuit that shapes the waveform of the differential signal to be transmitted. The receiver includes a latch circuit that latches data corresponding to the differential signal thus received with the use of a clock, the timing of which is variable. A control unit varies, in a matrix, a parameter of the equalizer circuit and an edge timing of the clock CLK supplied to the latch circuit.Type: ApplicationFiled: April 14, 2008Publication date: August 4, 2011Applicant: ADVANTEST CORPORATIONInventor: Daisuke Watanabe
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Patent number: 7990169Abstract: An electrical testing device used for testing an electronic device under test. The electrical testing device includes a cable configured for receiving a test signal and transmitting the received test signal therethrough, and a testing unit connected to the cable and configured for analyzing the test signal. The cable includes a flexible body, a number of first connectors connected to an end of the flexible body configured for receiving a test signal from the electronic device under test, and a second connector connected to the other end of the flexible body configured for transmitting the test signal between the flexible body and the testing unit.Type: GrantFiled: March 5, 2009Date of Patent: August 2, 2011Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventor: Kim-Yeung Sip
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Publication number: 20110156739Abstract: A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Hsiao-Chuan CHANG, Ming-Hsiang CHENG, Tsung-Yueh TSAI, Yi-Shao LAI, Ming-Kun CHEN
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Patent number: 7957732Abstract: In order to mount a mobile phone in a test device, the current between the battery unit and the phone unit is fed through a switch unit. The switch unit contains at least one switch for interrupting the current, e.g. for resetting the mobile phone after malfunction.Type: GrantFiled: June 13, 2006Date of Patent: June 7, 2011Assignee: Swissqual License AGInventor: Hanspeter Bobst
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Patent number: 7956632Abstract: The socket of the present invention includes a lid having a first protrusion on the reverse side, and a first terminal connected electrically to the first protrusion, and a main body having a second terminal on the upside, and a third terminal connected electrically to the second terminal on the reverse side, in which an electronic component is contained in the main body, and the first terminal and the second terminal are connected electrically in the space enclosed and fixed by the lid. The inspection system of the present invention includes a socket of the present invention, and an evaluation board for connecting a third terminal of the socket electrically to the inspection apparatus of the electronic component, and propagating an inspection signal.Type: GrantFiled: September 18, 2007Date of Patent: June 7, 2011Assignee: Panasonic CorporationInventor: Masahiro Takatori
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Patent number: 7956631Abstract: A test socket, adapted for connecting the semiconductor package and a printed circuit board comprises a base and a plurality of contacts received in the base. The base has a retaining board defining a plurality of first receiving holes and a positioning board defining a plurality of second receiving holes. The contacts has a contacting portion, an elastic portion and a retaining portion, the elastic portion is disposed between the retaining board and the positioning board and protruding rightward, and the contacting portion extends beyond the elastic portion and defines a acute angle with a horizontal line in a right hand before contacting with the semiconductor package to prevent the contacting portion from scratching with the left inner sidewall of the second receiving hole when pushed downward by the semiconductor package and rotating leftward.Type: GrantFiled: March 10, 2009Date of Patent: June 7, 2011Assignee: Hon Hai Precision Ind. Co., Ltd.Inventors: Ke-Hao Chen, Wen-Yi Hsieh
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Publication number: 20110121850Abstract: Spring assemblies and a test socket using the spring assemblies. The spring assemblies are used in a test socket electrically connecting lead terminals of a semiconductor chip to test terminals of a test device by contacting the lead terminals and the test terminals, and include: first springs in which a first steel wire having elasticity and conductivity is coiled in a spiral in one direction; and second springs in which a second steel wire having elasticity and conductivity is coiled in a spiral in an opposite direction to the direction in which the first springs are coiled, which have outer diameters narrower than inner diameters of the first springs, and are inserted into the first springs. Accordingly, electric resistances and inductances of two spring assemblies coiled in a spiral are reduced to improve electricity transmission characteristic. A height of a test socket is easily adjusted using spring assemblies having desired lengths.Type: ApplicationFiled: July 20, 2009Publication date: May 26, 2011Inventor: Jae Hak Lee
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Patent number: 7944223Abstract: The present invention discloses a burn-in testing system including a burn-in board and a burn-in testing apparatus, the burn-in board including: a first interface component, adapted to connect with the burn-in testing apparatus for signal input and/or output between the burn-in board and the burn-in testing apparatus; and a second interface component, adapted to connect with a device under test for signal input and/or output between the burn-in board and the device, wherein the burn-in testing system further includes a pin matching unit flexibly connected with the burn-in board and adapted to adjust signal connection relationship between the first interface component and the second interface component according to a pin description of the device.Type: GrantFiled: September 14, 2010Date of Patent: May 17, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Venson Chang, Kary Chien, Shunwang Chiang
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Patent number: 7940070Abstract: A flexible redistribution membrane and a piece of silicon rubber is used in a testing fixture for testing a singulated bare die. The silicon rubber is used as a cushion under the flexible redistribution membrane against the downward pressure from the bare die during testing so that the top pads of the flexible redistribution membrane can be electrically tight coupling to bottom pads of the bared die to be tested.Type: GrantFiled: April 8, 2009Date of Patent: May 10, 2011Assignee: Nichepac Technology Inc.Inventor: Cheng-Lien Chiang
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Publication number: 20110102008Abstract: A socket for testing a semiconductor chip includes a base cover, a conductive sheet, upper plungers, a housing, lower plungers and a support plate. The base cover has a coupling opening in the central portion thereof, and the conductive sheet is fitted into the coupling opening of the base cover and includes conductive parts and an insulation part. The upper plungers are seated onto upper ends of the conductive parts and come into contact with corresponding terminals of the semiconductor chip. The housing has insert holes at positions corresponding to the upper plungers and fastens the upper plungers to the corresponding conductive parts. The lower plungers are provided under lower ends of the conductive parts and come into contact with corresponding terminals of a PCB to electrically connect the conductive parts to the PCB.Type: ApplicationFiled: March 11, 2010Publication date: May 5, 2011Applicant: Leeno Industrial Inc.Inventor: Chae Yoon Lee
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Publication number: 20110102009Abstract: A test socket, an electrical connector, and a method for manufacturing the test socket. In detail, the test socket for electrically connecting terminals of a semiconductor device to pads of a test apparatus includes: a housing having through-holes vertically extending to correspond in position to the terminals of the semiconductor device; contact pins disposed to correspond in position to the through-holes of the housing and contacting the terminals of the semiconductor device; and elastic members connected to the contact pins in the through-holes of the housing to contract and expand, wherein the elastic members are adhered to the contact pins by using an adhesive material.Type: ApplicationFiled: June 19, 2009Publication date: May 5, 2011Inventor: Jae Hak Lee
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Patent number: 7932737Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.Type: GrantFiled: December 30, 2008Date of Patent: April 26, 2011Assignee: Cascade Microtech, Inc.Inventors: Frank-Michael Werner, Matthias Zieger, Sebastian Giessmann
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Patent number: 7932739Abstract: An apparatus for supporting BGA packages for one or more testing processes is disclosed. The apparatus includes a substrate member. The substrate member has a plurality of contact pads, with each of the contact pads being spatially disposed around a peripheral region of the substrate. The apparatus further includes a plurality of contact regions spatially configured on a portion of the substrate member. Each of the plurality of contact regions is numbered from 1 through N being electrically connected to respective contact pads numbered from 1 through N. The plurality of contact regions is configured to provide electrical contact to respective plurality of balls provided on a BGA package. The apparatus additionally includes a holder device coupled to the substrate member. The holder device is adapted to mechanically hold the BGA package in place to provide mechanical contact between the plurality of balls and respective plurality of contact regions.Type: GrantFiled: May 7, 2009Date of Patent: April 26, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Shan An Liang, Chun Kui Ji, Ping Lung Liao, Tian Qin
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Publication number: 20110084720Abstract: A test apparatus for an electronic device package is provided, which includes a test socket having a first portion with a recess for receiving an electronic device package having external terminals arranged in a terminal configuration and a second portion. An interchangeable insert board is disposed between the first portion and the second portion and extended on the recess, which includes first contact pads arranged in a first pad configuration compatible with the terminal configuration and facing the recess and second contact pads arranged in a second pad configuration and disposed between the first and the second portions. Trace layers each electrically connects one of the first contact pads to one of the second contact pads. The contact pins each penetrates through the second portion and electrically connects to one of the second pads, wherein the contact pins are arranged in a pin configuration compatible with the second pad configuration.Type: ApplicationFiled: October 13, 2009Publication date: April 14, 2011Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Shun-Ker Wu
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Publication number: 20110084721Abstract: A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads.Type: ApplicationFiled: November 12, 2010Publication date: April 14, 2011Applicant: ADVANTEST CORPORATIONInventor: Shinichi HAMAGUCHI
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Publication number: 20110080187Abstract: In one embodiment, a device interface board is provided which includes a printed circuit board with a DUT interface structure, such as socket, associated with a DUT side of the printed circuit board. A high frequency connector and electronic component are mounted in a cavity formed in a back side of the printed circuit board. A signal via through the printed circuit board couples the high frequency connector and electronic component with the DUT interface structure. An encapsulating structure may be provided, which covers the cavity while allowing a cable to connect to the high frequency connector.Type: ApplicationFiled: October 2, 2009Publication date: April 7, 2011Inventors: Peter Hotz, Wolfgang Steger
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Publication number: 20110074457Abstract: An improved efficiency system for testing electronic components in a motherboard/daughterboard assembly in which the daughterboard is mounted in spaced parallel relationship the to motherboard includes one or more device-under-test socket sub-assemblies having a test socket thereon for receiving a device-under-test and a connector component for disengagable connection to a complementary connector component on the daughterboard with the socket sub-assembly effecting interengagement of the complementary connector component on the daughterboard via an opening in the motherboard to allow ready access to the test socket for temporary installation, testing, and removal of a device-under-test.Type: ApplicationFiled: January 17, 2010Publication date: March 31, 2011Inventors: Ryan B. Roderick, Ronald D. Kimmel
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Publication number: 20110050264Abstract: According to one embodiment, a substrate inspection apparatus includes a probe socket, a probe pin, and an adaptor. The probe socket is fixed to an inspection jig on which a substrate is provided, one end of the probe socket being connected to a processor. The probe pin is attached to the other end portion of the probe socket, includes a tip shape conforming to an inspection point of the substrate with which the probe pin is in contact, and including at least one of a projection and a groove designed to specify the tip shape on a side on which the probe pin is attached to the probe socket. The adaptor is attached to the other end portion of the probe socket, and including a through hole formed in conformity with the shape of the side on which the probe pin is attached to the probe socket.Type: ApplicationFiled: August 25, 2010Publication date: March 3, 2011Inventor: Kiyoharu Kurosawa
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Publication number: 20110001505Abstract: The present invention dicloses test sockets fabricated by MEMS technology for testing of semiconductor devices. Semiconductor device test sockets fabricated by MEMS technology in accordance with one or more embodiments of the invention offer many unique advantages over conventional test sockets (e.g. sockets utilizing pogo-pins). In one embodiment of the invention, a novel test socket includes a substrate with multiple cavities of certain depths in middle region of one side, electrical contacts (electrodes) of cantilever type directly above the cavities making individual contact with each contactor of semiconductor device, and multiple signal paths electrically connecting the cantilever type contacts on one side of the substrate and the loadboard PCB(printed circuit board) or motherboard PCB placed on the other side of the substrate.Type: ApplicationFiled: July 2, 2010Publication date: January 6, 2011Inventor: Jaewoo Nam
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Publication number: 20100315112Abstract: An integrated probe card and socket adapter includes probe needles for probing a wafer including a plurality of CSP IC each having a plurality of bumps. A socket adapter includes a socket body having an elevated portion and a recessed base portion. The recessed base portion has a base portion thickness and includes a plurality of base portion through-holes that align with and receive the bumps on at least one of said plurality of CSP IC after singulation (singulated CSP IC) for securing the singulated CSP IC thereto. The elevated portion includes a plurality of elevated portion through-holes for fastening to the probe card when the probe card is underlying. The base portion thickness is sized so that the probe needles extend into the base portion through-holes a sufficient distance to contact the bumps of the singulated CSP IC for testing using the probe card.Type: ApplicationFiled: May 6, 2010Publication date: December 16, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hung Quoc Nguyen, Damian Peter Lewis, Perry Fitzgerald Daniels