Abstract: The present invention relates to a socket device for testing a semiconductor device. More particularly, the present invention relates to a socket device that is capable of testing ball grid array (BGA) and land grid array (LGA) type semiconductor devices, or BGA/LGA hybrid semiconductor devices according to the shapes of leads of the semiconductor devices. A latch structure for pressing and holding a semiconductor device is improved such that a roller is provided at the front end of a latch so as to minimize wear caused by friction with a sandpaper-like surface on an upper surface of the semiconductor device, even in the case of approximately one hundred thousand or more rounds of testing, thereby remarkably extending the life of the socket device, increasing testing efficiency, and reducing costs.

Abstract: An inspection apparatus for inspecting a wiring board having an opposing electrode facing an upper face of the wiring board, a capacitance meter electrically connected to the opposing electrode and the multi-layer wiring, and measuring capacitance between the opposing electrode and the multi-layer wiring, ground, a switch box that is connected to the ground wirings, the opposing electrode, and the ground, and switches to select between a first connection state, in which all the ground wirings are electrically connected to the opposing electrode, and a second connection state, in which one ground wiring is electrically connected to the ground. A control unit extracts a capacitance value by calculating difference between a first capacitance and a second capacitance, wherein capacitance in units of layers of the multi-layer wiring are measured based on the capacitance value extracted by the control unit.

Abstract: A testing tool includes a tool body, a panel imitation member disposed on the tool body, an indicating device, and a probe device. A test panel cover is detachably disposed on the tool body. The probe device is disposed in the panel imitation member and includes a probe and a conductive member disposed under the probe. The probe is elastically disposed through the panel imitation member between initial and triggering positions. When the probe is located at the initial position, the probe extends out from the panel imitation member to abut against the test panel cover. When the test panel cover is sunken inward to contact with the panel imitation member so as to drive the probe to the triggering position, the probe contacts with the conductive member to electrically conduct the indicating device.

Abstract: A handler includes a base having an opening portion, a first hand which transports a transport target, a first transport section which transports the first hand to above the opening portion and moves the first hand down, a second hand which transports the transport target, a second transport section which transports the second hand to above the opening portion and moves the second hand down, and a control section which controls an operation of the first transport section and an operation of the second transport section. The handler has a state where the first hand and the second hand are disposed in parallel to the opening portion while being close to each other toward above the opening portion.

Abstract: A computer-executable method, apparatus, or computer program product for automating the analysis of interconnects used with data storage systems, where one or more measured parameters, such as an S-parameter, may be used to determine signal characteristics of the interconnects.

Abstract: A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.

Abstract: A semiconductor testing jig is provided with a conductive stage including a plurality of mounting portions on which a plurality of vertical semiconductor devices are each individually disposed with lower surface electrodes being in contact with the plurality of mounting portions, an insulating frame portion having a lattice pattern that is disposed on the stage and surrounds each of the plurality of mounting portions in plan view to define each of the mounting portions, and an abrasive layer disposed in a position in the frame portion, the position facing each of the vertical semiconductor devices disposed on the mounting portions.

Abstract: An apparatus includes a metal housing, and a pogo pin penetrating through the metal housing. The pogo pin has a first end extending out of a first surface of the metal housing, and a second end extending out of a second surface of the metal housing, with the first and the second surfaces being opposite surfaces of the metal housing. A membrane is attached to the metal housing, wherein the membrane includes a metal line embedded therein. A metal pad is in physical contact with the pogo pin, wherein at least a portion of the metal pad is inside the membrane.

Abstract: A circuit system for testing a chip is provided. The circuit system includes a first layer coupled with a plurality of ground communication mediums. Each ground communication medium facilitates communication of a ground signal. The circuit system includes a second layer coupled with a first integrated circuit chip. The second layer is coupled with a plurality of radio frequency (RF) communication mediums. The RF communication mediums facilitate communication of RF signals. The first integrated circuit chip communicates via one of the RF signals and the ground signal with a second integrated circuit chip. The first and second layers are used to probe the RF signals and the ground signal.

Abstract: A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

Abstract: The present invention discloses a glass substrate cassette and pick-and-place system for glass substrates. The glass substrate cassette comprises: a cassette case, comprising a pair of side walls disposed in parallel and vertically; and a plurality of support racks, disposed inside the cassette case for supporting glass substrates, each support rack comprising a pair of connecting elements supporting respectively the pair of side walls and a plurality of support elements lined up in parallel along a first horizontal direction and connected to the pair of connecting elements, connecting element able to move along the first horizontal direction with respect to the side walls and at least partially beyond the cassette case. The support rack of the present invention can move beyond cassette to realize random pick-and-place of glass substrate at any layer.

Abstract: A fixture in which an attractive magnetic force is utilized to join two parts of a container or housing together is discussed. The fixture comprises a fixture body portion, a fixture base portion and a removable fixture plate portion. At least one body magnet resides within the fixture body portion and at least one plate magnet resides within the removable fixture plate. The fixture body and plate magnets are positioned such that when they are brought together, an attractive magnetic force pulls the plate towards the fixture body. Therefore, when the respective housing portions are positioned within the fixture, the magnetic force compresses the housing portions together.

Abstract: A probe apparatus includes a card clamp unit detachably supporting a probe card; and a wafer mounting table adsorbing the semiconductor wafer and bringing electrodes on the semiconductor wafer into contact with the probes. In order to mount the semiconductor wafer including an annular portion protruding from a rear surface of an outer peripheral portion and a thin portion having a thickness smaller than the annular portion, the wafer mounting table includes a planar portion on which the thin portion is mounted; and a step-shaped portion which is formed at an edge of the planar portion and mounts the annular portion thereon. Multiple circular vacuum chuck grooves are concentrically formed in the planar portion, and at least some of the vacuum chuck grooves are connected to multiple vacuum paths through which vacuum evacuation is performed at multiple positions separated from each other by 90° or more along a circumferential direction.

Abstract: Provided is a handler apparatus which can connect devices under test to sockets of a test apparatus quickly and with low power consumption. The handler apparatus for conveying and connecting a plurality of devices under test to a plurality of sockets provided on a test head of a test apparatus, includes a position adjusting section that moves each of the plurality of devices under test on the test tray and adjusts the position thereof to a corresponding one of the plurality of sockets; and a device mounting section that mounts the plurality of devices under test whose positions have been adjusted by the position adjusting section, to the plurality of sockets.

Abstract: A test platform includes a base, a supporting member rotatably supported on the base, a laser emitter mounted on the base, and a laser receiver mounted to the supporting member and aligning with the laser emitter. The supporting member includes a network socket electrically connected to the laser receiver. The laser emitter is electrically connected to a network communication device.

Abstract: A probe card and method are provided for testing magnetic sensors at the wafer level. The probe card has one or more probe tips having a first pair of solenoid coils in parallel configuration on first opposed sides of each probe tip to supply a magnetic field in a first (X) direction, a second pair of solenoid coils in parallel configuration on second opposed sides of each probe tip to supply a magnetic field in a second (Y) direction orthogonal to the first direction, and an optional third solenoid coil enclosing or inscribing the first and second pair to supply a magnetic field in a third direction (Z) orthogonal to both the first and second directions. The first pair, second pair, and third coil are each symmetrical with a point on the probe tip array, the point being aligned with and positioned close to a magnetic sensor during test.

Abstract: A test carrier includes a base member and a cover member. The base member includes a multi-layer board including a wiring line that is electrically connected to a die and a base film that supports the multi-layer board. The cover member includes a frame-shaped cover frame having an opening formed therein. The size of the multi-layer board is larger than the size of the die and is smaller than the size of the opening in a direction along a surface that is opposite to the die.

Abstract: An electronic device testing apparatus includes a housing unit which disassembles an empty test carrier and assembles the test carrier while housing an untested die in the test carrier, a test unit which tests the die housed in the test carrier, and a retrieving unit which disassembles the test carrier, retrieves the tested die from the test carrier, and reassembles the empty test carrier.

Abstract: Provided is an electrical test socket that is arranged between a terminal of a test target device and a pad of test equipment in order to electrically connect the terminal and the pad, the electrical test socket including: a socket body including a central hole at a center thereof in order to house the test target device inside; a pin connection member comprising a plurality of conductive pins that are arranged on locations corresponding to the terminal of the test target device housed in the central hole of the socket body, and whose upper end contacts the terminal of the test target device, and a housing having penetration holes into which the conductive pins are inserted to support the conductive pins; and a sheet-type connection member in which a plurality of conductive parts are arranged on locations corresponding to the conductive pins, wherein the plurality of conductive parts are arranged on a bottom portion of the pin connection member, exhibit conductivity only in a thickness direction, and are elas

Abstract: A testing assembly for testing a plurality of semiconductor devices comprising a carrier assembly adapted to hold the plurality of semiconductor devices at predetermined locations therein that is operably connectable with a plurality of different socket assemblies. A universal socket assembly is also described.

Abstract: A method of testing semiconductor devices includes placing a plurality of semiconductor devices in a carrier assembly and performing at least one testing operation on the plurality of semiconductor devices while they remain inside the carrier assembly.

Abstract: A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.

Abstract: A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material.

Abstract: An integrated circuit (IC) device tester maintains a set point temperature on an IC device under test (DUT) having a die attached to a substrate. The tester includes a thermal control unit and a fluid management system configured to supply the thermal control unit with fluids for pneumatic actuation, cooling, and condensation abating. The tester can includes a box enclosing the thermal control unit thereby providing a substantially isolated dry environment during low humidity testing of the DUT. The heat exchange plate may include an inner structure for thermal conductivity enhancement.

Abstract: A device for measuring electronic components having a plurality of conductors applied to a dielectric cable carrier, which conductors are each connected both to a contact finger and to a connection contact, such that a switch is integrated in at least one of the conductors, via which the conductor can be additionally connected to a ground connection.

Abstract: A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.

Abstract: A method of testing a packaged semiconductor device under test (DUT) including a leadframe having a plurality of pins and at least one thermal pad with a semiconductor die having topside bond pads wire-bonded by bond wires to the plurality of pins and secured to the thermal pad. A leadframe sheet is provided including a plurality of packaged DUTs including support members that connect to the packaged DUTs. The thermal pads are shorted to one another, and the leadframe sheet is trimmed for electrically isolating the pins from one another. A first electrical contact is provided to the thermal pad. Active pins of the plurality of pins are electrically contacted with a contactor. Automatic testing identifies shorts between the active pins and the thermal pad.

Abstract: A test carrier includes a film-shaped base film which has first bumps which contact test pads of a die; and a cover film which is superposed over the base film, and the test carrier holds the die between the base film and the cover film. The first bumps are relatively higher than second bumps which the die has.

Abstract: Electrical characteristics of a mounting board over which a semiconductor device is mounted is improved. A mounting board (wiring board) includes a plurality of first through holes and second through holes extending from its upper surface bearing a semiconductor device (semiconductor package) to its lower surface and through-hole wirings formed in the respective through holes. The mounting board has a capacitor arranged on its lower surface and electrically connected with the semiconductor device via second electrodes. Among a plurality of first electrodes formed on the upper surface of the mounting board, the several first electrodes to be connected with the capacitor are connected with one wiring formed in a first through hole with a larger diameter than a signal transmission path.

Abstract: A socket which enables occurrence of contact defects to be suppressed is provided. A socket 11 to which a test carrier 20, which has: a base film 32 on which bumps 324 are formed for contact with electrode pads 51 of a die 50; and external terminals 312 which are electrically connected to the bumps 324, is electrically connected comprises: contactors 125 which contact external terminals 312; and an elastic member 131 which pushes against bump-forming portions 32a and bump-surrounding portions 32b on the base film 32. The elastic member 131 has: a first elastic layer 132; and a second elastic layer 133 which is more flexible than the first elastic layer 132, and a second elastic layer 133 is laid over the first elastic layer 132 and contacts the base film 32.

Abstract: A device tester for an IC device under test (DUT), the DUT having a substrate and an attached die. The device tester includes a thermal control unit and a test socket assembly which conforms to the DUT's profile. The thermal control unit includes a pedestal assembly, a heater having a fuse coupled to a heating element, a substrate pusher, and a force distributor for distributing force between the pedestal assembly and the substrate pusher. The test socket assembly includes a socket insert that supports and also conforms to the DUT's profile.

Abstract: A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage.

Abstract: A test structure operable to receive an integrated circuit is described. The test structure includes a substrate, a test contact member, a base structure, an aperture, and a conductive contact member. The test contact member extends from a surface of the substrate and has a tip at one end. The base structure is suspended above the surface of the substrate and has an aperture in which the test contact member is positioned. Furthermore, the conductive member is disposed in the aperture. The conductive member is positioned further away from the surface of the substrate compared to the tip of the test contact member. A method to test an integrated circuit (IC) utilizing the test contactor is also described.

Abstract: A test carrier that temporarily accommodates a die includes: a first wiring pattern that electrically connects an external terminal of the test carrier and a TSV of the die; and a second wiring pattern that electrically connects the TSVs.

Abstract: [Problem] A carrier assembly apparatus which is able to be streamlined in structure is provided. [Solution] The carrier assembly apparatus 1 comprises: an assembly table 31 which supports a base member 70 on which a die 90 is placed, a holding head 46 which holds a cover member 80, a pressure reduction head 44 which has a pressure reduction chamber 443 accommodating the cover member 80 and having an opening part 444 and which abuts against the assembly table 31 so as to form a sealed space, a first elevating actuator 43 which simultaneously move the holding head 46 and the pressure reduction head 44 to the assembly table 31, and a second elevating actuator 47 which moves the holding head 46 relative to the pressure reduction head 44.

Abstract: Structures and techniques for restraining devices for testing. Test sockets may retain devices under test using one or more retention members protruding from sidewalls of the test sockets. Retained devices may be oriented such that contact arms may traverse horizontally to access the devices to, for example, provide desired testing environments. Devices may be retained by forces applied by the retention members to the retained devices in response to displacement, such as compression or deformation, of the retention members caused by the retained devices. Retention of the devices may be achieved without the need for additional fasteners, claims, or adjustment.

Abstract: Embodiments of the system and methods disclosed herein reduce the amount of handling necessary to organize the IC packages and thus may be utilized to increase the throughput of a test handler. To organize the IC packages, the IC packages may be initially placed on a first IC tray by the test handler. All of the IC packages are tested from the first IC tray so as to generate operational state data items for the IC packages. After all of the IC packages on the first IC tray are tested, the IC packages are sorted based on the operational state data items. In this manner, the operational state data items of the IC packages are known before sorting and thus not every IC package needs to be picked and placed in order to organize the IC packages.

Abstract: According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode.

Abstract: The resistive probing tip system has one or more carriers and one or more electrical contact assemblies. Each carrier has opposing surfaces with a plurality of resistors engaging the carrier. Each of the plurality of resistors has opposing electrical contacts that are exposed at respective opposing surfaces of the carrier. Each electrical contact assembly has opposing surfaces with electrical contacts exposed at the opposing surfaces with each electrical contact exposed on one surface coupled to a corresponding electrical contact on the other opposing surface. The carrier(s) and the electrical contact assembly(s) selectively mate to and mate from one another with the electrical contacts exposed at the opposing surfaces the carrier(s) and the electrical contact assembly(s) contacting one another. The carrier(s) and/or the electrical contact assembly(s) may be selectively secured to either of a circuit board or a probe head.

Abstract: To provide an IC device testing socket, capable of improving signal transmission efficiency during testing an IC device, without deteriorating the replacement workability of contact pins. A substrate 2 has dielectric layers 22-25 embedded in a base material 21 constituted by dielectric material such as glass epoxy. Each dielectric layer has a conductive layer, such as copper, formed on both sides thereof. Each of contact pins 3 extends generally perpendicular to surfaces 26 and 27 of substrate 2, and penetrates substrate 2. A through hole 28, into which each contact pin may be pressed, is formed in base material 21 of substrate 2, each high-dielectric layer and conductive layer. A conductive material 281, such as copper, is formed on an inner surface of each through hole 28.

Abstract: An electrical test contact electrically connects a test terminal of an Integrated Circuit (IC) test assembly with an IC terminal of an IC device in an electrical interconnect assembly. The test contact is formed of electrically conductive material and includes a head portion and a foot portion. The head portion includes a first electrical contacting portion for electrically engaging an IC terminal of an IC device during use, and the foot portion includes a second electrical contacting portion for electrically engaging a test terminal of a test assembly during use. The head portion includes a head receiving portion that receives a first resiliently biasing member to retain the first resiliently biasing member in contact with the test contact. The first resiliently biasing member biases the first electrical contacting portion against the IC terminal of the IC device during use. An electrical interconnect assembly having multiple test contacts is also disclosed.

Abstract: A test carrier which can suppress the occurrence of contact defects while securing positional precision of the terminals is provided. A test carrier 10 comprises: a base film 40 which has one main surface which has bumps which contact electrodes 91 of the die 90; and a cover film 70 which is laid over the base film 40, the die 90 is held between the base film 40 and the cover film 70, the base film 40 has: a first region 40a which has a first thickness t1; and a second region 40b which has a second thickness t2 which is thinner than the first thickness t1, and the second region 40b faces at least a part of the edge 92 of the die 90.

Abstract: A coaxial socket useful in association with an integrated circuit (IC) device tester and having a conducting pin surrounded by an insulating layer and embedded in a conducting base. This coaxial pin configuration allows for good thermal conductivity and better electrical signal transmission specially for testing high-speed integrated circuits.

Abstract: The present invention provides a test socket adaptable for testing different Integrated Circuit (IC) pad size during an IC testing. The test socket comprising a molded socket having an inner space and a plurality of through-apertures disposed on its surface; and a plurality of contact elements disposed within the inner space of the molded socket, each contact element has a pin contact edge and a pin-end; wherein each pin contact edge extends through the through-apertures of the molded socket; wherein each pin contact edge provides a linear surface area for contact with the DUT's lead; and wherein each pin contact edge provides a large contact area for various DUT's lead size.

Abstract: A structure and method for providing a contact pin between a device under test (DUT) and a load board which provides upper and lower contact point which are axial aligned is disclosed. The pin has an upper (30) and lower (32) section and a hinge in between which allow flex of both upper and lower contact (24/26) which, but the axial alignment can provide a direct replacement for POGO pins but with greater reliability. It also includes a structure and method for removing upper pins 230 by use of a modified hinge 244a. In an alternate embodiment, the lower section includes a leg extension 320 and a sliding contact land 360 which slides against an aperture in the housing. A spacer 342 provides space for decoupling components on the load board. The hinge may include a truncated cylinder 40b which is configured to permit remove of the upper pin without removal of the lower.

Abstract: A test coupler for supplying a device under test with test signals contains a first coaxial connector, a waveguide port, and a first strip conductor. Test signals of a lower frequency range are supplied to the first coaxial connector. Test signals of an upper frequency range are supplied to the waveguide port. The test coupler guides the test signals on the first strip conductor to the device under test.

Abstract: A system for analyzing electronic devices includes an input station, a transport apparatus, an electric machine interface station, an electric machine interface, a support structure and first and second thermal components. The input station receives a plurality of electronic devices and the transport apparatus transports each of the electronic devices from the input station to the electric machine interface station. The electric machine interface engages the electronic device when the electronic device is at the electric machine interface station, and is disengageable from the electronic device for the electronic device to be transportable by the transport apparatus away from the electric machine interface station. The first and second thermal components are located on opposing sides of the electronic device when the electronic device is at the electric machine interface station to simultaneously transfer heat to or from the electronic device.

Abstract: An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals.

Abstract: A method is disclosed for the measurement of a power device in a prober, which serves the examination and testing of such components. In the process, a power device is held by a chuck, and at least one electric probe is held by a probe holder, and optionally, the power device or the probe is positioned each relative to the other using a positioning device with an electrical drive, and contacts the power device. At the same time, an electrical connection remains between the probe to a signal unit with which a power signal is sent out or received, is blocked and only unblocked when it is determined that the contact between probe 26 and contact area is established.

Abstract: An automatable management system for testing one or more electronic control modules (ECMs), in one or more machines, is disclosed. The one or more ECMs are switchably connected to a testing unit (TU). The system includes at least one ECM connector, connectable to the one or more ECMs. The at least one ECM connector is one of a male connector or a female connector. Similarly, the system includes at least one TU connector connectable with the TU. Further, at least one actuator is operably connectable to at least one of the at least one ECM connector and the at least one TU connector. The actuator is configured to facilitate an electrical connection between the ECM and the testing unit in response to a relay signal generated by the testing unit.