Abstract: For testing a high density BGA package, a central pressure block is designed to press against the chip of the package during test in a test socket. High density socket probe causes high pressure against the package, especially the area under the chip. With the central pressure block of the present invention, the high density BGA package is prevented from deformation because the central pressure block pressing downward against the chip, which balances the pressure coming upward from the high density socket probes under the circuit board in the area under the chip.

Abstract: A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads.

Abstract: A test socket for electrically connecting a device under test (DUT) to an electrical signal source comprises a plurality of pogo pins spaced apart from each other, a stabilizing plate supporting the plurality of pogo pins, a plurality of conductive lines passing through the stabilizing plate and configured to electrically connect the electrical signal source to the pogo pins, and at least one inner stabilizer disposed in the stabilizing plate between the conductive lines and configured to apply an elastic force toward the DUT where the DUT is brought into contact with the pogo pins.

Abstract: An example system for testing electronic assemblies (EAs) may include carriers for holding EAs and slots for testing at least some of the EAs in parallel. Each slot may be configured to receive a corresponding carrier containing an EA and to test the EA. An example carrier in the system may include a first part and a second part. At least one of the first part and the second part include a first structure, and the first structure is movable to enable electrical connection between an EA and an electrical connector.

Abstract: [Problem] A test carrier able to secure a high air-tightness is provided. [Solution] A test carrier 10 comprises a cover member 50A and a base member 20A which are bonded together while sandwiching a die 90 between them. ultraviolet rays can pass through the cover member 50A.

Abstract: A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral slideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed.

Abstract: A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage.

Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

Abstract: A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

Abstract: A probe card structure adaptable to different test apparatuses of different specifications includes a probe card adapted to a first specification, a reinforcement member adapted to a second specification and a specification conversion interface unit disposed between the probe card and the reinforcement member. The probe card without the specification conversion interface unit can be directly mounted on a test apparatus of the first specification by means of a reinforcement member of the first specification to carry out the test process. Alternatively, the specification conversion interface unit can be combined with the probe card to convert the probe card from the first specification to the second specification. Accordingly, the probe card of the second specification can be mounted on a test apparatus of the second specification by means of the reinforcement member of the second specification to carry out the test process.

Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.

Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.

Abstract: A high voltage connector assembly includes a plurality of pin assemblies, each of the plurality of pin assemblies having a first end and a second end. The first end of each of the plurality of pin assemblies is configured to releasably electrically engage a load board. A plurality of pin pads, wherein the second end of each of the plurality of pin assemblies is configured to electrically engage a pin pad included within the plurality of pin pads. A plurality of connector pads are electrically coupled to the plurality of pin pads, wherein each of the plurality of connector pads is configured to be electrically coupled to a wire-based conductor included within a plurality of wire-based conductors. A potting compound is configured to encapsulate the plurality of connector pads.

Abstract: An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment.

Abstract: A test socket system has a housing with a screw that extends through central openings in the housing and a pusher block. Positioned below the pusher block is an integrated circuit and positioned below the integrated circuit is a contact set. The contact set is slidably received within slots on the inner surface of side walls of the housing. Positioned below the contact set is a PC adapter which is connected to a motherboard. The PC adapter has holes that receive dowels that extend downwardly from the bottom edge of the side walls of the housing. This system allows for easy and quick attachment of integrated circuits to a motherboard for testing purposes.

Abstract: A method and apparatus for testing a digital device. An apparatus for facilitating testing a digital device comprises a flat-top socket and a flat-top carrier board. The flat-top socket has a recess for accepting a carrier board, the recess having electrical contacts disposed in a pattern matching a pattern on a digital device. The flat-top carrier board also has a pattern of electrical contacts that match those on a digital device. A further embodiment provides an apparatus for facilitating testing of a digital device. The apparatus includes a digital device electrically and mechanically attached to a flip-chip carrier and also includes a flip-chip socket having an interface for connecting with the flip-chip carrier and an existing socket.

Abstract: Provided is a semiconductor device testing apparatus including a first socket configured to load a package, on which a semiconductor device to be tested may be mounted, and a second socket coupled to the first socket. The first socket may include an upper part including a hole configured to accommodate the package and a terminal pad provided at both side edges of the hole to hold input and output terminals of the package, and a lower part including a heating room, in which a heater and a temperature sensing part may be provided, the heater being configured to heat the semiconductor device and the temperature sensing part being configured to measure temperature of the semiconductor device. The second socket may include a probe card with a pattern that may be configured to receive test signals from an external power source.

Abstract: A method and apparatus for testing a package-on-package digital device is provided. The method includes the steps of: affixing a top device onto a wing board; affixing a bottom device onto the wing board; connecting the top side solderballs of the bottom package to the bond fingers of the wing board. The wing board is then mounted onto a flat top socket. Once the mounting has been completed, the testing begins, and may use a solid immersion lens or optical diagnostic tool. The configuration of the flat top socket and wing board allows the optical diagnostic tool full access to the bottom device for the testing process and failure analysis.

Abstract: A test device includes a circuit board with a connector, a test socket, a contact arm, and a number of signal lines. A first end of the contact arm is rotatably mounted on the circuit board and electrically connected to the test socket. A first end of the signal line is electrically connected to the connector. A second end of the signal line is fixed on the circuit board. The contact arm can be rotated to make a second end of the contact arm contact the second end of one of the signal lines.

Abstract: The inspection of semiconductors or like substrates by the present mechanism minimizes deflection in the checkplate and probe card. An inspection device including a housing, a toggle assembly within the housing, an objective lens assembly attached within the toggle assembly including an objective coupled within an objective focus, wherein the objective focus is deflectable along an optics axis, and a cam assembly including a rotary cam and a window carrier, wherein the window carrier is moveable along the optics axis with rotation of the rotary cam, wherein the cam assembly is coupled to the toggle assembly with the objective and window are aligned along the optics axis.

Abstract: A terminal end for a flat test probe having tapered cam surfaces providing a lead-in angle on the tail of the terminal end which extend to a sharp rear angle to engage detents or projections within a receptacle. The tapered cam surfaces and shape rear angles allow the probe to be inserted into the receptacle with minimal force to retain the flat test probe within the receptacle.

Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: A method and apparatus for a localized printed circuit board layer extender (LLX) is provided. The apparatus relieves layer routing congestion in and around high pin count integrated circuits. The method begins when a localized layer extender is provided that is compatible with the bottom-side pin-field of a device under test (DUT). The LLX is affixed to the bottom-side pin-field of the DUT. Test signals are then routed through the LLX as part of a test procedure. The apparatus includes: a LLX that substantially matches the pin-field of a bottom side of a DUT; a LLX base; and a LLX debug interface.

Abstract: Provided is a test structure for wafer acceptance test (WAT). The test structure includes a row of a plurality of first pads electrically connecting to each other, a second pad, a third pad, a first peripheral metal line, and a second peripheral metal line. The second pad is disposed in the vicinity of a first end of the row, wherein the second pad is electrically disconnected to the first pads. The third pad is disposed in the vicinity of a second end of the row, wherein the third pad is electrically disconnected to the first pads. The first peripheral metal line is disposed at a first side of the row and electrically connected to the second pad. The second peripheral metal line is disposed at a second side of the row and electrically connected to the third pad.

Abstract: Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.

Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

Abstract: The electronic device mounting apparatus 1 comprises: a first camera 123 for imaging a flexible board 74 of a base member 70 of a test carrier 60 to generate a first image information; an image processing apparatus 40 for detecting a position of an alignment mark 79 of the flexible board 74 from the first image information and calculating a print start position 782 of the first interconnect patterns 78 on the flexible board 74 on the basis of the position of the alignment mark 79; a printing head 122 for forming a first interconnect pattern 78 on the flexible board 74 from the print start position 782; and a second conveyor arm 21 for mounting a die 90 on the flexible board 74 on which the first interconnect pattern 78 is formed.

Abstract: Testing assembly for testing a singulated semiconductor die comprising a power component. The assembly comprises an current input connectable to a current source, for providing a current greater than 50 Amps to the power component; a signal output connectable to a signal analyzer, for receiving signals representing a sensed parameter of the power component sensed when the current is provided; a first contact unit, adapted to support the semiconductor die; a second contact unit, movably mounted relative to the first contact unit; and at least an electrically-conductive resilient sheath, adapted to be sandwiched between the semiconductor die and the second contact unit when the second contact unit is brought toward the semiconductor die during a test, the sheath forming part of an electrical path from the current input through at least a part of the die when thus sandwiched.

Abstract: An IC socket is pneumatically actuated and has an integrated heat sink. Thermally conductive elements of the heat sink extend through an opening of a pneumatically actuated element shaped as a closed curve of finite width so that heat radiating from the thermally conductive elements may dissipate through a top opening of the IC socket. Downward force exerted by the pneumatically actuated element is transferred through a gimbaled multi-plate and spring arrangement to provide even pressure on the die and substrate of an IC device being held in place by the IC socket. A spring-loaded ground tab on the bottom of the IC socket simplifies grounding of the IC socket to avoid damaging the held IC device by static discharge.

Abstract: A probe card having a configurable structure for exchanging/swapping electronic components for impedance matching and an impedance method therefore are provided. In the probe card, an applied force is exerted on the electronic component so as to make the electronic component electrically connected with at least one conductive contact pad of a supporting unit. The supporting unit is a circuit board or a space transformer. In order to facilitate the exchange or swap of the electronic component, the applied force can be removed. The probe card includes a pressing plate which can be moved between a pressing position and a non-pressing position. The pressing plate has a pressing surface which is contacted with the top end of the electronic component while the pressing plate is in the pressing position. Therefore, the applied force can be generated or removed by changing the positioning of the pressing plate.

Abstract: A test socket has a housing with an inlet configured to receive a substrate. A plurality of terminals are coupled to the housing, and a plurality of sliding pins are coupled to the terminals. The pins are configured to make contact with respective pads or terminals of the substrate to be tested. The pins have different lengths or positions to send and receive test signals.

Abstract: Disclosed is an inspection apparatus for a semiconductor device, which is to inspect an electric characteristic of an inspective object having a plurality of electric inspective contact points. The inspection apparatus includes a socket assembly which includes a plurality of probe pins retractable in a longitudinal direction, a probe pin supporter supporting the probe pins in parallel with each other, and a socket board including a plurality of fixed contact points a first end portion of the probe pins, and an inspective object carrier which includes an inspective object accommodating portion accommodating the inspective object so that the inspective contact points face toward a second end portion of the probe pins, and a floor member interposed between the inspective object and the probe pin supporter and including probe holes penetrated corresponding to the inspective contact points and passing the second end portion of the probe pin therethrough.

Abstract: A device for testing electronic component devices on a carrier or a substrate, having a positioning and holding device for the earner or the substrate, a test head and a test socket connected thereto, with which multiple simultaneous electronic component devices on the carrier or the substrate are contactable. At least one additional test socket is connected to the test head.

Abstract: Spring assemblies and a test socket using the spring assemblies. The spring assemblies are used in a test socket electrically connecting lead terminals of a semiconductor chip to test terminals of a test device by contacting the lead terminals and the test terminals, and include: first springs in which a first steel wire having elasticity and conductivity is coiled in a spiral in one direction; and second springs in which a second steel wire having elasticity and conductivity is coiled in a spiral in an opposite direction to the direction in which the first springs are coiled, which have outer diameters narrower than inner diameters of the first springs, and are inserted into the first springs. Accordingly, electric resistances and inductances of two spring assemblies coiled in a spiral are reduced to improve electricity transmission characteristic. A height of a test socket is easily adjusted using spring assemblies having desired lengths.

Abstract: A test system for testing a device under test (DUT) is provided. The test system may include a DUT receiving structure configured to receive the DUT during testing and a DUT retention structure that is configured to press the DUT against the DUT receiving structure so that DUT cannot inadvertently shift around during testing. The DUT retention structure may include a pressure sensor operable to detect an amount of pressure that is applied to the DUT. The DUT retention structure may be raised and lowered vertically using a manually-controlled or a computer-controlled positioner. The positioner may be adjusted using a coarse tuning knob and a fine tuning knob. The positioner may be calibrated such that the DUT retention structure applies a sufficient amount of pressure on the DUT during production testing.

Abstract: A test system having a manipulation device and a test unit. The manipulation device has a receiving unit with a socket that accommodates a packaged integrated circuit, which has a top side and a bottom side. A plurality of electrical terminal contacts are formed on the bottom side. In a first state, the manipulation device provides the integrated circuit to the test unit, and during the first state the test unit is disposed above the top side of the integrated circuit and forms a connection with the manipulation device, and the test unit carries out a function test on the integrated circuit. A sensor device is formed on the top side, and the top side of the integrated circuit is oriented in a direction of the test unit and the electrical terminal contacts are electrically connected to the receiving unit of the manipulation device.

Abstract: The present document relates to chip sockets which for testing integrated circuit chips. A chip socket carries an integrated circuit chip comprising a plate for mounting onto a front side of a PCB, a plurality of electrical PCB connectors in a first area on a backside of the plate, wherein the plurality of electrical PCB connectors is adapted for electrically connecting the chip socket to a corresponding plurality of connectors on the PCB and a corresponding plurality of chip connectors on a front side of the plate, wherein the plurality of chip connectors is electrically connected to the plurality of electrical PCB connectors respectively; wherein the plurality of chip connectors connect the chip socket to a corresponding plurality of connectors of the integrated circuit chip, wherein the plate comprises a recess at its backside.

Abstract: A test device is provided for testing a bottom chip of a package-on-package (PoP) stacked-chip. An upper surface of the bottom chip has a plurality of soldering points for electrically connecting a plurality of corresponding soldering points of a top chip of the PoP stacked-chip. The test device includes a test head and a plurality of test contacts. The test head has the top chip installed inside. The plurality of test contacts is installed on a lower surface of the test head and electrically connected to the plurality of corresponding soldering points of the top chip inside the test head. When the lower surface of the test head contacts the upper surface of the bottom chip, the plurality of test contacts is electrically connected to the plurality of soldering points for testing the bottom chip.

Abstract: The test socket includes: an elastic conductive sheet including a conductive portion and an insulating supporting portion; a sheet type connector including an electrode portion that is disposed on the conductive portion and is formed of a metal, and a sheet member that supports the electrode portion, wherein the sheet member comprises a cut portion formed by cutting at least a portion of the sheet member between adjacent electrode portions; and an electrode supporting portion including an upper supporting portion that contacts an upper edge of the electrode portion to support the electrode portion and exposes an upper center portion of the electrode portion to be open and an electrode supporting portion including a connection supporting portion that connects the upper supporting portion and the insulating supporting portion.

Abstract: A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.

Abstract: A component transport apparatus includes: a transport hand including a plurality of index units each one of which is capable of holding a component; a movable body that moves the transport hand; and a plurality of functional stations on which the components are mounted. The index units function to mount the components on the functional stations. The functional stations are spaced apart at intervals along a movement direction of the transport hand. The index units are spaced apart at intervals equal to the intervals at which the functional stations are spaced apart along the movement direction of the transport hand.

Abstract: An opener for a test handler is provided. Even when holding members of inserts of a carrier board are manipulated to release semiconductor devices that have been in a held state, a predetermined distance can remain between an upper surface of the opening plate and a lower surface of the insert, thus preventing the inserts from becoming defective.

Abstract: A semiconductor testing apparatus is provided wherein components that must be arranged most closely are arranged most closely to terminals of a test object. The present apparatus is semiconductor testing apparatus comprising a printed circuit board, and a test socket mounted on an upper surface of the printed circuit board and forming a signal connection path between a test object and the printing circuit board, wherein a chip shaped capacitor is mounted on the upper surface of the printed circuit board, an interference avoidance space avoiding contact with the capacitor is formed in the test socket, the interference avoidance space being formed at a location facing the location where the capacitor is mounted, and the capacitor and the test socket being non-contacted from each other by the interference avoidance space.

Abstract: Transferring electronic probe assemblies to space transformers. In accordance with a first method embodiment, a plurality of probes is formed in a sacrificial material on a sacrificial substrate via microelectromechanical systems (MEMS) processes. The tips of the plurality of probes are formed adjacent to the sacrificial substrate and the remaining structure of the plurality of probes extends outward from the sacrificial substrate. The sacrificial material comprising the plurality of probes is attached to a space transformer. The space transformer includes a plurality of contacts on one surface for contacting the plurality of probes at a probe pitch and a corresponding second plurality of contacts on another surface at a second pitch, larger than the probe pitch, wherein each of the second plurality of contacts is electrically coupled to a corresponding one of the plurality of probes. The sacrificial substrate is removed, and the sacrificial material is removed, leaving the plurality of probes intact.

Abstract: An opener and a buffer table for a test handler are disclosed. The opener includes an opening plate, a plurality of pin blocks forming pairs, and at least one or more interval retaining apparatus for retaining an interval between the pin blocks forming a pair. Each of the pin blocks is movably coupled to the opening plate, and includes opening pins for releasing a holding state of a holding apparatus that holds semiconductor devices in a carrier board. Although semiconductor devices to be tested are altered in size and a carrier board loading with the semiconductor devices is thus replaced, the opener does not need to be replaced, thereby reducing the replacement cost and the waste of resources.

Abstract: A socket which enables occurrence of contact defects to be suppressed is provided. A socket 11 to which a test carrier 20, which has: a base film 32 on which bumps 324 are formed for contact with electrode pads 51 of a die 50; and external terminals 312 which are electrically connected to the bumps 324, is electrically connected comprises: contactors 125 which contact external terminals 312; and an elastic member 131 which pushes against bump-forming portions 32a and bump-surrounding portions 32b on the base film 32. The elastic member 131 has: a first elastic layer 132; and a second elastic layer 133 which is more flexible than the first elastic layer 132, and a second elastic layer 133 is laid over the first elastic layer 132 and contacts the base film 32.

Abstract: An exemplary die carrier is disclosed. In some embodiments, the die carrier can hold a plurality of singulated dies while the dies are tested. The dies can be arranged on the carrier in a pattern that facilities testing the dies. The carrier can be configured to allow interchangeable interfaces to different testers to be attached to and detached from the carrier. The carrier can also be configured as a shipping container for the dies.

Abstract: A test system may be provided in which devices under test are loaded into test trays and tested at a plurality of test stations. To test a device under test at a given test station, the test tray may be installed into a test fixture at the test station. Test equipment at each test station may communicate with the device under test via the test fixture and the test tray. Each test tray may have a spring-loaded corner portion that may be used to secure the device under test to the test tray. The test tray may have contacts that mate with corresponding contacts at each test fixture and may have a built in cable that connects to the device under test. The test fixture may have a detector that can detect whether or not a test tray is present on the test fixture.

Abstract: A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning potions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier.