Abstract: According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode.

Abstract: A system for analyzing electronic devices includes a first cab, an input station, a transport apparatus, an electric machine interface station, and an electric machine interface. The first cab includes a holder having formations for removably receiving a first subset of electronic devices and a communications interface. The input station receives the first cab and the transport apparatus transports the first cab with the first subset of electronic devices from the input station to the electric machine interface station. The electric machine interface is positioned to engage communicatively with the communications interface of the first cab when the first cab is at the electric machine interface station, and is disengageable from the communications interface of the first cab for the first cab to be transportable by the transport apparatus away from the electric machine interface station. Heat conducts to or from the electronic devices while they are being analyzed.

Abstract: In one embodiment, a device interface board is provided which includes a printed circuit board with a DUT interface structure, such as socket, associated with a DUT side of the printed circuit board. A high frequency connector and electronic component are mounted in a cavity formed in a back side of the printed circuit board. A signal via through the printed circuit board couples the high frequency connector and electronic component with the DUT interface structure. An encapsulating structure may be provided, which covers the cavity while allowing a cable to connect to the high frequency connector.

Abstract: In one embodiment, an interface includes a plurality of test electronics to DUT interfaces. Each test electronics to DUT interface has at least one test electronics interface, at least one DUT interface, and an electrical coupling between the at least one test electronics interface and the at least one DUT interface. First and second subsets of the DUT interfaces are respectively positioned along the perimeters of first and second concentric shapes.

Abstract: A test carrier which can suppress the occurrence of contact defects and secure positional precision of the terminals is provided. The test carrier 10 comprises: a film-shaped base film 40 which has a plurality of bumps 43 which respectively contact electrode pads 91 of a die 90; and a cover film 70 which is laid over the base film 40 and which covers the die 90, and the plurality of bumps 43 include first bumps 43a and second bumps 43b which are relatively higher than the first bumps 43a.

Abstract: A test carrier which can suppress the occurrence of contact defects and secure positional precision of the terminals is provided. The test carrier 10 comprises: a base film 40 which has bumps 43 which contact the electrode pads 91 of the die 90; a cover film 70 which is laid over the base film 40 and which covers the die 90; and a spacer 45 which is interposed between the base film 40 and the cover film 70 and which is arranged around the die 90.

Abstract: A test carrier which enables a reduction of cost to be achieved. The test carrier 10 comprises: a base film 40 which holds a die 90; and a film-shaped cover film 70 which is laid over the base film 40 and covers the die 90, the cover film 70 has a self-adhesiveness and is more flexible than the base film 40.

Abstract: A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads.

Abstract: An electronic device test fixture deploys a plurality of contact elements in a dielectric housing. The plumb arrangement of contact elements each include an armature or transversal configured to first depress and then slide laterally when urged downward by the external contacts of a device under test. The rotary movement of the transversal is optimized via the configuration of a surrounding forked regulator such that surface oxide deposition on the external device under test terminal is disrupted to reliably minimize contact resistance without damaging or unduly stressing the electrical junction of the device under test.

Abstract: A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material.

Abstract: A holder for measurement configured to be capable of holding an object of measurement, the object of measurement included a package including a plurality of semiconductor chips and a conduction portion exposed to the outside through a lateral surface of the package, including: a support board including a through-hole; a fixation portion configured to fix the object of measurement to the support board; and a probe portion movable in at least one axial direction with respect to the support board, and configured to be capable of coming into contact with the conduction portion.

Abstract: A test apparatus for testing semiconductor integrated circuits includes a test head, a probe card holder for detachably holding a probe card that probes a semiconductor device, a heater for heating the probe card, and a heater holder that holds the heater in direct contact with the probe card when the probe card is held by the probe card holder. The test apparatus heats the probe card efficiently and thereby reduces test time and cost.

Abstract: A test socket having a lid and a base with a cavity for receipt of an integrated circuit and removable test probe inserts having test probes positioned around a perimeter of the cavity.

Abstract: A system for testing with an automated test equipment (ATE) includes a tester having at least one test resource, a tandem handler, and a mux relay that switchably connects the test resource, via parallel connections, to either one of dual sockets at each instant of testing. The handler has first and second manipulator arms. Each arm operates as to a particular one of the respective sockets, to retrieve a next device to be tested and position the device in the socket (while testing is performed on a device in the other socket), to disposition the device from the socket once testing is completed as to the device in the socket, and thereafter repeat until all staged devices for testing have been tested (or an interruption of testing otherwise occurs). The mux relay switches between sockets in response to the tandem handler acting as a master and the tester as slave.

Abstract: In a semiconductor test apparatus, a first device is tested as a device under test in a state where the first device provided with a transmitter transmitting a signal and a second device provided with a receiver receiving the signal transmitted by the transmitter, are connected together. The transmitter includes an equalizer circuit that shapes the waveform of the differential signal to be transmitted. The receiver includes a latch circuit that latches data corresponding to the differential signal thus received with the use of a clock, the timing of which is variable. A control unit varies, in a matrix, a parameter of the equalizer circuit and an edge timing of the clock CLK supplied to the latch circuit.

Abstract: Methods and systems for testing an integrated circuit during an assembly process are described. The integrated circuit is received from inventory. The integrated circuit is placed in a socket on a first circuit board for system-level testing. The system-level testing is performed prior to placement and permanent attachment of the integrated circuit onto a second circuit board. Provided the integrated circuit passes the system-level testing, the placement and permanent attachment of the integrated circuit to the second circuit board is the next step following the system-level testing in the assembly process.

Abstract: A device tester for an IC device under test (DUT), the DUT having a substrate and an attached die. The device tester includes a thermal control unit and a test socket assembly which conforms to the DUT's profile. The thermal control unit includes a pedestal assembly, a heater having a fuse coupled to a heating element, a substrate pusher, and a force distributor for distributing force between the pedestal assembly and the substrate pusher. The test socket assembly includes a socket insert that supports and also conforms to the DUT's profile.

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract: An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment.

Abstract: A probe card and method are provided for testing magnetic sensors at the wafer level. The probe card has one or more probe tips having a first pair of solenoid coils in parallel configuration on first opposed sides of each probe tip to supply a magnetic field in a first (X) direction, a second pair of solenoid coils in parallel configuration on second opposed sides of each probe tip to supply a magnetic field in a second (Y) direction orthogonal to the first direction, and an optional third solenoid coil enclosing or inscribing the first and second pair to supply a magnetic field in a third direction (Z) orthogonal to both the first and second directions. The first pair, second pair, and third coil are each symmetrical with a point on the probe tip array, the point being aligned with and positioned close to a magnetic sensor during test.

Abstract: An apparatus for supporting a device, comprising a base assembly, a plurality of carrier columns extending from the base unit, and a plurality of vertical support plates, each vertically movable along a respective carrier column and including a pivotal device mounting bracket. A pneumatic unit including a piston rod is associated with each vertical support plate such that vertical motion of the piston rod controls vertical motion of the respective vertical support plate.

Abstract: A test socket includes a test base and at least one electrical connection module. The at least one electrical connection module is detachably mounted in the test base and each one of the at least one electrical connection module has a frame and an electrically conducting element. The frame has a receiving hole for receiving and testing an IC. The electrically conducting element is detachably mounted on a bottom of the frame. After long time of use, the ineffective electrical connection module or electrically conducting element thereof can be rapidly and easily replaced with a new or an effective one by directly detaching the electrical connection module from the test base. Therefore, idle time or dead time of test apparatuses is shortened and test efficiency is enhanced.

Abstract: A test section unit provided to a test head body includes a plurality of sockets to be attached with electronic devices to be tested and a performance board as a main substrate. All of the sockets are provided with the performance board without an intervening a socket board.

Abstract: A serial attached small computer system interface (SCSI) (SAS) interface output signal detecting apparatus includes an SAS female connector, an SAS male connector, and two subminiature version A (SMA) connectors. Each of the SAS female and male connectors includes first and second groups of data pins and a group of power pins. The power pins of the SAS female connector are connected to the power pins of the SAS male connector. The SMA connectors are connected to two data output pins of the second or first group of data pins of the SAS female connector in response to the first group of data pins of the SAS female connector being connected to the first group of data pins of the SAS male connector or the second group of data pins of the SAS female connector being connected to the second group of data pins of the SAS male connector.

Abstract: Systems, methods, devices, and computer program products are described for allowing optical backside failure analysis of a wire-bonded semiconductor device concurrent with electrical testing of the device. For example, a semiconductor device is prepared and mounted in the optical testing subsystem, such that a circuit region of the device is exposed to an optical testing environment, and an analog to the original array of the device is presented via the optical testing subsystem as a derived array. The electrical testing subsystem converts the derived array to a test array, and presents the test array in a way that is physically and electrically compatible with a test socket of an electrical testing environment. By coupling the electrical testing subsystem with the optical testing subsystem, a pin-to-pin coupling may be effectuated between the test array of the test socket and bonding locations on the device corresponding to the device's original array.

Abstract: A connecting device for connecting pins of a DIP chip to a test device comprises two each of half frames, columns of testing pins, connecting screws, fixing screws, and four holding plates. The two columns of testing pins are arranged respectively on the two half frames parallel to the lengthways direction of the half frame. The distance between two adjacent testing pins in the same column is equal to that between the two adjacent pins in the same column of the DIP chip. The two connecting screws screw into the half frames perpendicular to the lengthways direction of the half frame. Two of the holding plates extend down from each of the half frames and are aligned with short sides of the corresponding half frame. The fixing screws fix the two holding plates on the same half frame along a direction parallel to the lengthways direction of the half frame.

Abstract: A test board can be inserted to a test head and removed from the test head while the connecting section for mounting thereon devices under test is mounted on the upper portion of the test head. A test head for retaining therein at least one test board for testing devices under test, includes: a casing provided with, on one side surface thereof, an opening through which the at least one test board is inserted and removed, the casing retaining therein the at least one test board with an upper side thereof oriented towards an upper surface of the casing; and a mounting member that guides a lower side of the at least one test board through the opening to a pre-set position, imposes an upward force to the lower side of the at least one test board, thereby mounting the at least one test board to the casing.

Abstract: A capacitor test fixture for positioning capacitors under test includes a main body, a clamping section, an operating section, and a cover. The main body defines an opening, a plurality of receiving slots at the bottom of the opening to receive the capacitors, some positioning slots located at opposite sides of the opening, and a sliding slot. The clamping section includes a first hook, and the operating section includes a second hook corresponding to the first hook. The cover locates and fixes the clamping section and the operating section to the main body. The operating section functions when the second hook holds back the first hook, the capacitors under test are received within the receiving slots, and when the second hook releases the first hook, the clamping section secures and makes contact with the capacitors for testing.

Abstract: Diagnostic tools for testing integrated circuit (IC) devices, and a method of making the same. The first diagnostic tool includes a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between proximal ends of contact members in the socket and contact pads on a printed circuit board (PCB). A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location external to the first interface. The electrical devices are electrically coupled to the conductive traces and programmed to provide one or more of continuity testing at the first interface or functionality of the IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a surrogate IC device.

Abstract: A handler tray may include a tray body and a socket. The tray body may be configured to receive an object. The tray body with the object may be transferred to a test board. The tray body may be selectively interposed between the object and the test board to supply a test current from the test board to external terminals of the object. The socket may be formed on the tray body. The socket may electrically make contact with the external terminals of the object. Thus, a pick-up robot and an insert may be unnecessary, so that a test system and method of testing the object may have an optimally available space.

Abstract: A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate. The first conductive trace is disposed on the conductive plug and on the substrate in the first area. The second conductive trace is disposed on the substrate in the second area. It is noted that the first conductive trace and the second conductive trace have the same material and the same shape. A measurement method of the above-mentioned test structure is also provided.

Abstract: According to an example embodiment, a contact cell includes a first element that is flexible and electrically conductive, and that is structured to have at least one bend along an entire length of the first element. The contact cell further includes a second element that is flexible and electrically conductive, and that is structured to have at least one bend along an entire length of the second element. The contact cell further includes a tie that is electrically non-conductive, and that is affixed to the first element and affixed to the second element such that the first element and second element are physically and electrically separated from each other.

Abstract: An electrically conductive contact element can include a first base and a second base with elongate, spaced apart leaves between the bases. A first end of each leaf can be coupled to the first base and an opposite second end of the leaf can be coupled to the second base. A body of the leaf between the first end and the second end can be sufficiently elongate to respond to a force through said contact element substantially parallel with the first axis and the second axis by first compressing axially while said force is less than a buckling force and then bending while said force is greater than the buckling force.

Abstract: An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket configured to electrically connect the test object to the test board; and a handler configured to transport the test object to the socket. The socket comprises a first connection unit configured to be electrically connected to the first connection terminals of the test object and a second connection unit configured to be electrically connected to the second connection terminals of the test object.

Abstract: Structures and techniques for restraining devices for testing. Test sockets may retain devices under test using one or more retention members protruding from sidewalls of the test sockets. Retained devices may be oriented such that contact arms may traverse horizontally to access the devices to, for example, provide desired testing environments. Devices may be retained by forces applied by the retention members to the retained devices in response to displacement, such as compression or deformation, of the retention members caused by the retained devices. Retention of the devices may be achieved without the need for additional fasteners, claims, or adjustment.

Abstract: An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals.

Abstract: A test tray for a test handler is disclosed that is loaded with semiconductor devices and then carries them along a predetermined circulation route. The test tray allows one fixing unit to fix a plurality of adjacent insert modules to the receiving spaces of the frame, thereby efficiently using the space of the frame and allowing a relatively large number of insert modules to be installed in the same area, in comparison to the conventional test tray.

Abstract: A test board is provided. The test board includes a test module configured to accommodate an integrated circuit (IC) device and first wirelessly enabled functional blocks located in the test module and configured to communicate with second wirelessly enabled functional blocks of the IC device.

Abstract: An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket configured to electrically connect the test object to the test board; and a handler configured to transport the test object to the socket. The socket comprises a first connection unit configured to be electrically connected to the first connection terminals of the test object and a second connection unit configured to be electrically connected to the second connection terminals of the test object.

Abstract: A socket for testing a semiconductor chip includes a base cover, a conductive sheet, upper plungers, a housing, lower plungers and a support plate. The base cover has a coupling opening in the central portion thereof, and the conductive sheet is fitted into the coupling opening of the base cover and includes conductive parts and an insulation part. The upper plungers are seated onto upper ends of the conductive parts and come into contact with corresponding terminals of the semiconductor chip. The housing has insert holes at positions corresponding to the upper plungers and fastens the upper plungers to the corresponding conductive parts. The lower plungers are provided under lower ends of the conductive parts and come into contact with corresponding terminals of a PCB to electrically connect the conductive parts to the PCB.

Abstract: The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure.

Abstract: To provide an IC device testing socket, capable of improving signal transmission efficiency during testing an IC device, without deteriorating the replacement workability of contact pins. A substrate 2 has dielectric layers 22-25 embedded in a base material 21 constituted by dielectric material such as glass epoxy. Each dielectric layer has a conductive layer, such as copper, formed on both sides thereof. Each of contact pins 3 extends generally perpendicular to surfaces 26 and 27 of substrate 2, and penetrates substrate 2. A through hole 28, into which each contact pin may be pressed, is formed in base material 21 of substrate 2, each high-dielectric layer and conductive layer. A conductive material 281, such as copper, is formed on an inner surface of each through hole 28.

Abstract: An improved efficiency system for testing electronic components in a motherboard/daughterboard assembly in which the daughterboard is mounted in spaced parallel relationship the to motherboard includes one or more device-under-test socket sub-assemblies having a test socket thereon for receiving a device-under-test and a connector component for disengagable connection to a complementary connector component on the daughterboard with the socket sub-assembly effecting interengagement of the complementary connector component on the daughterboard via an opening in the motherboard to allow ready access to the test socket for temporary installation, testing, and removal of a device-under-test.

Abstract: Embodiments of the system and methods disclosed herein reduce the amount of handling necessary to organize the IC packages and thus may be utilized to increase the throughput of a test handler. To organize the IC packages, the IC packages may be initially placed on a first IC tray by the test handler. All of the IC packages are tested from the first IC tray so as to generate operational state data items for the IC packages. After all of the IC packages on the first IC tray are tested, the IC packages are sorted based on the operational state data items. In this manner, the operational state data items of the IC packages are known before sorting and thus not every IC package needs to be picked and placed in order to organize the IC packages.

Abstract: A test socket for an integrated circuit device includes a base for receiving the circuit device and a frame movable linearly toward and away from the base. Springs bias the frame away from the base. Device holders are movable substantially linearly on the frame between a closed position where the device holders are in proximity to one another and an open position where the device holders are remote from one another. Cams move the device holders between the open and closed positions in response to movement of the frame toward and away from the base.

Abstract: A socket connector for electrically connecting a lead of a semiconductor device under test (DUT) with a tester includes a container having a chamber, a conductive end or plug that seals the chamber at one end, and a conductive membrane that seals the chamber at another end. A liquid conductive material fills the chamber. The conductive plug is arranged to be in electrical contact with the tester. The lead of the semiconductor DUT is in electrical contact with the conductive membrane and thus with the tester via the conductive membrane, the liquid conductive material and the conductive plug.

Abstract: A test board includes a socket, a mounting test circuit, and a relay. An analog core embedded application processor is installed into the socket. The mounting test circuit has a same configuration as an environment where the analog core embedded application processor is actually used. The relay disconnects the mounting test circuit from the socket in response to a first control signal when a vector test is performed on the analog core embedded application processor, and that connects the mounting test circuit to the socket in response to a second control signal when a mounting set test is performed on the analog core embedded application processor.

Abstract: An electronic component pressing device includes a first pressing member for pressing a predetermined first region of the electronic component to be tested; a second pressing member for pressing a predetermined second region other than the first region of the electronic component to be tested; a gimbal mechanism for adhering the first pressing member to the first region when the first pressing member presses the first region of the electronic component to be tested; first pressing load applying means for applying a pressing load on the gimbal mechanism; and second pressing load applying means for applying a pressing load on the second pressing member.

Abstract: A universal test socket includes a housing frame including a side wall, an inner protruding portion protruding inwardly from the side wall, and a through window formed at a center portion of the housing frame, wherein the through window is surrounded by the side wall, a pin plate assembly coupled to the housing frame and including a pin plate in which a plurality of test pins are arranged and a plurality of guide pins formed on periphery of the pin plate, and a package guide portion coupled to the housing frame and located above the pin plate assembly, a semiconductor package to be tested being mounted on the package guide portion. When the pin plate assembly is coupled to the housing frame, the positions of the test pins arranged in the housing frame are varied according to a rotation angle of the pin plate assembly with respect to the housing frame.

Abstract: An apparatus for testing radio frequency (RF) and/or mixed signal semiconductor devices and or modules is described. specifically described is how the distributed stimulus for RF automatic test applications, unified testhead for automatic test applications, reverse card backplane for automatic test applications, direct coaxial interface for automatic test applications, cable-free interface for automatic test applications, micromachine switch matrix for automatic test applications, device specific module high speed date for RF automatic test applications may be used within tester apparatus described herein or in other test applications. Additionally a high speed date communications test apparatus which may be used in a variety of device testers is described herein.