Abstract: An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance circuit in a feedback path for reducing a slew rate of a buffered output signal generated by the output buffer. In the decoupling configuration, the capacitance circuit electrically couples the capacitor between a power potential and a ground potential of the output buffer for increasing power noise immunity of the output buffer. The output buffer may have more than capacitance circuit, each of which is individually configurable into the slew rate configuration or the decoupling configuration.

Abstract: Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters.

Abstract: The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source. The output of the transmitting circuit delivers, when the transmitting circuit is in the activated state, voltages between one of the signal terminals and the reference terminal (ground). A receiving circuit delivers, when the receiving circuit is in the activated state, output signals of the receiving circuit determined each by the voltage between one of the signal terminals and the common terminal, to the destination. In the closed state, the common terminal switching circuit is, for the common terminal, equivalent to a voltage source delivering a constant voltage, connected in series with a passive two-terminal circuit element presenting a low impedance.

Abstract: A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up or pull down a predetermined node and compare a voltage of the predetermined node with a reference voltage to generate calibration codes, by using parallel resistor units that are turned on or off in response to the calibration codes. An output driver is configured to terminate a data output node to a pull-up or pull-down level to output data, by using the parallel resistor units. At least one of the parallel resistor units having at least two resistivities includes resistors with different resistivities connected to each other in parallel.

Abstract: A plurality of nodes are coupled via a serial data bus A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality of nodes and is defined as the bit master. One or more of the nodes transmits onto the bus dominant and recessive states at a first predetermined time after each transition. The transmitted states represent respective dominant and recessive bits of an attempted message. The plurality of nodes detect dominant and recessive states of the bus at a second predetermined time after each transition. Any of the one or more nodes that transmits a recessive bit at the first predetermined time and detects a dominant bit at the second predetermined time ceases transmission of bits onto the bus.

Abstract: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit(s) input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Abstract: An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Abstract: Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a predetermined clock and a clock control unit configured to selectively supply the clock to the calibration control unit according to an operation mode of a semiconductor device employing the calibration circuit.

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract: A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the internal circuit, a feedback line branched off from signal line in buffer transmitting data signal to an output stage circuit of the output buffer, and a delay test circuit connected to the feedback line.

Abstract: A bus switch for connecting and disconnecting a bus connection provided by a pair of buses includes a first switching element and a second switching element. The first switching element is coupled between an input terminal and an output terminal of a high-potential side bus of the pair of buses. The second switching element is coupled between an input terminal and an output terminal of a low-potential side bus of the pair of buses. The bus connection is connected when the first switching element and the second switching element are activated, and the bus connection is disconnected when the first switching element and the second switching element are deactivated.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract: Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.

Abstract: A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence detector element for detecting coincidence of an input signal to the delay element and an output of the delay element. The plurality of variable delay stages may comprise stacked inverter circuits or stacked NAND circuits.

Abstract: In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.

Abstract: In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

Abstract: A system reduces a received RF signal from EMI generated by a digital electronic system that includes a clock. In the present invention the clock frequency, that generates signals and strobes data out, is purposely changed or modulated, by, illustratively, driving the power node of the clock. The typical filter circuit between the clock power node and the power supply is used to advantage in that the filter impedance allows a buffer to more easily drive the clock power node since the low impedance of the power supply is isolated by the filter circuit. The changing of the clock frequency spreads the EMI RF harmonics over a spectrum so that any harmonics received by an RF receiver will be short lived and therefore of small magnitude.

Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Abstract: Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.

Abstract: Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.

Abstract: A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an external resistor. The calibration circuit also includes a code generation unit configured to generate a calibration code in response to a voltage of the calibration node and a reference voltage, a calibration resistor unit configured to drive the calibration node in response to the calibration code and turn-off when the code generation unit is disabled, and a precharge unit configured to precharge the precharge node to a predetermined voltage level when the code generation unit is disabled.

Abstract: The present invention provides an input/output device capable of bringing a per-unit input/output circuit into a simple configuration without impairing reliability even when logic levels opposite in polarity are outputted between input/output devices made conductive to the outside. The input/output device is equipped with one reference port Pk selected from a port group which inputs and outputs signals, target ports Pt selected from other than the reference port of the port group, and a conduction detector which detects that conduction is made between input/output terminals for the reference port Pk and the target ports Pt.

Abstract: In a logic circuit, a first switching device is connected between a first voltage and an output terminal through which an output signal is output. The switching device is selectively activated and deactivated based on an input signal. A second switching device is connected to a ground voltage and is selectively activated and deactivated based on the input signal. A control circuit outputs a control signal in response to the input signal. The control signal has a first voltage level during a first time period in which a state of the input signal changes, and has a second voltage level during a second time period in which a state of the input signal is constant. The second voltage level is lower than the first voltage level. A field relaxation circuit is connected between the terminal through which the output signal is output.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit being connected to a first node; and a transmission line circuit configured to be responsive to a control signal to connect the first node to a pin of a system employing the impedance adjusting circuit.

Abstract: A differential line compensation apparatus, semiconductor chip and system are disclosed.

Abstract: An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block.

Abstract: An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

Abstract: In one embodiment, an output driver buffer circuit for a logic device includes an output driver transistor adapted to adjust an output voltage of an output pad; a capacitor adapted to be connected to the transistor gate and further adapted when charged and connected to the gate to turn the transistor on; and a reference voltage source adapted to be connected to the transistor gate and further adapted when connected to the gate to maintain the transistor on. The reference voltage source is further adapted to be connected to the transistor gate after the capacitor has turned the transistor on and independent of the level of the output voltage of the output pad.

Abstract: A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.

Abstract: An interface circuit includes a driver circuit (12) made up of a combination of a plurality of transistors, a calibration circuit (14) for performing selection of on and off of one or more of the plurality of transistors for adjusting on-resistance thereof, and a terminating resistor (13) that is connected to an output side of the driver circuit (12). One or more of the transistors are turned on based on an output of the calibration circuit (14), so that a combination resistance value of the on-resistance and the terminating resistor matches characteristic impedance of the transmission line. The driver circuit (12), the calibration circuit (14) and the terminating resistor (13) are formed on the same semiconductor integrated circuit SK, and the calibration circuit (14) detects process variation and temperature variation of the transistor and the resistor formed on the semiconductor integrated circuit (SK).

Abstract: A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch, the first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit resp

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: An integrated circuit device includes a receiver that is capable of receiving and converting either differential input signals or two unrelated single-ended input signals.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: A self-adaptive output buffer for an output terminal of an electronic circuit suitable to be connected to a load is proposed. The self-adaptive output buffer includes means for sensing an indication of the capacitance of the load and means for driving the load according to the sensing, wherein the means for sensing includes capacitive means with a preset capacitance, means for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring a measuring voltage at the capacitive means due to a charge sharing between the capacitive means and the load.

Abstract: An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

Abstract: This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.

Abstract: A low voltage differential signaling (LVDS) transmitter receives a data signal, a data invert signal and a plurality of logic signals. The LVDS transmitter includes a first-stage differential signaling transmitting circuit and a second-stage differential signaling transmitting circuit. The first-stage differential signaling transmitting circuit receives the data signal and the data invert signal and has a first output terminal and a second output terminal. The second-stage differential signaling transmitting circuit is controlled by the logic signals, and has a third output terminal and a fourth output terminal respectively connected to the first output terminal and the second output terminal, so as to generate a needed pre-emphasis signal. When no pre-emphasis signal needs to be generated, the second-stage differential signaling transmitting circuit is controlled to be in disabled state.

Abstract: A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal.

Abstract: A data input/output driver for use in a semiconductor memory device includes a data transmitting block for transmitting a data between an inside and an outside of the semiconductor memory device and generating a data driving signal in order to indicate a timing of outputting the data. A reference data generating block generates a reference data. A switching block outputs the reference data in response to the data driving signal. The data and the reference data are combined as an output signal.

Abstract: A drive module for driving a load is disclosed. In one embodiment, the drive module includes an output terminal for connecting the load. A first control terminal is provided for applying a first control signal, according to which the circuit arrangement provides a supply voltage having a first or a second voltage level at the output terminal. A second control terminal is provided for applying a second control signal the slope of an edge in the event of a level change in the supply voltage being dependent on the second control signal.

Abstract: A system includes an apparatus for reducing leakage in a circuit. The apparatus includes one or more active devices connected to form a main circuit portion and at least one other active device coupled between the main circuit portion and one from the group including ground and Vdd, the other active device being configured to control leakage in the main circuit portion. A gate length, a gate oxide, and a threshold voltage of the other active device are optimized for low leakage.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

Abstract: A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.

Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.

Abstract: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

Abstract: The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signal and the latch output signal, in which the pull-up circuit increases an output voltage of the output driver circuit from a ground level to a first level when the preset enable signal is at a low level and the latch output signal is at the high level.