Abstract: A circuit is disclosed. The circuit includes an output driver with a pull-up device, and a pull-down device. The circuit also includes a pre-driver, configured to generate a first signal for the pull-up device and to generate a second signal for the pull-down device, a first positive feedback circuit configured to increase the slew rate of the first signal in response to a transition in the second signal, and a second positive feedback circuit configured to increase the slew rate of the second signal in response to a transition in the first signal.

Abstract: The present invention relates to an apparatus and a method for transmitting wireless power, and more particularly, to an apparatus and a method for transmitting wireless power that rapidly and precisely adjusts impedance so as to transmit desired power. Disclosed an apparatus for transmitting wireless power that performs wireless power transmission, including: an oscillator; an amplifier; an impedance matcher including a matching network which adjusts impedance according to a digital control signal and an analog signal, a sensor, a digital controller which outputs a digital control signal, and generates an analog control start signal when adjustment of the impedance by the digital control signal is completed, and an analog controller which outputs the analog control signal, and a transmitting antenna which radiates the magnetic field by using the transmission power.

Abstract: A fully integrated circuit configuration that can be used to control the power path of a number of PMOS load switches is described. The circuit has a unique feature that it can automatically select the input voltage to be presented to the VOUT pin based upon the voltage levels at the respective VIN pins. By using combinations of the EN input pin and the SEL input pin, the circuit can be configured to perform one of four functional behaviors: 1. Complete shutdown (both switches in the OFF position), 2. Automatic input selection according the voltage levels that are presented on the VIN pins, 3. Selection of the VIN1 input only, or 4. Selection of the VIN2 input only. This concept is extended to multiple input sources in further embodiments.

Abstract: A circuit includes a power-on control circuit and a voltage generating circuit. The power-on control circuit is configured to cause a power-on control signal to follow a voltage level of a first supply voltage during a first time period that a voltage level of a second supply voltage is less than a threshold value, and to set the power-on control signal to have a voltage level of a reference voltage during a second time period that the voltage level of the second supply voltage is greater than the threshold value. The voltage generating circuit is configured to generate a voltage signal responsive to the power-on control signal.

Abstract: A driver circuit for driving a transmission line, such as a cable or a metal trace on a printed circuit board is described. The driver may be configured to drive lines with voltages exceeding the maximum voltage than a transistor can withstand for a given fabrication node. The driver may be configured to receive a supply voltage larger than that indicated by manufacturers. The driver may use a fast path and a slow path. Signals provided by the slow path and the fast path may be combine to adapt the input signals to levels that do cause stress to a transistor. A plurality of drivers of the type described herein may be used to provide digital-to-analog conversion.

Abstract: A driver includes a first level shifting unit generating a second signal swinging in a second threshold range in response to a first signal swinging in a first threshold range, a second level shifting unit generating a third signal swinging in a third threshold range in response to the second signal, a first pull-up driving unit driving an output terminal with a first high-voltage in response to the second signal, a first pull-down driving unit driving the output terminal with a first low voltage in response to the third signal, a second pull-down driving unit driving the output terminal with a second low voltage higher than the first low voltage in response to the fourth signal, and a first path coupling unit coupling the second pull-down driving unit with the output terminal in response to the second signal.

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Abstract: A circuit may include an output circuit with an output circuit output impedance and a control circuit. The output circuit may include a driver circuit that includes an output terminal and a driver circuit output impedance at the output terminal. The output circuit may also include an adjustable impedance circuit that includes an adjustable impedance. The adjustable impedance circuit may be coupled between the output terminal of the driver circuit and a signal transmission line. The output circuit output impedance may be based on the driver circuit output impedance and the adjustable impedance. The control circuit may be coupled to the adjustable impedance circuit. The control circuit may be configured to adjust the adjustable impedance of the adjustable impedance circuit such that the output circuit output impedance approximately equals a particular impedance.

Abstract: A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

Abstract: A semiconductor device may include a ZQ calibration circuit, a reference code setting circuit, a variable information generating circuit, and an internal circuit. The ZQ calibration circuit may perform a ZQ calibration operation in response to a ZQ calibration enable signal to generate a ZQ calibration code. The reference code generating circuit may output a predetermined code value as a reference code. The variable information generating circuit may compare the ZQ calibration code to the reference code to generate variable information. The internal circuit may determine operation timings based on a difference between the ZQ calibration code and the reference code.

Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner may generate a baseline current using a baseline capacitor and may provide the baseline current to the channel input.

Abstract: A switching power voltage regulator includes a pulse width modulation (PWM) signal generator, an output circuit and a feedback circuit. The PWM signal generator is configured to generate a PWM signal. The feedback circuit is configured to provide a feedback signal to the output circuit according to an output voltage of the output circuit. The output circuit includes an inductor, a plurality of inverters, and a driver. Each of the inverters includes a first transistor and a second transistor. When the inductor needs to be charged, the driver selectively switches one or more corresponding first transistors on according to the feedback signal.

Abstract: Embodiments of apparatuses and methods for proportional feedback for reduced overshoot and undershoot in a switched output are described. An embodiment of an apparatus includes a switching output stage configured to receive an input signal and provide a responsive output signal. The apparatus may also include a pulling circuit coupled to one of the first switching device and the second switching device. The pulling circuit may pull a control voltage of power transistors in the switching output stage to reduce impedance of at least one of the transistors in response to a determination that the output signal at the common output node is outside of a predetermined range of a threshold value. Pulling strength may increase as a voltage difference between the output signal and one of the first supply voltage and the second supply voltage increases.

Abstract: A semiconductor device includes: a pre-emphasis control signal generation block suitable for generating first and second pre-emphasis control signals for controlling a pre-emphasis operation; at least one first output driver suitable for being selectively enabled in response to a selection code signal and driving a pad in response to a first output signal; and at least one second output driver suitable for being selectively enabled in response to the selection code signal and the first pre-emphasis control signal, performing the pre-emphasis operation with a driving force corresponding to a calibration code signal, and performing the pre-emphasis operation with a maximum driving force in response to the second pre-emphasis control signal.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: This system for transmitting avionic information of the type including means for transmitting data frames through at least one transmission network based on avionic switches, intended for corresponding receiving means. The system further includes means for determining the crossing time by at least some of the data frames of at least some of the switches and means on the network for transmitting a corresponding crossing time information frame associated with this data frame, intended for corresponding receiving means.

Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit.

Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

Abstract: An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.

Abstract: A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Abstract: A pulse generation circuit, for outputting a pulse signal at an output terminal, comprises a PMOS, an NMOS and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate coupled to a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate coupled to a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first logic signal, relating to the second gate control signal and a delay signal of the second gate control signal, and generates the second gate control signal according to the control signal and a second logic signal, relating to the first gate control signal and a delay signal of the first control signal.

Abstract: A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.

Abstract: An output buffer apparatus is provided. A clamp circuit outputs a clamp voltage through a transistor pair having a first configuration. A bias circuit outputs a bias voltage through a transistor pair having a second configuration. A rate control circuit for rising/falling edge buffers an input signal according to the clamp voltage and the bias voltage to generate a buffered signal.

Abstract: A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.

Abstract: A method for reducing common-mode disturbances during power-on and power-off modal transitions in a current driver includes providing a programmable current source operative to generate a current having a controllable rise-time and controlling the programmable current source such that a rise-time of the current generated by the current driver is set to a first rise-time value during power-on and power-off modes of operation and is set to a second rise-time value during polarity transitions in a data mode of operation of the current driver, the first rise-time value being greater than the second rise-time value.

Abstract: Automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver and power stage circuits have been achieved by using multiple feedback control signals. These feedback signals are taken both from the gates of power devices on high side and low sides and from the gates of one or more devices on both high side and low side that enable power device ON state. No duty cycle limitation is required of the input signal. The control logic uses NAND/NOR RS latches. The solution disclosed can readily be scaled to higher order of feedback loops providing even greater level of robustness.

Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Abstract: A Controller Area Network (CAN) driver (a transmitter) includes a conventional main driver having an open drain first driver MOSFET, for pulling up a first conductor of a bus in a dominant state, and an open drain second driver MOSFET, for pulling down a second conductor of the bus in the dominant state. Since it is difficult to perfectly match the driver MOSFET characteristics for conducting exactly equal currents during turning on and turning off, significant common mode fluctuations occur, resulting in electromagnetic emissions. Source followers are respectively connected in parallel with the first driver MOSFET and the second driver MOSFET for creating a low common mode loading impedance on the conductors during times when the main driver MOSFETs are turning on and turning off to greatly reduce any common mode fluctuations caused by the main driver MOSFETs.

Abstract: A semiconductor device, includes an input buffer, first and second PMOS transistors serially interconnected between a first power supply node and an output node of the input buffer. First and second NMOS transistors are serially interconnected between a second power supply node and the output node of the input buffer. A replica circuit includes a third and fourth PMOS transistors serially interconnected between the first power supply node and an output node of the replica circuit. Third and fourth NMOS transistors are serially interconnected between the second power supply node and the output node of the replica circuit. The input node of the replica circuit is connected to the output node of the replica circuit and a comparison circuit compares a voltage at the output node of the replica circuit to a reference voltage.

Abstract: A data output circuit of a semiconductor apparatus may include a first driver coupled to an output terminal via a first node, a second driver coupled to the output terminal via a second node and a controller coupled to the first and second drivers and configured to adjust a slew rate of a data signal output via the output terminal.

Abstract: A valley inductance current polarity change in a pulse width modulated circuit charged with an inductive charge is detected by comparing respective times that a first output of the circuit charged with an inductive charge and a second output of a pulse width modulated reference circuit with no inductive charge reach an output level. Responsive thereto, control over operation of the pulse width modulated circuit charged with an inductive charge is made with respect to switching to a pulse skipping mode of operation or keeping the pulse width modulation mode of operation.

Abstract: It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and—each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line.

Abstract: In some aspects of the invention, provided is a semiconductor device capable of compensating sufficiently instantaneous drop of power source voltage without enlarging device scale extremely. When digital circuit and power device driving circuit are formed on chip in the state connected to power source in common in parallel, for digital circuit of functional circuit remaining abnormal state after power source recovery and analog circuit and power device driving circuit of functional circuit retaining continuously normal state even before power source recovery, resistors are formed on chip in power source E side of the functional circuits, and in addition, capacitors are formed on chip 1 in parallel with the functional circuits, and consequently, it becomes possible to enlarge each resistance value of resistors as compared with a case of attaching externally resistors and capacitors in the entire chip.

Abstract: An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.

Abstract: A switching circuit includes a first switch, a second switch, and a reservoir capacitor. The first switch includes a first gate, a first source, a first drain, and a first gate-to-source capacitor coupled between the first gate and the first source. The second switch includes a second gate, a second source, a second drain, and a second gate-to-source capacitor coupled between the second gate and the second source. The reservoir capacitor is coupled to both the first gate and the second gate. When the first switch is turned on, the first gate-to-source capacitor is charged by a power voltage source and accumulates charges. When the first switch is turned off, the reservoir capacitor is charged by the charges from the first gate-to-source capacitor. The charges stored in the reservoir can be used to charge the second gate-to-source capacitor.

Abstract: Various methods and devices that involve power-on-reset (POR) circuits are disclosed herein. An exemplary POR circuit for generating a POR signal upon detecting that a supply voltage has reached a desired level comprises a sense circuit and a delayed buffer. The sense circuit comprises: (i) an inverter powered by a known bias voltage; (ii) a feedback circuit powered by the supply voltage; and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level. The delayed buffer is coupled to the output node of the sense circuit that generates the POR signal in response to the voltage transition. The feedback circuit shuts off the sense circuit in response to the voltage transition. The POR circuit generates the POR signal for a local system. The known bias voltage is provided by an external system.

Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well.

Abstract: A semiconductor device includes: a pre-emphasis control signal generation portion suitable for generating a pre-emphasis control signal for a pre-emphasis operation; and a plurality of output drivers, a portion of which performs the pre-emphasis operation based on the pre-emphasis control signal when an output operation is performed.

Abstract: A driver for a power transistor switch comprising a FET complementary output stage which is driven by another FET complementary pre-driver stage which is further driven by an input-buffer and level-shifter stage. The pre-driver stage includes a current-limiting and cross-delaying circuit which is inserted in between drains terminals of a complementary FET pair. The current-limiting and cross-delaying circuit limits shoot-current at the pre-driver stage; and in conjunction with the FET pair and the input-buffer and level-shifter stage, it is adapted to delay turning on one complementary output FET until after the other complementary output FET is turned off, thereby preventing cross conduction at the output stage.

Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.

Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

Abstract: A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.

Abstract: A device for grounding pop-click noise may include an output block configured to generate an output signal at an output node. A switch circuit coupled to the output node may be configured to be operable to couple the output node to a ground potential. The switch circuit may include a first and a second transistor. A drain, a source, and a gate node of the first transistor may be coupled to the output node, a drain node of the second transistor, and a first control signal, respectively. A drain, a source, and a gate node of the second transistor may be coupled to a source node of the first transistor, the ground potential, and a second control signal, respectively. The first and the second control signals may operate the switch circuit to couple the output node to the ground potential during a pre-determined period associated with the pop-click noise.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: An Electro-Static-Discharge (ESD) protection circuit uses Silicon-On-Insulator (SOI) transistors with buried oxide but no parasitic substrate diode useable for ESD protection. A filter voltage is generated by a resistor and capacitor. When a VDD-to-VSS ESD positive pulse occurs, the filter voltage passes through an n-channel pass transistor and inverted to drive a gate of a big SOI transistor that shunts ESD current. A second path is used for a VSS-to-VDD ESD positive pulse. The filter voltage passes through a p-channel pass transistor to the gate when the positive ESD pulse is applied to VSS. The big SOI transistor can connect between VDD and VSS for a power clamp, and the gates of the n-channel and p-channel pass transistors connect to VDD. A small diode may be added between VDD and VSS to generate a small triggering current to activate grounded-gate transistors near I/O pads for full-chip Pad-based ESD protection.

Abstract: Embodiments of the invention are generally directed to a configurable multi-mode driver and receiver. An embodiment of a communication system includes a communication channel, and a first device and a second device coupled with the communication channel. The first device includes a driver apparatus to drive data signals on the communication channel, the driver apparatus including circuits to receive and drive the data signals, where the circuits are configurable for termination resistance of the driver circuit apparatus, and each of the plurality of circuits is comprised of one or more circuit units, the circuit units being configurable for equalization control of the driver apparatus. The second device includes a receiver to receive data signals from the communication channel as an input. Either the first device or the second device includes configurable circuit elements to provide signal reflection control for the system.

Abstract: A duty-cycle distortion self-correcting delay line has an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal. The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.

Abstract: In accordance with embodiments of the present disclosure, an apparatus may include an input for indicating a characteristic of an output load current of a switched output stage comprising at least one driver device and a predriver circuit coupled to the input and a gate terminal of the at least one driver device, the predriver circuit for driving an input voltage signal to the gate terminal and configured to select an effective impedance of the gate terminal based on the input for indicating the output load current. In accordance with these and other embodiments of the disclosure, a method may include receiving an input for indicating a characteristic of an output load current of a switched output stage comprising at least one driver device and selecting an effective impedance of a gate terminal of the at least one driver device based on the input for indicating the output load current.

Abstract: A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage and the gate of the power MOS transistor. The adaptive pull-up unit maximizes pull-up current driving ability. The adaptive pull-down unit is connected between a second power source voltage and the gate of the power MOS transistor. The adaptive pull-down unit maximizes pull-down current driving ability.