Abstract: A transceiver circuit may include: a first NMOS transistor suitable for pulling up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.

Abstract: A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device is provided. The switch device has the gate terminal, a drain terminal, and a source terminal. The waveform conversion circuit includes a parallel circuit of a first capacitor and a first resistor and a voltage clamp unit. The parallel circuit is coupled between the controller and the gate terminal. The voltage clamp unit is coupled between the gate terminal and the source terminal and configured to clamp a voltage across the gate terminal to the source terminal at a first voltage in an OFF pulse of the control signal and at a second voltage in an ON pulse of the control signal.

Abstract: The present disclosure relates to a touch circuit, a touch sensing device, and a touch sensing method. According to the present disclosure, it is possible to obtain an accurate touch sensing result (the presence or absence of a touch and/or a touch position) by compensating for the unintentional change in the quantity of the charge corresponding to a signal obtained by driving a touch screen panel, so as to obtain sensing data in which the influence of the parasitic capacitance generated inside or outside the touch screen panel is reduced or eliminated, thereby improving capacitance-based touch sensing performance.

Abstract: Disclosed are structures and methods for CMOS drivers that drive silicon optical push-pull Mach-Zehnder modulators (MZMs) with twice the drive voltage per interferometer arm as with prior art designs.

Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.

Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.

Abstract: A capacitance-sensing circuit may include a plurality of channel inputs associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a baseliner component that is coupled to the plurality of channel inputs. The baseliner component may generate a baseline compensation signal using a capacitive circuit and may provide the baseline compensation signal to each of the plurality of channel inputs of the capacitive sense array.

Abstract: Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.

Abstract: Apparatus embodiments of the invention are disclosed for requesting power via a wired interface. In example embodiments, a pull-down circuit in the apparatus acting as a power consumer when there is no energy in the apparatus, is connected via a configuration line over a cable to a power provider device. The apparatus may be in a power down mode, it may have an empty battery, or it may have no battery. The pull-down circuit is configured to use energy from the configuration line to pull down a voltage on the configuration line, to signal the power provider device to provide power over another line of the cable to the apparatus.

Abstract: An output circuit includes a first transistor, a second transistor, an operational amplifier that outputs a control voltage, and a switch circuit that controls voltage output in accordance with a control signal. When the control signal is in a first state, the switch circuit supplies the control voltage to the gate of the first transistor to turn on the first transistor and electrically connects the drain of first transistor to the operational amplifier so that a first output voltage is output from the drain of the first transistor. When the control signal is in a second state, the switch circuit supplies the control voltage to the gate of the second transistor to turn on the second transistor and electrically connects the drain of the second transistor to the operational amplifier so that a second output voltage is output from the drain of the second transistor.

Abstract: A digitally-assisted voltage regulator includes a gate driver circuit and a compensation circuit. The voltage regulator digitizes the load profile, and uses the digital information to compensate for process and temperature variations. The voltage regulator outputs a regulated voltage signal and one or more control signals based on a supply voltage and a reference voltage. The gate driver circuit receives the regulated voltage signal and generates a gate driver signal. The compensation circuit receives the control signal and generates first and second compensation signals. The voltage regulator regulates a voltage level of the regulated voltage signal using the regulator compensation signal, and controls a ramp-rate of the gate driver signal using the second compensation signal.

Abstract: A level shift includes a bias voltage providing circuit, a level shifting circuit and an output switching circuit. The level shifting circuit includes a high level shifting unit and a low level shifting unit. When the high level shifting unit is in a cut-off state, the high level shifting unit further receives a first bias voltage such that the high level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the high level shifting unit. When the low level shifting unit is in a cut-off state, the low level shifting unit further receives a second bias voltage such that the low level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the low level shifting unit. The level shifter of the present application provides a higher response speed.

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal. At least two of the respective delays may have a different duration. The first circuit may also be configured to change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.

Abstract: A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

Abstract: Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.

Abstract: A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor. In a particular embodiment, the circuit can be a cascode circuit.

Abstract: Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.

Abstract: The present invention discloses a differential signal skew detecting circuit configured to detect a skew of a differential signal. An embodiment of the circuit includes: a common mode voltage outputting circuit configured to output a common mode reference voltage and a common mode skew voltage; and a skew detecting circuit configured to inspect the common mode reference voltage and the common mode skew voltage according to a clock signal so as to output a skew detection value, in which when the skew detecting circuit detects the skew of the differential signal, the skew detection value is a first value, and when the skew detecting circuit detects no skew of the differential signal, the skew detection value is a second value.

Abstract: A circuit for minimizing a cross-conduction time interval includes a phase node, a high-side gate drive node, a low-side gate drive node, a high-side FET coupled to the high-side gate drive node, and a low-side FET coupled to the low-side gate drive node. A high-side adjustable delay delays a transition edge of a high-side gate drive signal. A low-side adjustable delay circuit delays a transition edge of a low-side gate drive signal. A high-side delay adjustment guidance circuit provides high-side delay adjustment guidance based on a detected body-diode conduction of the low-side FET detected during a first time period. A low-side delay adjustment guidance circuit provides low-side delay adjustment guidance based on a detected body-diode conduction of the low-side FET detected during a second time period.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Abstract: A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first circuit is coupled to the first terminal and the second terminal. The first circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and a delay setting. The delay setting corresponds to a delay between successive ON times of the first switch and the second switch. The second circuit is coupled to the first circuit. The second circuit is configured to monitor a first voltage on the first terminal and a second voltage on the second terminal, and to generate the delay setting based on at least the first voltage on the first terminal, or the second voltage on the second terminal.

Abstract: A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer may include a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer may include a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer may include a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal.

Abstract: A CAN module comprising a bit duration compensation component arranged to generate a compensated transmit command signal for controlling the driver component to drive a dominant state on the CAN bus. The compensated transmit command signal comprises dominant bits of a compensated-bit duration Tbit_cp=Tbit_Tx+tc, wherein tc comprises a compensation offset derived at least partly from a difference between a transmit-bit duration of a digital transmit command signal and a receive-bit duration of a received data signal.

Abstract: A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A panel function test circuit is able to perform a function test when a display panel is in a first state and is able to perform electrostatic protection when the display panel is in a second state, whereby the display panel requires fewer components and less wiring space.

Abstract: An once a channel voltage exceeds a threshold, when the transistor is in an OFF state. This is over-voltage protection circuit for a transistor is presented. This circuit acts to switch on the transistor achieved with internal components which are integrated with the transistor, avoiding the need for external diodes or Zener structures. The circuit has a transistor with a control terminal, a first current carrying terminal and a second current carrying terminal. The over-voltage protection circuit has a level shifter arranged to feed back a level-shifted version of a channel voltage between said first and second current carrying terminals to the control terminal. The level shifter allows the switching threshold voltage of the transistor to be crossed when a predetermined value of the channel voltage is crossed.

Abstract: Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.

Abstract: A low-voltage differential signaling transmitter includes a stage-by-stage amplification module, a level adjustment module, and a drive module. The level adjustment module shifts upward and shift downward a differential mode received signal, so as to, after enabling upward-shifted and downward-shifted signals to overcome a threshold voltage of a load transistor inside a post-stage circuit, have more headroom to improve an operation bandwidth of the load resistor. A low-voltage differential signaling receiver is also proposed herein.

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) on a plurality of devices. A first device and a second device are provided for testing. A test signal is provided for performing a time-dependent dielectric breakdown (TDDB) test on the first and second devices. A selection signal for selecting said first and second devices for performing said TDDB test. The first and second devices are arranged in series with a first resistor such that based upon said selecting, the test signal is applied substantially simultaneously to the first and second devices through the first resistor. A determination is made as to whether a breakdown and/or a failure of at least one of the first and second devices has occurred based upon a change in voltage across the first resistor.

Abstract: A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such as one or more inverters, configured to generate the second transition in response to receiving the first transition, where the second transition is delayed with respect to the first transition. Such line driver may be used to signals having high data rates to transmission lines, such as cables or metal connection on printed circuit boards.

Abstract: Apparatus embodiments of the invention are disclosed for requesting power via a wired interface. In example embodiments, a pull-down circuit in the apparatus acting as a power consumer when there is no energy in the apparatus, is connected via a configuration line over a cable to a power provider device. The apparatus may be in a power down mode, it may have an empty battery, or it may have no battery. The pull-down circuit is configured to use energy from the configuration line to pull down a voltage on the configuration line, to signal the power provider device to provide power over another line of the cable to the apparatus.

Abstract: Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A semiconductor integrated circuit device may include a main inverter and a negative bias temperature instability (NBTI) compensating circuit. The main inverter may be configured to receive an input signal. The main inverted may be configured to reverse the input signal. The main inverter may include a PMOS transistor and an NMOS transistor. The NBTI compensating circuit may be configured to receive the input signal. The NBTI compensating circuit may be selectively driven in an operation start time section of the PMOS transistor in the main inverter to compensate a driving force of the PMOS transistor.

Abstract: Devices and methods are provided where a feedback is provided from a control terminal of a first switch, and a second switch is controlled based on the feedback.

Abstract: A semiconductor device may include a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer. The semiconductor device may include a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer. The semiconductor device may include a first input/output (I/O) unit configured to input and output the first signal or the second signal through the first I/O unit. The semiconductor device may include a first selection unit configured to selectively couple a connection among the first redistribution layer, the second redistribution layer, and the first I/O unit in response to a logic level of a first selection signal. The semiconductor device may include a first selection signal generation unit configured to generate the first selection signal.

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

Abstract: Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.

Abstract: The semiconductor device for fabricating an IC is provided. The semiconductor device includes a deep n-well (DNW), a first inverter, a second inverter, an electrical path, and a charge-dispelling device. The DNW is formed in a substrate. The first inverter is formed inside the DNW. The second inverter is formed in the substrate and outside the DNW. The electrical path is arranged between the first inverter and the second inverter. The charge-dispelling device is connected between the ground of the first inverter and the ground of the second inverter to develop a bypass path. The impedance of the bypass path is lower than the impedance of the electrical path.

Abstract: A semiconductor device includes a first driver configured to pull up a voltage level of a pad to a first power voltage in response to a driving signal, a second driver configured to pull down the voltage level of the pad to a second power voltage in response to the driving signal, a switch protection resistor configured to change an electrical resistance between the pad and the second driver in response to a switch control signal, and an ESD detector configured to detect a voltage level of the first or second power voltage and generate the switch control signal.

Abstract: An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.

Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.