Abstract: According to one embodiment, there is provided an output circuit including a driver transistor and a pre-driver circuit. The driver transistor is connected to an output terminal. The pre-driver circuit is configured to turn ON/OFF the driver transistor. The pre-driver circuit includes a first transistor, a second transistor, a third transistor. The first transistor is configured to control ON speed of the driver transistor. The second transistor is connected in parallel with the first transistor. The second transistor is configured to control ON speed of the driver transistor. The third transistor is connected in parallel with the first transistor and in series with the second transistor. The third transistor is configured to activate or deactivate the second transistor.

Abstract: Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.

Abstract: A semiconductor apparatus includes a switching device, a voltage detection circuit, a switch circuit, and a control circuit. The voltage detection circuit outputs a detection voltage according to a voltage applied between the first and second terminals of the switching device. The switch circuit is provided in series with a gate drive wire connected to the gate terminal of the switching device and switches between a high impedance state and a low impedance state according to a control signal. The control circuit outputs the control signal to put the switch circuit into the low impedance state when the detection voltage is not greater than a predetermined threshold voltage and outputs the control signal to put the switch circuit into the high impedance state when the detection voltage is greater than the threshold voltage.

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract: A serial data transmission system includes a sending terminal for sending data, a receiving terminal for receiving the data sent by the sending terminal, a first connecting capacitor connected between the sending terminal and the receiving terminal, and a second connected capacitor connected between the sending terminal and the receiving terminal. The sending terminal includes a sending terminal driving unit, and an amplitude detecting unit connected to the sending terminal driving unit. The sending terminal driving unit outputs a pair of differential signals according to signals of the received data. The amplitude detecting unit detects changes in amplitudes of the differential signals outputted by the sending terminal driving unit, and outputs an indicating signal for indicating whether the sending terminal is properly connected to the receiving terminal. A serial data transmission method is further provided.

Abstract: An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another.

Abstract: Some of the embodiments of the present disclosure provide a method comprising outputting data at a logic circuit; and in anticipation of a possible change in the data during a data window, applying at least a partial inversion to an output of the logic circuit from a start of the data window.

Abstract: An output driver for driving a data output signal through an output pad includes a plurality of calibration paths to calibrate the impedance of the output pad. Depending upon the desired impedance, various ones of the calibration paths are selectively coupled to the output pad. Each selected calibration path adds a capacitive load to a data node, which affects the slew rate for the data output signal. To adjust the capacitive load on the data node in light of the calibration path selections, the output driver includes a plurality of selectable capacitors corresponding to the plurality of calibration paths. If a calibration path is not selected to couple to the output pad, the corresponding selectable capacitor capacitively loads the data node.

Abstract: A converter circuit includes a converter and a controller. The converter converts an input voltage to an output voltage. The controller receives a reference voltage, generates a slew voltage having a substantially constant first slew rate if the reference voltage changes from a first level to a second level, and controls the converter based on the slew voltage to cause the output voltage to change from a third level to a fourth level at a substantially constant second slew rate.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: An inverter is capable of improving the reliability of driving. The inverter includes a first transistor and a second transistor. The first transistor is coupled between a first power source and an output terminal of the inverter, and has a first gate electrode coupled to a first input terminal of the inverter and a second gate electrode coupled to a third power source. The second transistor is coupled between the output terminal and a second power source, and has a first gate electrode coupled to a second input terminal of the inverter and a second gate electrode coupled to the third power source.

Abstract: An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: A low-leakage IO circuit is provided. The IO circuit includes an impedance path between a pad and a power supply. The impedance path bypasses a signal path of the pad and includes a switch circuit. According to a relationship between voltages of the power supply and the pad of the IO circuit, the switch circuit selectively conducts the impedance path. When the power supply provides power normally, the switch circuit conducts the impedance path to provide a pull-up resistor between the pad and the power supply. When the power supply provides no power and its voltage is lower than a voltage of the pad, the switch circuit disconnects the conducting path to effectively reduce power leakage.

Abstract: A serial communication apparatus includes a slew rate control circuit, an output circuit, a detection circuit, and a switching circuit. The slew rate control circuit has a predetermined impedance, and supplies a constant current from an output according to an input signal. In the output circuit, first capacitance is charged and discharged by the constant current from the slew rate control circuit. The output circuit outputs a digital signal from an output terminal according to a drive voltage. The noise detection circuit detects noise propagated from the output terminal, and outputs a switching signal according to a detection result. The switching circuit switches an impedance of the slew rate control circuit to a value smaller than the predetermined impedance according to the switching signal.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored.

Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

Abstract: The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.

Abstract: An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream.

Abstract: Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

Abstract: A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive circuits is selected as the selected bus drive circuit. When a logical value corresponding to the data input to be output is the same as a logical value that has been held by the bus holder and output to the common bus, the selected bus drive circuit stops outputting the logical value corresponding to the data input to the common bus. With this configuration, it is possible to eliminate the unnecessary output of the selected bus drive circuit, and to reduce unnecessary current consumption compared to the conventional semiconductor integrated circuit.

Abstract: Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUT1 exceeds an upper threshold V90% while a control signal EN_PG is active, and produces an inactive level of PG if EN_PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUT1 is less than a lower threshold V10% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUT1, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer.

Abstract: An interface device for connection between two electronic components of an electronic circuit, includes: an input terminal, an output terminal and a reference terminal, an input voltage between the reference and input terminals, an output voltage between the reference and output terminals, an input impedance, and an output voltage gain, at least one resistance connected to at least one terminal among the input and output terminals, at least one analog switch positioned between the output and reference terminals, the switch having a closed or an open state, and control elements for each switch, at least one parameter among the input impedance and the output voltage gain of the device having distinct values as a function of whether the analog switch is closed or open, each analog switch including at least one N-type field effect controllable transistor and one P-type field effect controllable transistor connected in series.

Abstract: A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.

Abstract: An integrated circuit includes a first plurality of transistors and a second plurality of transistors coupled together to form a standard cell that performs a logic function. Each of the first plurality of transistors is more critical to a speed of operation of the standard cell than any of the transistors of the second plurality of transistors. Each of the first plurality of transistors has a gate length longer than a gate length of any of the transistors of the second plurality of transistors.

Abstract: Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed.

Abstract: An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command.

Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: A method is provided for controlling a data transmission device. The method includes providing a reference voltage to the common mode driver and putting the data transmission device in a low power state. The method also includes driving a differential signal pair output from the common mode driver during a portion of the low power state. Also provided is a device that includes a data output driver portion configured to drive an output signal at a common mode voltage and a data output driver portion configured to drive an output signal at a differential voltage level during at least a portion of time when the device is not in a low power state. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the device. Also provided is an apparatus configured to perform the method.

Abstract: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

Abstract: An electromagnetic interference (EMI) shielding circuit and a semiconductor integrated circuit including the same are provided. The EMI shielding circuit includes a data level comparison unit, a control signal generation unit, and a driver for EMI cancellation. The data level comparison unit generates a data comparison signal by comparing a number of high-level data transmitted through a plurality of data lines and a number of low-level data transmitted through the plurality of data lines. The control signal generation unit generates a driving control signal in response to the data comparison signal. The driver for EMI cancellation outputs an EMI cancellation signal in response to the driving control signal.

Abstract: A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs.

Abstract: High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC.

Abstract: A semiconductor integrated circuit includes: a first transistor and a second transistor connected in series between a first voltage and a second voltage; a first inverter configured to control the first transistor; a second inverter configured to control the second transistor; and a current source, wherein the current source is connected in series with at least one of the first inverter or the second inverter.

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

Abstract: A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.

Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.

Abstract: An output circuit includes a first transistor coupled to an external terminal and including a gate terminal that receives a first drive signal. The first transistor drives a potential at the external terminal in accordance with the first drive signal. A first capacitor includes a first end coupled to the gate terminal of the first transistor and a second end coupled to the external terminal. The output circuit also includes a circuit portion coupled to the first transistor. The circuit portion maintains the first transistor in an inactivated state when the gate terminal of the first transistor is in a floating state.

Abstract: Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.

Abstract: A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip.

Abstract: A buffer circuit including an input terminal capable of receiving an input signal and an output terminal capable of being connected to a capacitive load, including an output circuit a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, and means for controlling said first and second transistors receiving the input signal The buffer circuit further includes means for comparing the voltage on the output terminal of the circuit with at least one threshold voltage, the comparison means being connected to said control means.

Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: A transmitter configured for pre-emphasis is described. The transmitter includes a voltage-driven single-ended-termination driver circuitry. The voltage-driven single-ended-termination driver circuitry includes a first termination point and a second termination point. The transmitter also includes a pre-emphasis encoder circuitry. The pre-emphasis encoder circuitry receives a pre-emphasis signal. The transmitter may reduce signal loss in transmission lines by detecting a transition in a data stream, adjusting a source determination resistance and obtaining a gain from the adjusted source determination resistance.

Abstract: An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.