Abstract: An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.

Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Abstract: According to one embodiment, a level conversion circuit includes an intermediate voltage generating portion to generate an intermediate voltage between a first voltage and a second voltage upon receiving the first voltage and the second voltage higher than the first voltage. A buffer portion operates on the intermediate voltage upon receiving a first signal and an inverted first signal of a first amplitude corresponding to the first voltage. The buffer portion outputs a second signal and an inverted second signal having a second amplitude corresponding to the intermediate voltage. A level shift portion operates on the second voltage upon receiving the second signal and the inverted second signal, and outputs a third signal and an inverted third signal having a third amplitude corresponding to the second voltage.

Abstract: One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.

Abstract: In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.

Abstract: A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.

Abstract: Low-power routing multiplexers that reduce static and dynamic power consumption are provided. A variety of different techniques are used to reduce power consumption of the routing multiplexers without significantly increasing their size. For example, power consumption of the routing multiplexers may be reduced by reducing short-circuit currents, reducing leakage currents, limiting voltage swing, and recycling charge within the multiplexer. Multiple power reduction techniques may be combined into a single routing multiplexer design. Low-power routing multiplexers may also be designed to operate in selectable modes, such as, a high-speed, high-power mode and a low-speed, low-power mode.

Abstract: An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, circuitry for producing an oscillatory output signal having a peak voltage of V volts uses MOS transistor circuitry transistors of which are designed for a maximum port-to-port voltage of substantially less than V volts. A first inverter chain is coupled to an input signal to produce a predriver output signal. A second inverter chain of multiple of inverters including a first inverter produces a driver output signal. Circuitry is provided for AC-coupling the predriver output signal to the second inverter chain, it being configured to translate the predriver output signal to a higher voltage range to produce a translated predriver output signal.

Abstract: A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of the first and second level shift circuits includes a first transistor of a first conductivity type having a gate receiving the first and second pulse signals respectively, a source connected to a ground, and a drain that outputs a level shifted pulse signal, and a second transistor of a second conductivity type having a gate connected to the first transistor gate, a drain connected to the first transistor drain, and a source connected to the power supply via a connected transistor group, the connected transistor group includes at least one of the second conductivity type transistors.

Abstract: A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.

Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces.

Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).

Abstract: A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.

Abstract: A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 5, a barrier gate circuit 2 and a holding circuit (MMP1, MMP2). The level converter circuit converts a signal level of a circuit operating in a VDD1 system to a signal level of a VDD2 system. The barrier gate circuit is responsive to a standby signal (STBY) to fix input signals (AB, AAB) of the level converter circuit 5 at a LOW level. The holding circuit holds an output of the level converter circuit 5 at a constant voltage when the input signals (AB, AAB) are at the LOW level (FIG. 1).

Abstract: A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.

Abstract: A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source VH and the N-MOS transistor is connected to a low potential source VL. The gate of each MOS transistor is connected to an input signal line. The inverter circuit further includes a P-MOS transistor connected between a node and input signal line, and an N-MOS transistor connected between a node of the N-MOS transistors and the input signal line. The gates of the P-MOS transistor and the N-MOS transistor are connected to an output signal line of the inverter circuit.

Abstract: A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.

Abstract: An isolated level shifter base cell that is configurable as either an isolated HIGH level shifter or an isolated LOW level shifter based on changes to connection layers, e.g., metal-2 and/or via-1 layers, without adjusting lower layers, or base layers, that form the isolated level shifter base cell. Regardless of the configuration selected, the isolated level shifter base cell requires the same footprint and provides the same input-to-output path timing. Further, the isolated level shifter base cell is configurable as either a HIGH or LOW isolation cell, i.e., without level shifting, based on changes to the connection layers while again maintaining the same footprint and input-to-output path timing. The configuration of the described isolated level shifter base cell can be changed late in the integrated circuit design process without affecting integrated circuit base layers, without changing the integrated circuit footprint, and without introducing integrated circuit timing changes.

Abstract: A circuit arrangement for shifting a voltage level comprises a data-current converter (2) that is connected to a first connection (K1) and that has an input for feeding a digital input data signal (DIN), a first output for providing a current (I), and also a second output for providing a reference current (I1), and a current-data converter (3) that is connected to a second connection (K2) and that has a first input for feeding the current (I), a second input for feeding the reference current (I1), and also an output for providing a digital output data signal (DOUT). Here, a voltage level of the digital output data signal (DOUT) is different from a voltage level of the digital input data signal (DIN). In addition, a method for shifting a voltage level is provided.

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Abstract: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bi-directional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.

Abstract: A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.

Abstract: A level shifter for integrated circuits includes input stage transistors, reference stage transistors, a cascode stage coupled to the input stage and the reference stage transistors and a pair of comparators. The cascode stage generates a first cascode output and a second cascode output. The input stage transistors selectively conduct a low reference voltage as the first cascode output based on a pair of inputs provided to the input stage transistors. The reference stage transistors selectively conduct a high reference voltage as the second cascode output based on a first comparator output and a second comparator output. The pair of comparators generate the first and the second comparator outputs based on the first and the second cascode outputs.

Abstract: In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

Abstract: A level shifter circuit for shifting from a first voltage level technology (such as 0.9 volt) to a second level voltage technology (such as 3.3 volt) with increased switching speed. The increased speed is achieved by adding a boost circuit to the pull-up transistors to boost the switching speed and shut itself down after the transition. The level shifter circuit does not require intermediate level transistors or intermediate level voltage sources.

Abstract: A level converter comprising an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal; and a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit including: a latch circuit having: a first inverter circuit provided in a first path between a second high power source and the low power source; and a second inverter circuit provided in a second path between the second high power source and the low power source, wherein the latch circuit is formed by coupling an input terminal and an output terminal of the first inverter circuit and the second inverter circuit; a first transistor coupled to the first path; and a second transistor coupled to the second path.

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Abstract: An integrated circuit high voltage analog switch has digital logic-level control interface circuit. A level translator is coupled to the digital logic-level control interface circuit. A plurality of output multi-channel high voltage switches is coupled to the level translator.

Abstract: A level shift circuit shifts a first voltage level to a second voltage level that is different from the first voltage level. The level shift circuit includes a set-level circuit 21 configured to detect and transmit a set signal that is used to set a logic voltage state based on the second voltage level, a reset-level circuit 22 configured to detect and transmit a reset signal that is used to reset the logic voltage state based on the second voltage level, and a reference-level circuit C3 configured to provide a reference signal that is used to detect the set signal and reset signal based on the second voltage level. The set-level circuit, reset-level circuit, and reference-level circuit transmit signals from the first voltage level to the second voltage level through capacitors C1, C2, and C3, respectively.

Abstract: A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.

Abstract: A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

Abstract: Level shifting circuits generate multiple tracking signals that are in-phase with an input signal, but are also level-shifted with wider voltage swings relative to the input signal. These input tracking signals are provided as separate inputs to an inverter having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein. A level shifting circuit may include a differential input circuit, which is responsive to true and complementary input signals. A first load circuit is electrically coupled to the differential input circuit. This first load circuit is configured to generate first and second tracking signals at respective first and second nodes therein. These first and second tracking signals are in-phase, level-shifted versions of each other, and have respective voltage swings that are greater than a voltage swing of the complementary input signals.

Abstract: A level shifter includes a level shifting circuit which receives input signal from a function block and changes the voltage level of the input signal, to output an output signal; a current blocking circuit, which suppresses current flowing to the level shifting circuit in an input suppression mode in which power supplied to the function block is cut and deactivates the level shifting circuit; and an output control circuit, which controls the output signal of the level shifting circuit to have a direct current (DC) voltage level in the input suppression mode.

Abstract: A circuit for converting a lower voltage logical signal to a higher voltage. The circuit comprises a current mirror structure having first and second branches, each comprising at least a first transistor of a first kind, an input transistor of a second kind, and a second transistor of the first kind coupled between them. The first transistors are arranged as a current mirror. The input transistors are driven using a logical signal at the lower voltage, controlling the current mirror structure to output a corresponding logical signal at the higher voltage. The second transistors are driven by an intermediate reference voltage so as to reduce the operating voltage of the third transistors. The first kind is tolerant of a higher operating voltage than the second kind.

Abstract: A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.

Abstract: An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a first circuit portion including: a first circuit that is connected between a first high-side power line and a low-side power line and that outputs a second signal based on a first signal input thereto; and a second circuit portion including: a first transistor that is connected between a second high-side power line and a node and that has a normally-on characteristic; a second circuit that is connected between the node and the low-side power line and that outputs a third signal based on the second signal input thereto.

Abstract: Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit (230) detects a transition from a high level to a low level of the input signal and a control circuit (245) operates a first FET to produce the low level of the output signal. A second FET is operated by the high level of the input signal to output the high level of the output signal.

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

Abstract: A circuit comprises first and second buffers, and an output buffer. The first buffer receives an input signal and provides a first buffer output signal on a first lead. The second buffer receives the input signal and provides a second buffer output signal on a second output lead. The output buffer has a first input lead coupled to the first output lead and AC coupled to the second output lead. The AC coupling communicates timing information from the second buffer to the output buffer. The first buffer applies sufficient voltage to control the first input lead of the output buffer under DC conditions.

Abstract: Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power supply terminal (VDD), and a gate connected to an output terminal; a PMOS transistor including a source connected to a source of the depletion type NMOS transistor, a drain connected to the output terminal, and a gate connected to an input terminal; and an NMOS transistor including a source connected to a reference terminal (GND), a gate connected to the input terminal, and a drain connected to the output terminal.

Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

Abstract: Described herein is the method and apparatus for generating symmetrical level shifted signals by a symmetrical level shifter. The symmetrical level shifter comprises an edge detector operable to generate transition edge based pulses from an input signal based on a first power supply level; a voltage level shifter, coupled with the edge detector, operable to convert the transition edge based pulses based on the first power supply level to edge based pulses based on a second power supply level; and a divider circuit, coupled with the voltage level shifter, operable to generate an output signal from the edge based pulses based on the second power supply level.

Abstract: A cross-coupled inverter includes a first inverter and a second inverter cross-coupled such that the input terminal of each inverter is connected to the output terminal of the other inverter. A set signal is input to the gate of a first set transistor, and an inverted set signal is input to the gate of a fourth set transistor. A reset signal R is input to the gate of a first reset transistor of a reset unit, and an inverted reset signal is input to the gate of a fourth reset transistor thereof. The gate of the second set transistor and the gate of the third reset transistor are connected to the output terminal of the second inverter. The gate of the third set transistor and the gate of the second reset transistor are connected to the output terminal of the first inverter.

Abstract: A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, VSS, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic “0” to the true ground level. This eliminates sneak current and logic level corruption.

Abstract: A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.

Abstract: A device for shifting voltage levels includes an input stage, an output stage and multiple cascode sets connected between the input stage and the output stage. The input stage includes input transistors connected to a first voltage and an input for receiving an input signal. The output stage includes output transistors connected to a second voltage and an output for outputting an output signal having a voltage level different from a corresponding voltage level of the input signal. Each cascode set includes corresponding cascode transistors gated to a third voltage, which is between the first voltage and the second voltage, preventing excessive voltage across terminals of the input transistors and the output transistors.