Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: A power interrupting device has: an output terminal connected to a load; interruption circuits connected in parallel between a power source and the output terminal; and a control device controlling each interruption circuit. Each interruption circuit has: a switch element connected between the power source and an intermediate node, and ON/OFF controlled by an interruption signal output from the control device; and a rectifier connected such that a forward direction thereof is from the intermediate node to the output terminal. The control device sets the interruption circuits as a diagnosis target circuit in turn. The control device sets the interruption signal output to each interruption circuit such that the switch element of the diagnosis target circuit is OFF. Moreover, the control device determines, based on a voltage of the intermediate node of the diagnosis target circuit, whether an abnormality occurs in the diagnosis target circuit.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: A push-pull driver according to an example includes a push stage coupled via a first coupling capacitor to an output of the push-pull driver and a pull stage coupled via a second coupling capacitor to the output of the push-pull driver. Using an example may allow to improve a trade-off between saving energy, an overall complexity of a corresponding implementation, a robust and reliable operation and other parameters and design goals.

Abstract: An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input signal; a path switching unit coupled in a path between the pull-up driving unit and the output node according to a direction of a first current flowing between the pull-up driving unit and the output node and operable to selectively switch on or off the path; a pull-down driving unit coupled to the output node to supply a low voltage in response to the input signal; a path blocking unit coupled in a path between the pull-down driving unit and the output node to block the path; and a bypass unit coupled to form a bypass path between the pull-down driving unit and the output node.

Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.

Abstract: Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

Abstract: A transmitter circuit includes: a driver that includes an output resistor set to a resistance value according to an input code, and that outputs, to an output terminal, an output signal; and a high potential side resistor and a low potential side resistor that are connected to the output terminal. The transmitter circuit further includes a high potential side current source that is set with a current value according to the input code, and a low potential side current source that is set with a current value according to the input code. The transmitter circuit further includes a high potential side switch and a low potential side switch that switch between allowing current output from the high voltage side current source and the low voltage side current source to pass, and blocking the current.

Abstract: According to one embodiment, a first impedance adjustment circuit of a driver circuit includes a first resistor having an end connected to a first signal node. The first impedance adjustment circuit includes a first MOS transistor having an end connected to the other end of the first resistor. The first impedance adjustment circuit includes a second resistor having an end connected to the first signal node. The first impedance adjustment circuit includes a second MOS transistor having an end connected to the other end of the second resistor. The first impedance adjustment circuit includes a third resistor having an end connected to the other end of the first MOS transistor and the other end of the second MOS transistor, and the other end connected to the first output pad.

Abstract: Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.

Abstract: The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.

Abstract: Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground.

Abstract: Certain aspects of the present disclosure provide a high-speed AC-coupled inverter-based buffer, which may be used as a buffer for a voltage-controlled oscillator (VCO), for example. One example buffer for a VCO generally includes a first inverter stage having an input node configured to receive a first complementary signal of a differential pair, a second inverter stage having an input node configured to receive a second complementary signal of the differential pair, a biasing stage replicating the first inverter stage or the second inverter stage, wherein an output node of the biasing stage is connected with an input node of the biasing stage, a first impedance coupled between the input node of the first inverter stage and the input node of the biasing stage, and a second impedance coupled between the input node of the second inverter stage and the input node of the biasing stage.

Abstract: A preamplifier circuit comprising six transistors is provided. The first transistor is coupled to a power supply line and the second transistor is coupled to a ground line. The first and second transistors are controlled by an enable signal. The third and fourth transistors are connected between the first and second transistors, for generating a first amplifier output signal in response to a first input signal. The fifth and sixth transistors are connected between the first and second transistors, for generating a second amplifier output signal in response to a second input signal. The first, third, and fifth transistors are of a first conductivity type, and the second, fourth, and sixth transistors are of a second conductivity type. The preamplifier circuit can be applied to any type of ADC that utilizes a comparator.

Abstract: A circuit includes an amplifier output stage that includes a high switch and a low switch that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response to a PWM input signal. The circuit includes a high gate drive that drives the high switch with a PWM high drive signal derived from the PWM input signal. This includes a low gate drive that drives the low switch with a PWM low drive signal derived from the PWM input signal. The circuit includes an edge corrector that adjusts at least one of a leading edge and a trailing edge of the PWM input signal to compensate for response time differences with respect to a direction of the load current to the load.

Abstract: In a driver having a reference point with a reference potential for driving a target switching element having an on-off control terminal, a charging path electrically connects the on-off control terminal of the target switching element and a driving power source for charging the on-off control terminal of the target switching element. A bypass path electrically connects the on-off control terminal of the target switching element and the driving power source. A storage has a first conductive end electrically connected to the bypass path and a second conductive end electrically connected to the reference point of the target switching element, and is configured for storing therein charge sent through the bypass path.

Abstract: A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.

Abstract: An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.

Abstract: A differential driver circuit includes a differential driver configured to drive an output signal based upon a positive leg pull up signal, a positive leg pull down signal, a negative leg pull up signal, and a negative leg pull down signal. A first pre-driver includes a first driver configured to receive a positive leg signal and a first voltage divider coupled to an output of the first driver and configured to produce the first pull up signal and the first pull down signal. A second pre-driver includes a second driver configured to receive a negative leg signal and a second voltage divider coupled to an output of the second driver and configured to produce the second pull up signal and the second pull down signal. The differential driver may include a positive leg and a negative leg, each having a pull up transistor and a pull down transistor.

Abstract: An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a second mode by a digital data transmission stage 103 for digital data and supply, the audio output stage P-channel transistor MP being switchably back-gate biased by a bias circuit 107 according to the operating mode to achieve high-voltage tolerance.

Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.

Abstract: Provided is a transmission drive circuit which can reduce distortions of a transmission signal and transmission noise, and is isolable from a signal line. A transmission drive circuit 700 includes a drive transistor 10 and an isolation diode 31 connected between a node n1 coupled to a signal line SL commonly used to propagate a transmission signal and a reception signal and a power source line HVP, and further includes an isolation diode 32 and a drive transistor 20 connected between the node n1 and a voltage line HVM. Furthermore, the transmission drive circuit 700 includes a switch 41 connected between a node n2 between the drive transistor 10 and the isolation diode 31, and a node n4 of a ground voltage Vs, and a switch 43 connected between a node n3 between the drive transistor 20 and the isolation diode 32, and a node n4.

Abstract: A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair of differential output terminals, a current mode drive unit and a voltage mode drive unit. The pair of differential output terminals has a first output terminal and a second output terminal. The current mode drive unit is arranged for outputting a first reference current from one of the first and second output terminals and receiving the first reference current from the other of the first and the second output terminals according to the first data input. The voltage mode drive unit is arranged for coupling a first reference voltage to one of the first and the second output terminals and coupling a second reference voltage to the other of the first and the second output terminals according to the first data input.

Abstract: Systems and methods are disclosed involving adaptive power up features for high-speed synchronous RAM. In one exemplary implementation, there is provided a semiconductor device including a memory cell, power circuitry, and an output buffer with level shifting circuitry. Moreover, the device may include power circuitry comprised of a first power up circuit and a second power up circuit and/or level shifting circuitry comprised of a pull up level shift circuit and a pull down level shift circuit. Other implementations and specific circuit configurations are also disclosed.

Abstract: A DC-DC converter including an output stage, a feedback loop, a pulse-width modulation (PWM) generating circuit, and a driving circuit is disclosed. The output stage is coupled to an input voltage and an output inductor to provide an output voltage. The feedback loop is coupled to the output inductor and receives the output voltage to generate a control signal. The PWM generating circuit is coupled to the feedback loop and receives the control signal. The PWM generating circuit also includes a timing signal generating unit which makes the PWM generating circuit to generate a PWM signal according to a correction voltage. The correction voltage is reacted in the output voltage and a first current source related to the input voltage. The driving circuit is coupled to the output stage and the PWM generating circuit and receives the PWM signal to control the operation of the output stage.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to toggle the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: A single supply level shifter converts an input logic level IN into level shifted OUT and OUT_X. An IN inverter generates level-shifted OUT at an OUT Node. IN is coupled at an INT Node to a VDD supply rail, through an INT_Node PFET that controls the INT Node based on OUT_X. An OUT_X network includes a separate IN_X inverter (generating inverted IN independent of level shifting), and an OUT_X circuit that controls pull-up/down of an OUT_X Node to generate level-shifted OUT_X, receiving control inputs from both IN and IN_X inverters. The OUT_X circuit is a three FET stack: a pull-up/down PFET/NFET pair receives IN_X, and an OUT_X Node control PFET, coupled between the pull-up PFET and the OUT_X Node, receives OUT. Based on OUT and IN_X, the OUT_X circuit generates OUT_X as an inverted OUT (including supplying OUT_X to the INT_Node PFET to control the INT Node (including OUT pull-up).

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: A circuit for controlling output swing in a current-mode logic circuit is described. The circuit comprises a plurality of current-mode logic circuits coupled in series; a first current-mode logic circuit of the plurality of current-mode logic circuits coupled to provide a signal to a second current-mode logic circuit of the plurality of current-mode logic circuits; an amplitude detector coupled to detect an amplitude of the signal received at the second current-mode logic circuit; and a control circuit coupled to the amplitude detector; wherein the control circuit generates an amplitude control signal for a current-mode logic circuit of the plurality of current-mode logic circuits based upon a detected amplitude of the signal received at the second current-mode logic circuit. A method of controlling output swing in a current-mode logic circuit is also disclosed.

Abstract: A voltage reference circuit includes a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground. A second depletion-mode PMOS transistor is coupled to the first enhancement PMOS transistor to form a feedback circuit. A first resistive device is coupled between the voltage supply and the second depletion-mode PMOS transistor, and a second resistive device is coupled between the second depletion-mode PMOS transistor and the ground. A bias circuit is coupled to a gate of the first enhancement-mode NMOS transistor. The first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region. A first reference voltage across the first resistor and a second reference voltage across the second resistor are configured to be independent of the magnitude of the voltage supply and have low temperature drift.

Abstract: An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system.

Abstract: Dynamic power driven clock tree synthesis is described. Some embodiments can select one or more cells from a cell library based on power ratios of cells in the cell library. The embodiments can then construct a clock tree based on the one or more cells.

Abstract: One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors.

Abstract: A signal transmission circuit includes a driver circuit that includes complementary inverters, each of the complementary inverters including a plurality of transistor switches, each of the plurality of transistor switches including a pair of transistors, one of the pair of transistors operating in a saturation region and another of the pair of transistors operating in a triode region to cause a certain impedance, and that drives each of the plurality of transistor switches in accordance with complementary signals so as to output complementary voltages to a transmission line; and first voltage sources that supply operating voltages to the driver circuit so as to adjust amplitudes of the complementary voltages output from the driver circuit to the transmission line.

Abstract: Provided are a charge/discharge control circuit having a self-test function, which can dispense with a complicated test device, and a battery device. The battery device includes the charge/discharge control circuits each including a pull-up/pull-down circuit provided at a terminal to which a secondary battery is to be connected. When a self-test start signal is input so as to enter a self-test state, a self-test control circuit controls the pull-up/pull-down circuit, to thereby perform a test on a voltage detection circuit provided at the terminal to which the secondary battery is to be connected. When the self-test is finished, a self-test start signal is output to a next-stage charge/discharge control circuit, to thereby perform a test sequentially on the voltage detection circuits of the cascade-connected charge/discharge control circuits.

Abstract: A driving circuit includes a first driving module, configured to operate at a first operating voltage in a first mode and configured to be deactivated in a second mode; and a second driving module, wherein at least part of the second driving module operates at a protection voltage in the first mode and operates at a second operating voltage in the second mode, wherein the second operating voltage and the protection voltage are lower than the first operating voltage.

Abstract: A bridge circuit is provided. The bridge circuit includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided.

Abstract: A liquid crystal display apparatus includes a signal generating circuit configured to generate a first control signal and a second control signal; and a differential amplifier. The differential amplifier includes: a first differential pair of transistors configured to receive a differential input signal; a first constant current source connected with said first differential pair of transistors; and a first switch connected in parallel with said first constant current source and configured to increase current which flows through said first differential pair of transistors, in response to said first control signal which is active for a first time period in a level transition of said differential input signal.

Abstract: A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signal's, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.

Abstract: A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.

Abstract: To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

Abstract: A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.

Abstract: Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

Abstract: An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.

Abstract: Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.