Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

Abstract: An intrinsically safe digital circuit has at least two output signals and at least four input signals for detecting a potential error in the circuit and/or in one of its input signals, the at least four input signals forming two input signal pairs inverted in a double-track manner, and the at least two output signals forming an output signal pair inverted in a double-track manner. The output signal pair transmits a piece of information which is identical to the one of an input signal pair, when the error is not present.

Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.

Abstract: A method for supporting a tie of a chip to an electronic apparatus includes generating once a chip-specific characteristic variable in a chip, reading out the chip-specific characteristic variable by the chip, and transmitting characteristic data representing the read-out characteristic variable of the chip to an electronic apparatus.

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device is in the error state.

Abstract: A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.

Abstract: Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes configurable resources (e.g., configurable logic resources, routing resources, memory resources, etc.) that can be grouped in conceptual configurable tiles that are arranged in several rows and columns. Some embodiments allow tiles to be individually addressed, globally addressed (i.e., all addressed together), or addressed based on their tile types. The configurable IC includes numerous user-design state elements (“UDS elements”) in some embodiments. In some embodiments, the configuration/debug network has a streaming mode that can direct various circuits in one or more configurable tiles to stream out their data during the operation of the configurable IC.

Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Abstract: A method of increasing an initial threshold voltage (Vt) of selected devices. The method includes designing devices with desired antenna effects and adjusting an increase in Vt of some devices to specific values. The desired antenna effects produce a desired threshold voltage of the devices.

Abstract: An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux.

Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.

Abstract: A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.

Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.

Abstract: A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: Some embodiments of the invention provide a system that includes a first defect tolerant configurable integrated circuit and a second IC communicatively coupled to the defect tolerant configurable first IC.

Abstract: Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract: A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyze internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and at least one further signal processing logic module.

Abstract: In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

Abstract: An integrated circuit comprises logic circuitry driven by a clock and reference circuitry. In operation, logic elements of the reference circuitry are synchronized to the clock. In operation, a first sensing circuit outputs a voltage VC proportional to an instantaneous current consumption IC of the logic circuitry, and a second sensing circuit outputs a voltage VR proportional to an instantaneous fluctuating current consumption IR of the reference circuitry. In operation, differential circuitry outputs a voltage difference ?VR?VC between a scaled-up version ?VR of the voltage VR and the voltage VC, the scaled-up version scaled to approximately the scale of the voltage VC. In operation, a square root circuit receives the voltage difference as input and outputs a square root of the voltage difference. A current source is controllable by the output of the square root circuit to generate current through a dissipative load.

Abstract: A semiconductor device includes a first transistor included in a latch circuit, a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor, and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well.

Abstract: Transition detection circuitry for detecting during multiple clock cycles, transitions occurring within a detection period in each of said multiple clock cycles at a plurality of nodes within a circuit is disclosed. The transition detection circuitry comprises: a clock signal generator for generating a detection clock signal from a clock signal clocking a sampling element within said circuit, said detection clock signal defining said detection period; a plurality of transition detectors for detecting transitions at respective ones of said plurality of nodes during said detection period, each of said plurality of transition detectors being clocked by said detection clock signal; and combining circuitry for combining said detected transitions output by said plurality of transition detectors to generate a composite transition detection signal.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract: Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.

Abstract: Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.

Abstract: Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state.

Abstract: A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.

Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.

Abstract: A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.

Abstract: A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than the high frequency of the predefined high frequency code.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.

Abstract: According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

Abstract: Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circuits are realized with SRL storage cells driving succeeding SRL storage cells directly or through combinational logic such that the corruption of any one internal state variable in the driving SRL cell and it's the associated combinational output logic can affect at most one internal state variable of the succeeding SRL cell. An SRL circuit does not allow propagation of single SEU faults.

Abstract: An asymmetrical aging control system is described. This system actively varies associated dedicated circuits in a manner that minimizes power consumption, while preventing asymmetrical aging.

Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.