Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: A digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived, for example, from a communications signal. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.

Abstract: A circuit for detecting phase includes a first inverter, a second inverter, a differential amplifier, an output load latch and an output latch. The first and second inverters receive an input signal and an inverted input signal to generate first and second differential input signals in response to a clock signal and first and second control signals, respectively, and shut off transmissions of the input signal and the inverted input signal. The differential amplifier differentially amplifies the first and second differential input signals in response to the clock signal to provide first and second differential output signals as the first and second control signals. The output load latch latches the first and second differential output signals to generate the first and second latch output signals. The output latch latches the first and second latch output signals to output a phase detection signal.

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract: A phase detector includes a first control unit and a second control unit to generate a first control pulse and a second control pulse representative of a phase difference between a reference signal and a first clock signal. The first control unit receives the reference signal and the first clock signal and generates the first control pulse. The first control pulse has a first pulse width that varies depending on the phase difference between the reference signal and the first clock signal. The second control unit receives the reference signal and a second clock signal and generates the second control pulse such that the second control pulse substantially overlaps the first control pulse and has a second pulse width that is a preset value. The second clock signal has a frequency higher than that of the first clock signal.

Abstract: A P-ECU controls an actuator which drives a shift control mechanism. An encoder signal acquisition unit acquires signals output from an encoder which detects a rotational angle of the actuator. A counter calculates a count value from the output signals of the encoder. An energization control unit controls energization to the actuator. A first phase-matching unit uses the Z-phase signal of the encoder to match the count value with energized phases so as to find a correspondence therebetween and a second phase-matching unit matches the count value with energized phases to find a correspondence therebetween without using the Z-phase signal of the encoder. If the first phase-matching unit detects an abnormality of the encoder, the second phase-matching unit subsequently performs phase matching.

Abstract: First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.

Abstract: A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1–Ck6, a delay time detection signal DT1 corresponding to a delay time 5? from the multi-phase clock Ck1 to the multi-phase clock Ck6 is generated. An Up1 signal is forcibly output to a charge pump circuit CP1 based on this delay time detection signal DT1, and the output of a Down1 signal is suppressed.

Abstract: A method for detecting a phase difference between a first input signal and a second input signal is provided. The method contains: detecting the phase difference of the first and the second input signals to produce an output signal; generating a first voltage according to a first level of the output signal; generating a second voltage according to a second level of the output signal; and comparing the first voltage and the second voltage to produce the information regarding the phase difference between the first and the second input signals.

Abstract: A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.

Abstract: The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived from a communications signal, for example. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.

Abstract: A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.

Abstract: A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component signals can be combined to provide the expected UP and DOWN phase detector output control signals. The phase detector output signals are balanced and of uniform width, minimizing oscillator control signal ripple in the clock data recovery circuit, while the linearity of the phase detector makes its output predictable.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: A phase detection system is used in particular in a Delay-Locked Loop (DLL) to generate, as a function of phase differences of different signals (1, 2, 3), at least one control signal for changing the phase delay of phase delay elements (8, 9) in order to obtain a defined phase delay between the signals (1, 2, 3). For this purpose, an up signal for increasing the phase delay and a down signal for reducing the phase delay are advantageously generated, both of which signals act on a charge pump (21) the output signal of which can be used to control the phase delay elements (8, 9). To be able to control even very small phase differences, the up signal and the down signal are generated in such a way that in the steady oscillating state they simultaneously adopt their active switching state for a certain duration during each period.

Abstract: A printed wiring board includes an input conditioner having a plurality of analog dc inputs and a plurality of analog dc outputs; a switching circuit having an analog dc output, the switching circuit being connected to the plurality of analog dc outputs of the input conditioner; a sample and hold converter having an analog dc output, the sample and hold converter being connected to the analog dc output of the switching circuit; an A/D converter having a digital output, the A/D converter being connected to the analog dc output of the sample and hold converter; a microprocessor connected to the digital output of the A/D converter; a timer circuit connected to the microprocessor; a random access memory connected to the microprocessor; and a VME interface connected to the microprocessor.

Abstract: A phase detection device with low power consumption capable of accurately detecting that an object has moved, and returning from an intermittent energized mode to an always energized mode is provided.

Abstract: A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal 3 of a multiplier circuit 62 approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

Abstract: A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The phase detector includes a series of flip flops disposed in parallel that sample the second clock signal with both a rising edge of the first clock signal and a falling edge of the first clock signal. By tracking movement in one-to-zero or zero-to-one transitions in the sampled clock signals, the phase detector is operable to determine the phase difference between the first and second clock signals.

Abstract: A clock and data recovery system acquires a clock embedded in an input data stream by detecting the occurrence of transitions in the input data stream falling into a predetermined phase zone of a sample clock used to sample the input data stream. A control circuit counts how many evaluation intervals have at least one transition in the predetermined phase zone. The control circuit determines if lock is achieved according to the count. If it is determined that lock is not achieved, an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of evaluation intervals having one or more transitions in the predetermined phase zone is below a level indicating lock.

Abstract: The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

Abstract: An on-chip high-pass filter with large time constant comprising a capacitor, a first transistor having a first terminal connected to a first voltage source and a second terminal connected to the capacitor, and a second transistor having a first terminal connected to the second terminal of the first transistor and a second terminal connected to ground, wherein the first transistor and the second transistor are for operating as a large-resistance resistor. The electrical equivalent large-resistance resistor and the capacitor together form a high-pass filter between the input port and the output port.

Abstract: In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each other, but having the same frequency as the signal from which it was derived. The other frequency signal is compared against each of the phase-related developed signals to generate an error signal which quadrature rotates when the first and second signals are out of frequency with each other. A control signal is generated when the quadrature rotation is outside a certain limit. The error signal is controllably buffered to insure that the error signal only occurs when the frequencies are offset for a selected period of time.

Abstract: A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also are connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area.

Abstract: A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Abstract: A bang-bang phase detector circuit for use in a delay lock loop is disclosed. The phase detector includes a data signal line, a clock signal line, and a delay cell having an input coupled to the data signal line. The phase detector further includes a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second double flip-flop having a data input coupled to an output of the delay cell and a clock input coupled to the clock signal line. A NOR circuit has a first input coupled to an output of the first double flip-flop and a second input coupled to an output of the second double flip-flop. The phase detector provides a lag output signal line coupled to an output of the NOR circuit, and a lead output signal line coupled to the output of the second double flip-flop.

Abstract: A phase comparator includes a phase comparison unit performing a phase comparison. The phase comparison unit carries out a switching operation according to the exclusive OR between two signals to be compared and passes or receives a current to or from an output node according to a resultant phase difference. The exclusive OR is associated with the switching operation of two transistors. Namely, when one of the two transistors is turned on, the result of the exclusive OR is L level. Accordingly, the charging/discharging time for an output signal of a logic circuit is shortened and a stable phase comparison can be performed.

Abstract: A linear phase detector includes first, second and third latches connected in series, each of the latches having a data input, a data output and a clock input, and further includes reference signal generation circuitry and error signal generation circuitry. The reference signal generation circuitry has at least a first input coupled to the data output of the second latch and a second input coupled to the data output of the third latch. The error signal generation circuitry has at least a first input coupled to the data input of the first latch and a second input coupled to the data output of the second latch, and is configured to generate an output that is indicative, relative to the reference signal, of the phase error of a clock signal.

Abstract: An apparatus for frequency and phase acquisition has a voltage-controlled oscillator and a search generator with a forward path and a backward path for generating a search signal with a search frequency, the forward path of the search generator acting as a loop filter when the frequency is locked off. The search signal is symmetrized.

Abstract: A phase comparator includes a phase comparison unit performing a phase comparison. The phase comparison unit carries out a switching operation according to the exclusive OR between two signals to be compared and passes or receives a current to or from an output node according to a resultant phase difference. The exclusive OR is associated with the switching operation of two transistors. Namely, when one of the two transistors is turned on, the result of the exclusive OR is L level. Accordingly, the charging/discharging time for an output signal of a logic circuit is shortened and a stable phase comparison can be performed.

Abstract: A circuit for phase detection includes two current sources controlled by a phase detector. One of the current sources has a reference current input that is connectable to a first or second reference current source in response to the phase detector.

Abstract: A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also be connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area.

Abstract: A digital phase detector with a master stage having imbalanced latching devices with intentional input-referred offset for determining which one of a pair of input signals is leading the other and a slave stage connected to the master stage imbalanced latching devices and which slave stage is transparent when ones of the master state imbalanced latching devices are set to a logical one and which is latched and held when the master state latching devices are reset and armed for the next phase measurement.

Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

Abstract: A phase detection device with low power consumption capable of accurately detecting that an object has moved, and returning from an intermittent energized mode to an always energized mode is provided.

Abstract: A label printer-cutter includes a frame and a print head assembly connected to the frame. The print head assembly includes a print head for printing to a label media. The label printer-cutter includes a cutting assembly connected to the frame, and the cutting assembly is for catting the label media. The printer-cutter also includes a controller in operative association with the print head assembly and cutting assembly. The controller can be programmed to control the print head assembly and the cutting assembly such that printing to and cutting of the label media does not occur simultaneously in the label printer-cutter. Printing by the print head is controlled to correspond to cutting assembly rollers being positioned in a non-cutting position. Advantageously, printing to and cutting of a label media in a single label printer-cutter unit is accomplished in an efficient and cost-effective manner.

Abstract: A system for determining the instantaneous amplitude (a) and phase (&phgr;) of an analog sinusoid includes a sensor which produces the analog sinusoid output in response to the measurement of a parameter, an analog-to-digital converter which receives the analog sinusoid from the sensor and converts the analog sinusoid to a digital sinusoid, a delay device which receives the digital sinusoid and produces an in-phase signal (I) associated with the digital sinusoid, a transformer which receives the digital sinusoid and produces a quadrature signal (Q) associated with the digital sinusoid by introducing a phase shift plus a delay to the digital sinusoid, an amplitude computation device which receives the in-phase (I) and quadrature (Q) signals and computes the instantaneous amplitude (a) of the digital sinusoid by processing the in-phase (I) and quadrature (Q) signals according to the equation a={square root}{square root over ((Q2+I2))} and a phase computation device which receives the in-phase (I) an

Abstract: In an apparatus and a method for detecting a phase state capable of improving reliability of an air conditioner by preventing an abnormal operation of the air conditioner by detecting a phase state (antiphase and open-phase) of three phase AC power supplied to the air conditioner and displaying the detected phase state, the apparatus includes a phase detector for detecting first, second and third phases of a three phase current; an interrupt detector for detecting a falling edge of a pulse signal corresponded to the third phase of the detected first, second and third phases, recognizing an interrupt occurrence by the third phase when the falling edge is detected and generating a counting signal; a counter for counting a pulse signal corresponded to the first and second phases on the basis of the interrupt occurred-third phase according to the counting signal; an antiphase/open-phase detector for detecting a state as a normal connection state, an antiphase state on the basis of a pulse signal corresponded to t

Abstract: A device for transforming a periodic input signal into an output signal of distinct frequency, comprising two adjustable delay means receiving the input signal, a multiplexer selecting the output signal of one or the other of the delay means, control means for, according to whether the output signal frequency must be smaller or greater than the input signal frequency, increasing or decreasing at the rate of the input signal, or at a multiple of this rate, the delay of the selected delay means, and controlling a minimum or maximum delay for the delay means which has not been selected, and a phase comparator adapted to changing the multiplexer selection when the transitions of the signals output by the delay means corresponding to a same transition of the input signal are offset by a duration greater than or equal to one period of the input signal.

Abstract: A phase adjusting circuit for a semiconductor memory includes a D/A converter 20 which includes a D/A converting circuit 31 receiving code signals A1 to An, and a current mirror circuit 32 having an input transistor P1 connected to an output node S of the D/A converting circuit 31 and an output transistor P2 for supplying an output current lout. A switch circuit 34 is connected between a gate of the input transistor P1 and a gate of an output transistor P2, and a capacitor 36 is connected to the gate of an output transistor P2. The switch circuit 34 is turned off before the code signals A1 to An applied to the D/A converting circuit 31 change, and after a fluctuation of the potential on the output node S of the D/A converting circuit 31 has been settled, the switch circuit 34 is turned on, with the result that a hazard occurring in the D/A converting circuit 31 is prevented from being transferred to the current mirror circuit 32.

Abstract: A phase detector has a reference signal input for a reference signal and a detector input for a signal to be evaluated. A memory unit is connected to the detector input and stores a state of the signal to be evaluated at a storage instant. An evaluation unit is connected downstream of the storage unit and is designed in such a way that it can be used to compare the stored state of the signal with the state of the reference signal at an evaluation instant and to generate an evaluation result signal therefrom. The phase detector has a control unit for prescribing the storage instant and the evaluation instant, the control unit prescribing the storage instant first and then the evaluation instant. A detector output is connected to the evaluation unit and the evaluation result signal can be tapped off at the detector output.

Abstract: Phase detector constructed from a plurality of multi-input gates which combine combinations of unretimed input data with retimed data and with clock signals to achieve output pulses proportional to the phase difference between the unretimed data and the clock. In the embodiment the phase detector comprises an input for receiving data signals; an input for receiving clock signals; an output for providing phase control signals; data retiming circuitry for accepting unretimed data signals from said data input and for providing even and odd retimed signals therefrom; a plurality of multi-input gates having inputs connected to different combinations of said unretimed data signals, said retimed data signals, and said clock signals, such that no said gate can be active in two consecutive UIs, when a UI is defined as the length of time allocated to a single bit; and a combiner for mixing the outputs of at least two of said gates.

Abstract: A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

Abstract: A method and an apparatus are described for recovering a payload signal from an FSK signal that has been modulated by frequency shift keying. From the modulated signal a discrete-time series of sampled values are determined for which the phase difference relative to a preceding sampled value is respectively determined as well. The method and the apparatus can be used in a digital PBX to which the modulated signal is fed via an analog telephone network.

Abstract: A phase comparator has a flip-flop circuit and a logic circuit. The flip-flop circuit compares an input clock signal with a leading edge and a trailing edge of an input data signal to produce a leading phase comparison result signal indicative of a leading phase comparison result related to the leading edge of the input data signal and a trailing phase comparison result signal indicative of a trailing phase comparison result related to the trailing edge of the input data signal. The logic circuit produces an output up signal when both of the leading and the trailing phase comparison result signals indicate a lag phase of the input clock signal. The logic circuit produces an output down signal when both of the leading and the trailing phase comparison result signals indicate a lead phase of the input clock signal.

Abstract: A digital phase detector with a master stage having imbalanced latching devices with intentional input-referred offset for determining which one of a pair of input signals is leading the other and a slave stage connected to the master stage imbalanced latching devices and which slave stage is transparent when ones of the master state imbalanced latching devices are set to a logical one and which is latched and held when the master state latching devices are reset and armed for the next phase measurement.

Abstract: An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.

Abstract: A frequency comparator detects the phase of a data signal DATA by using four-phase clocks ICLK, /ICLK, QCLK and /QCLK as a reference and detects a change in the phase. A counting processing unit counts a period in which a control signal UP2 or DN2 is activated within a predetermined period, and outputs an overflow detection signal LOL2 if the frequency is high. A hysteresis generating unit changes a signal LOL to the L level only after signal LOL goes low X times consecutively. On the other hand, after signal LOL is set to the L level once, the hysteresis generating unit changes signal LOL to the H level only after signal LOL2 goes high X times consecutively. With such a configuration, a phase-locked state detecting circuit with reduced malfunction even when a data signal having larger jitter is input can be provided.