Abstract: A phase detection system is used in particular in a Delay-Locked Loop (DLL) to generate, as a function of phase differences of different signals (1, 2, 3), at least one control signal for changing the phase delay of phase delay elements (8, 9) in order to obtain a defined phase delay between the signals (1, 2, 3). For this purpose, an up signal for increasing the phase delay and a down signal for reducing the phase delay are advantageously generated, both of which signals act on a charge pump (21) the output signal of which can be used to control the phase delay elements (8, 9). To be able to control even very small phase differences, the up signal and the down signal are generated in such a way that in the steady oscillating state they simultaneously adopt their active switching state for a certain duration during each period.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A driver circuit that allows high-speed switching when the reference current (I) is small. The driver circuit includes a drive current generation circuit (220) for supplying to a first node (232) a drive current based on a binary data signal (DATA); a current mirror circuit (240) for conducting through a second node (234) a current (mI) having a magnitude of the current flowing through the first node (232), multiplied by a predetermined current mirror ratio (m); and a pre-bias circuit (260) for supplying a first pre-bias current (Ib1) to the first node (232) and supplying a second pre-bias current (Ib2) having a magnitude of the first pre-bias current (Ib1), multiplied by said current mirror ratio (m), to the second node (234).

Abstract: To provide a phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and have a high linearity of a phase to voltage conversion characteristic around phase-locked point in an operation of comparing phases of random NRZ signals in a phase.

Abstract: A phase comparator which eliminates jitter in a clock signal extracted in a phase locked loop. The phase comparator includes: a flip-flop circuit which inputs input data and the clock signal and stores the input data in response to the clock signal; a delay circuit which inputs the input data and delays the input data by a predetermined angle of 0° through 180°; a first logic gate which inputs the input data and an output signal of the flip-flop circuit and which outputs an output signal by taking an exclusive OR or exclusive NOR thereof; and a second logic gate which inputs the data and the output signal of the delay circuit and which outputs an output signal by taking an exclusive OR or exclusive NOR thereof.

Abstract: Phase detection circuitry is disclosed that can detect phase differences from a quadrature phase relationship, without requiring extensive additional circuitry for driving and correcting the phase detection circuitry. The phase detection circuitry can measure plural or multiple pulse durations consecutively, without interruption to reset the circuit or store the values generated by the circuit, affording a much higher sampling rate and sampling a higher proportion of pulses than is conventional. Averaging of the phase data samples is also provided by measuring multiple pulses, so that phase changes are not instigated based upon a signal from an individual pulse duration that may differ significantly from the average. In addition to detecting quadrature phase relationships, the phase detection circuitry can be adjusted to compensate for a desired offset in one of the signals from quadrature, or can be set to detect other phase relationships.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A phase detector is disclosed that detects the phase of two inputs with precision. A method and apparatus of phase detecting that subtracts out common errors due to temperature variations and supply voltage fluctuations. The phase detector and method preferably utilize digital circuitry such as exclusive OR gates and differential amplifiers to perform the accurate phase detection. The inputs and outputs may be attenuated or filtered to produce the desired results.

Abstract: A phase detector including a voltage controlled oscillator generating a voltage controlled oscillator output, and a first logic state device for receiving said voltage controlled oscillator output as an input. The phase detector also includes a reset device, for generating a reset signal to reset the first logic state device such that the output control signal of the first logic state device reaches a low level in response to a first edge of the reset signal.

Abstract: The present invention provides a transceiver which does not lose synchronization upon a transition from a non-precoded communication mode to a precoded communication mode and minimizes phase drift. A transceiver unit outputs a signal representing the phase of a received signal, and that possesses a controllable sampling rate. The transceiver is coupled to a phase reference selector and a timing control system. Upon a transition between communication modes, an adaptation period is initiated. The phase reference selector captures the phase estimate immediately prior to termination of the adaptation period, outputting a predetermined phase reference until such termination, at which point the stored phase estimate is outputted. The timing control system minimizes the difference between the phase estimate and the output of the phase reference selector by altering the sampling rate, except during the adaptation period, during which the sampling rate is held constant.

Abstract: A stabilizing circuit for stabilizing a horizontal transistor of a video display device. The stabilizing circuit includes a transient state detector for detecting a transient state of a phase locked loop circuit in a horizontal drive circuit due to a change in an operation mode of a video card in a computer system. A micro-computer outputs vertical and horizontal synchronous signals with frequencies before the change in the operation mode of the video card when the transient state detector detects the transient state of the phase locked loop circuit. The transient state detector detects the transient state of the phase locked loop circuit according to a direct current level variation based on a phase difference between a horizontal synchronous signal from the micro-computer and a horizontal drive signal from the phase locked loop circuit.

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data.

Abstract: An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.

Abstract: A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.

Abstract: The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.

Abstract: Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test T.sub.setup and T.sub.hold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.

Abstract: The invention relates to a phase detector, especially for a Phase Locked Loop of a desynchronizer of a digital transmission system for the transmission of signals of the synchronous digital hierarchy with a difference former (subtractor) connected to a comparator, to which can be conducted at the input side, via a first accumulator, a first input signal, and via a second accumulator a second input signal with the comparator being connected at the output side via a coder to a control input of the second accumulator.

Abstract: A shared path phase detector circuit for receiving a reference clock and an oscillator clock, the phase detector circuit providing an output signal for indicating a magnitude difference between a phase of the reference and oscillator clocks. The output signal is independently derived from the leading or lagging edge relationship of the reference and oscillator clocks. The output signal does not describe which signal leads, but only the width magnitude difference. The design provides a single path over which the output signal travels, without feedback, such that the circuit dependencies are greatly reduced.

Abstract: A phase comparator apparatus compares a first input signal and a second input signal to output first or second compare output signal. The apparatus includes a detector circuit and a compare output generator circuit. The detector circuit detects the phase difference between the first and second signals to output a detection signal. The compare output generator circuit determines the phase deviation between the first and second input signals using the detection signal and the second input signal. The compare output generator circuit outputs the first compare output signal when the second input signal lags behind the first input signal and outputs the second compare output signal when the second input signal leads the first input signal.

Abstract: A digital phase measuring system and method for measuring the phase difference between two signals including generating quadrature clock signals for a first reference signal, converting a second measured signal from analog to digital form by sampling the second measured signal using the quadrature clock signals to produce quadrature cartesian samples of the measured signal, and converting the quadrature cartesian samples to polar coordinates to define the polar phase coordinate representative of the phase difference between the two signals.

Abstract: A phase detector circuit includes a first flip flop, a second flip flop, a first charge pump and a second charge pump. Outputs of the flip flops directly enable the charge pumps in response to received clocking signals. A first delay circuit delays the output signal from the first flip flop to an AND gate which combines the delayed output signal and the output signal from the second flip flop. The AND gate output is delayed in a second delay circuit to produce a delayed reset signal which resets both flip flops simultaneously and disables the charge pumps. The phase detector circuit balances the amount of charge provided to a phase locked loop near the in-phase condition to improve linearization of the phase detector.

Abstract: A clock phase detecting circuit is provided which is arranged in a receiving section of a multiplex radio apparatus. Difference detecting unit detects the difference between input and output signals to and from an equalizing circuit, and squaring unit squares the detected difference. The squared value thus obtained shows a minimum value when the phase of a clock signal output from a clock regenerating circuit coincides with a normal position of signal point. Therefore, phase adjusting unit outputs a control signal to the clock regenerating circuit while monitoring the squared value, to adjust the phase of the clock signal output from the clock regenerating circuit so that the squared value output from the squaring unit may be minimized.

Abstract: An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates a second output if the phase relation between the plurality of clock signals has changed before the adjusting of the delay of the clock signals has occurred. A noise band circuit is configured to receive the second output of the controller and adjust the predefined range in response to the receiving of the second output.

Abstract: A semiconductor integrated circuit has a de-skew circuit for reducing a skew of an incoming signal from a specific circuit with respect to a synchronous clock signal. The de-skew circuit controls the phase of an outgoing signal to be transmitted from the semiconductor integrated circuit to the specific circuit in response to the skew of the input signal. This arrangement decreases not only a skew of incoming signals from the specific circuit but also a skew of outgoing signals to the specific circuit.

Abstract: An asynchronous digital phase detector. The digital phase detector includes an asynchronous state machine which simulates an edge triggered J-K flip flop. Additionally, the digital phase detector includes a reset line. The asynchronous state machine is implemented with logic which provides for optimal phase detector sensitivity and minimal dead zone. The logic within the digital phase detector is implemented with pass-transistors. The channel widths of the pass-transistors are selectively widened or narrowed to further increase the sensitivity of the phase detector.

Abstract: A low-cost microstrip phase detector that is photo-etched onto a circuit board is disclosed. The phase detector is used to detect the phase difference between two high-power radio frequency (RF) signals. One RF signal enters a delay line causing the signal to experience a 180.degree. phase shift. The other RF signal is not phase shifted. Both RF signals are then input into a Wilkinson combiner circuit. The structure of the Wilkinson combiner is such that there is no voltage output from the combiner when the two input signals are exactly 180.degree. out of phase. When the original signals (before the delay line) are in-phase, there is no voltage output from the combiner. However, when the original signals are out-of-phase to begin with, they do not enter the Wilkinson combiner with a 180.degree. phase difference. Instead, the phase difference is greater than or less than 180.degree., depending on whether one input signal leads or lags the other input signal.

Abstract: The sampling phase detector whose output signal (fd) has a very broad-band and a very even frequency response characteristic includes a step-recovery-diode (SRD) to which a series circuit including at least two diodes (D1,D2) is connected in parallel by means of coupling capacitors (Ck1,Ck2). An input signal is fed to the diodes (D1,D2) by means of an R/C-network (R1,R2,C3,C4) and an output signal (fd) is taken off, which corresponds to the phase shift between an input signal (fo) and a reference signal (fr). The reference signal (fr) is fed to the step-recovery-diode (SRD) via a balancing transformer (Tr). Decoupling resistors (Rs1,Rs2) are included in the connecting lines from the balancing transformer (Tr) to the step-recovery-diode (SRD), which damp interfering resonances or reflections of the balancing transformer.

Abstract: A computer controllable testing and monitoring station forms short-term intervals of simulated alternating current power level disturbance, either undervoltage (sag) or overvoltage (swell). The station forms the short term voltage sags or swells so that their effects on sensitive equipment can be measured. The starting point of the sag or swell disturbance, as well as the time duration of the disturbance, can be accurately controlled.

Abstract: A symmetric capture range is produced in a two-quadrant phase detector phase locked loop that utilizes nonsymmetric pulse waves. The phase detector is enabled only during VCO pulses. A latch stores the relative relationship between the leading edge of the input pulse and the center of the VCO pulse in the previous cycle. If the phase angle .theta. form the VCO pulse center to the leading edge of the input pulse is0 deg<.theta.<180 deg,then the phase detector incrementally decreases the VCO frequency at the next VCO pulse. If the phase angle .theta. is180 deg<.theta.<360 deg,then the phase detector incrementally increases the VCO frequency at the next VCO pulse.

Abstract: A signal sampling circuit receives a clock signal indicative of a sampling rate and a periodic input signal to produce a digitized sampled output signal. The sampled signal is applied to an all-pass filter having a single pole/zero pair in which the pole/zero values are determined by a number supplied by a number generator. The number generator varies the applied number in a random or pseudorandom fashion to create a correspondingly random or pseudorandom variation of the transfer function of the filter. The filtered sample signal is then further processed by an absolute value operator and an average value operator for application to an amplitude responsive device such as a meter. The random or pseudorandom variation of the filter transfer function introduces a corresponding random or pseudorandom variation of the phase shift imposed upon the sampled signal within the filter. This.

Abstract: A system for determining the time between the receipt of two different sils, includes a voltage ramp generator which generates a time dependent voltage signal upon receipt of a timing pulse at a time T.sub.1, and provides the instantaneous value of the voltage signal when the voltage ramp generator receives an input signal having a predetermined threshold value at time T.sub.2. A data processor coupled to receive the voltage signal, generates the timing pulse, and determines a time difference .DELTA.T from the voltage signal, where .DELTA.T=T.sub.2 -T.sub.1.

Abstract: A phase comparator has a first comparing circuit and a second comparing circuit. The first comparing circuit produces a first output pulse having a duration equal to a phase lead of a first input signal with respect to a phase of a second input signal. The first phase comparator also produces a second output pulse equal in duration to a phase lag of the first input signal with respect to the phase of the second input signal. The second comparing circuit produces a third pulse equal in duration to a phase lead of a third input signal with respect to a phase of a fourth input signal. The second comparator also produces a fourth output pulse equal in duration to a phase lag of the third input signal with respect to the phase of the fourth input signal.

Abstract: A phase detector biased in a manner to alleviate the mismatch between the biasing current sources and the phase detector core bias currents. The bias setting resistors are coupled together at a common node that forms the negative input of a differential feedback amplifier. The positive input to the amplifier is referenced to a reference voltage, and the output of the amplifier controls the biasing current sources. The feedback amplifier forces the average voltage at the current source outputs to approximately match the reference voltage applied to its positive input. Thus the average bias current from the bias current sources is forced to track the average bias currents of the phase detector core.

Abstract: Methods and apparatus for switching a load between first and second sources is shown to include first and second solid state switches connected to the load. First and second mechanical breakers are connected between the switches and the sources so that each source is connected to the load through a circuit breaker and solid state switch. A controller is connected to sense the voltage from the first and second sources. The controller is connected to the first and second switches and the first and second mechanical breakers. The controller senses the phase difference between the voltages from the first and second sources. The controller causes the first and second mechanical breakers to open and close in response to sensing the phase difference between the sources. The first and second mechanical breakers can include medium voltage vacuum breakers.

Abstract: A device for determining the phase difference between a first and a second digital input signal (S1, S2) is disclosed. In a first embodiment, a clock signal (CLOCK) is supplied as a first counting signal (18) to a first counter (16), which is reset by the appearance of a predetermined edge (31) of the first input signal (S1). This embodiment permits phase measurement values in the range between zero and 360.degree. to be generated at a high measurement rate. In second and third embodiments, which are preferably connected and, if desired, combined with the first embodiment, second and third switching signals (FORWARD, BACK) are generated from the digital input signals (S1, S2) and are supplied to a forward-backward counter (20). The second and third embodiments are suited for determining phase differences between the two digital input signals (S1, S2) which are multiples of 360.degree..

Abstract: A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.

Abstract: An oscilloscope has a trigger circuit which is operable in any one of three different modes. The trigger circuit has a number of edge detect circuits which generate pulses in response to a rising edge, falling edge, or both rising and falling edges of one or more signals. The trigger circuit has a multiplexer which routes one of three signal sources depending upon the selected mode. With a first mode, the multiplexer routes signals from a pattern detect circuit and the trigger circuit operates in a conventional manner to trigger based on the duration of the signal. In the second mode, the multiplexer routes signals from one edge detect circuit and the trigger circuit measures the frequency or rate of the signal. In the third mode, the multiplexer routes signals from a flip-flop which generates a pulse based upon the outputs from two different edge detect circuits and can be configured to measure setup or hold violations between two signals.

Abstract: A method of measuring a delay time in a semiconductor device which has a particular circuit subject to delay time measurement, a test circuit coupled to an input terminal of the particular circuit for bypassing the particular circuit, and a selector for selectively outputting either an output signal from the particular circuit or an output signal from the test circuit.

Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

Abstract: A frequency difference detection apparatus includes a first PLL, a second PLL, a first phase difference detection unit, a second phase difference detection unit, a phase difference processing unit, and a frequency difference detection unit. The first PLL detects a phase difference between an input clock and an output clock in response to the input clock and performs control to gradually suppress the detected phase difference to zero. The second PLL detects a phase difference between the input clock and an output clock in response to the input clock and performs control to suppress the detected phase difference to zero at a speed higher than that of the first PLL. The first phase difference detection unit detects a phase difference between the input clock and the output clock from the first PLL. The second phase difference detection unit detects a phase difference between the input clock and the output clock from the second PLL.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the center between each pair of consecutive edges. For example, the center between each pair of consecutive edges is determined by counting a number of cycles of an over sampling signal which occurs between each pair of consecutive edges to obtain a bit width. The bit width is divided in half and the result added to an edge phase value to obtain a value for the center. Also, the phase of the extracted clock signal may be varied based on the center between each pair of consecutive edges as follows. An amount a plurality of centers varies from a center of the extracted clock signal is averaged to produce a phase error.

Abstract: A small and efficient control circuit for a compensated CMOS off-chip driver and a driver circuit incorporating the control circuit. The control circuit uses an exclusive OR gate as a phase detector to determine the phase difference between a system clock and a delayed version of the system clock. An RC filter smooths the output of the exclusive OR gate to produce a voltage proportional to the delay introduced in the CMOS circuitry by environmental and process variables. The voltage from the RC filter is used as a control voltage to control the effective channel width of the effective pull-down device of the off-chip driver circuit. An off-chip driver using the control circuit is used in the I/O unit of a CMOS integrated circuit chip.

Abstract: A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.

Abstract: An on-chip digital servo scheme for providing continuous calibration of integrated circuit on-chip time delay devices to provide real-time regulation against various parameter or environmental changes, such as processing, temperature and power supply variations. The techniques are particularly useful for semiconductor delay lines comprised of a selectable number of identical unit delay circuits having the same propagation time. This scheme constantly monitors the delay changes in the unit delay elements and calibrates the delay line by comparing the delay against a stable, crystal controlled reference clock period to determine, in each instance, how many unit delay elements in the delay line is needed to effectively delay the amount of time to equal the reference clock period. A real time digital pointer number is generated and updated while the device is in operation.

Abstract: A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.

Abstract: A phase detector circuit (10) for generating an analog signal (VR) dependent upon the phase difference between two digital signals (VE, VA) includes two NOR circuits (20, 27) to the inputs (18, 26; 28, 24) of which the two digital signals are supplied on the one hand delayed and negated and on the other directly. The output signals of the NOR circuits (20, 27) control two current sources (S1, S2), one of which in the activated state furnishes a constant charge current (I1) for a storage capacitor (C) whilst the other of which leads a constant discharge current (I2) of equal magnitude away from said storage capacitor (C). The charge voltage at said storage capacitor (C) is an analog signal (VR) which represents a measure of the phase deviation between the digital signals (VE, VA).

Abstract: A detector for determining the phase of high AC voltages comprises two inputs for connecting to respective probes which contact the conductors to be tested, a rectifier circuit to which the inputs are connected, a chain of capacitors arranged to be charged in series from the output of the rectifier circuit, an operational amplifier configured as a trip amplifier for providing an output signal when the output voltage of the rectifier exceeds a predetermined value, and a transistor for discharging the capacitors in parallel through a buzzer and a chain of light emitting diodes when the output signal is provided.

Abstract: A phase-locked-loop (PLL) with stable phase discrimination includes a charge pump with a current source and current sink to control a VCO, and a phase discriminator to compare the VCO's signal to a stable reference signal for controlling the charge pump. The phase discriminator includes a resettable D-flipflop to provide the current source control signal and a resettable D-flipflop to provide the current sink control signal. The reset signal keeps both sink and source temporarily alive to avoid a dead zone region. The reset signal is produced under the combined control of the sink and source control signals and, in addition, of the reference signal to enhance stability.