Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

Abstract: A phase detection circuit determines phase difference between a periodic signal and a reference signal of substantially equal frequency. The circuit includes: a source input receiving the periodic signal; a feedback signal generator providing a feedback signal (PFB) with substantially the same frequency as the reference signal; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, determining an error signal from phase difference between the periodic signal and PFB; an integrator circuit integrating the error signal into an integration signal; and a digitizing circuit digitizing the integration signal. The feedback signal generator is coupled to the digitizing circuit, providing PFB based on the digitized integration signal, and selecting the phase of PFB from a number of fixed phases. The phase detection circuit generates a time-average of the phase of PFB selected from the plurality of fixed phases.

Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

Abstract: A sampling circuit and a receiver with relatively simple configuration and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits (102-1 to 102-4), charging switch (1021) is controlled on and off using one of four-phase control signals. Rotate capacitor (1022) shares electrical charge accumulated in IQ generating circuit (101) via charging switch (1021). Dump switch (1023) is controlled on and off using a different signal from the control signal used to control charging switch (1021) on and off, among the four-phase control signals. Buffer capacitor (1026) shares electrical charge with rotate capacitor (1022) via dump switch (1023) to form an output value.

Abstract: A translation circuit for mediating between a fiber-optic controller chip and a host device. The translation circuit may be on a fiber-optic transponder. The controller chip includes a phase locked loop that outputs a short synchronization signal when a hunting frequency passes through a target data signal frequency while hunting for a data signal and outputs a synchronization signal when the phase locked loop is locked onto a data signal. The translation circuit distinguishes between the synchronization signals and generates a lock signal when the phase locked loop is locked onto a data signal, but does not when the hunting frequency passes through the target data signal frequency. The lock signal may be used by a host device into which the fiber-optic transponder has been in installed. Errors from misinterpreted signals can thus be mitigated.

Abstract: A basic symmetric ?/2 phase-detector receives four control signals that control a differential current at the detector's output. Each respective control signal is a linear combination of a respective pair of signals chosen from a first input signal, its logic complement, a second input signal and the logic complement of the latter. Operation is based on time-averaging the differential current, the result being zero at a phase difference of ?/2. By means of adding one or more additional current sources to the output, controlled by one or more of the control signals, the basic operation is skewed. The time-averaged output current is now made zero only at a value of the phase difference different from ?/2.

Abstract: A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power than conventional comparator circuits having binary adders. For some embodiments, the comparator circuit is capable of performing full comparison operations on two or more arbitrary binary values. The comparator circuit can be implemented in TCAM devices to perform regular expression search operations.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract: There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: An apparatus and method for detecting a phase difference between an input signal and a reference signal in an all-digital phase locked loop (PLL) are provided. In a preferred embodiment, an N-stage tapped delay line and N-bit parallel latch are used to create a snapshot of the input signal by latching the output of the tapped delay line using the reference signal to clock the latch. An edge detector and encoder circuit translate the latched snapshot into a numerical phase difference value. A difference between this phase difference value and a desired phase difference is calculated and then added to an accumulator. The result in the accumulator is a numerical phase error value that can be fed to a numerically controlled oscillator (NCO). The output of the NCO can, in turn, be fed back into the phase/frequency comparator as the input signal, thus forming a fully-digital PLL.

Abstract: A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

Abstract: A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information.

Abstract: A phase detecting module capable of optimizing detection accuracy and noise robustness, and a detecting method, are included. The phase detecting module includes a phase detecting circuit, an energy estimating circuit and a selecting circuit. The phase detecting circuit detects a phase of an input signal to generate a phase detection value. The energy estimating circuit estimates energy of the input signal to generate an energy estimation value. The selecting circuit selectively outputs the phase detection value according to the energy estimation value.

Abstract: A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.

Abstract: There is provided a phase detection apparatus that can accurately detect a phase difference between an input signal and a reference signal even when the input signal and the reference signal have different duty cycles. A phase detection apparatus according to an aspect of the invention may include: a pulse generation unit generating a first pulse signal on an edge of an input pulse signal, and a second pulse signal based on an edge of a reference pulse signal having a predetermined phase; and a detection unit detecting a phase difference between the first pulse signal and the second pulse signal from the pulse generation unit.

Abstract: In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.

Abstract: The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for removing network-induced clock jitter and wander that occurs in a transport network during asynchronous mapping techniques, bit and/or byte-stuffing techniques, or traditional pointer adjustment schemes associated with traditional PDH (pleisiosynchronous digital hierarchy), SDH (synchronous digital hierarchy), and packet-based networks. The timing recovery circuit may be implemented in a logic circuit such as programmable, digital FPGA (field programmable gate array) logic, or alternatively in standard cell or gate-array ASIC (application-specific integrated circuit) technology, or like logic circuit design.

Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

Abstract: Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector comprises a first logic circuit for (i) sampling the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, and (ii) generating one or more error signals indicating a phase difference between the clock signal and the reference signal; and a second logic circuit for (i) sampling the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and (ii) generating one or more error signals indicating a phase difference between the clock signal and the reference signal.

Abstract: Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection signal by detecting a frequency of the external clock in response to the control signal, a decoder for outputting a selection signal by decoding the detection signal, and a delay unit for outputting a second clock by delaying the first clock or inverting and delaying a phase of the first clock in response to the selection signal.

Abstract: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

Abstract: An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.

Abstract: A phase detecting module capable of optimizing detection accuracy and noise robustness, and a detecting method, are included. The phase detecting module includes a phase detecting circuit, an energy estimating circuit and a selecting circuit. The phase detecting circuit detects a phase of an input signal to generate a phase detection value. The energy estimating circuit estimates energy of the input signal to generate an energy estimation value. The selecting circuit selectively outputs the phase detection value according to the energy estimation value.

Abstract: A method and device may determine the absence of a periodic signal or the absence of an edge of the periodic signal. The periodic signal may be a transmitted clock signal in a forwarded clock architecture. The periodic signal may be delayed by a fixed phase difference to produce a delayed periodic signal. The phase difference between the periodic signal and the delayed periodic signal may be determined. If the determined phase difference is above or below the fixed phase difference by a predetermined amount or more the periodic signal may be missing an edge. If the absence of the periodic signal or the absence of the edge of the periodic signal is detected, an error signal may be asserted. The error signal may be an in-band reset signal.

Abstract: A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.

Abstract: A method for comparing phases of two signals including placing a first output node in a floating state, detecting a first edge of a first signal on a first input node after placing the first output node in the floating state, coupling the first edge of the first signal to the first output node and resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node. A system for comparing phases of two signals can also be included.

Abstract: A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results. A memory control circuit is provided.

Abstract: In various embodiments, a phase current sampling apparatus (300, 600, FIGS. 3, 6), an electric motor drive system (100, FIG. 1), and a motor vehicle (1200, FIG. 12) include switching circuitry adapted to receive first and second phase current waveforms. The switching circuitry provides the first phase current waveform during at least two offset sampling instants, and provides the second phase current waveform during a reference sampling instant. An analog-to-digital converter is adapted to sample the first phase current waveform at the offset sampling instants, and to sample the second phase current waveform at the reference sampling instant. An embodiment of a method for regulating phase current waveforms includes an analog-to-digital converter generating samples of a first phase current waveform at sampling instants that occur before and after a reference sampling instant, and generating a sample of a second phase current waveform at the reference sampling instant.

Abstract: A PLL and DLL are designed such that the power consumption can be reduced, the size can be easily reduced, the band of the locked loop can be a higher one, and the reliability can be improved. There are provided a phase comparator for measuring a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing the number of bits representing “H” in a control signal when the phase signal represents the lead or decreasing the number of bits representing “H” in the control signal when the phase signal represents the lag, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” increases or decreasing the oscillation period when the number of bits representing “H” decreases.

Abstract: A PLL and DLL are designed such that the power consumption is reduced, the size is reduced, the band width of the locked loop is increased, and the reliability is improved. There are provided a phase comparator for measuring the value of a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing by one the number of bits representing “H” in a control signal when the phase signal represents the lead of the phase or decreasing by one the number of bits representing “H” in the control signal when the phase signal represents the lag of the phase, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” in the control signal increases or decreasing the oscillation period when the number of bits representing “H” decreases.

Abstract: A method, circuit, and computer program product for receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is at least partially based upon a second reference signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. A first anticipated differential change in the output signal is determined, the first anticipated differential change to occur based upon a transition in the first reference signal. A second anticipated differential change in the output signal is determined, the second anticipated differential change to occur based upon a transition in the second reference signal. A first realized differential change in the output signal is measured, the first realized differential change occurring based upon a transition in the first reference signal.

Abstract: A phase discriminator for being used in a phase-locked loop to determine if a phase difference between a reference signal and a target signal has reached a programmable gap value is disclose which comprises a programmable phase gap selector receiving the reference signal, a first phase digital converter converting an output signal from the programmable phase gap selector to a first digital code, a second phase digital converter converting a phase difference between the target signal and the reference signal to a second digital code, and a code comparator comparing the first and second digital code and generating a first instructional signal based on a change of order of the values of the first and second digital code.

Abstract: The present invention relates to an apparatus for accurately detecting a mains phase. The apparatus is constructed with a zero-crossing detector, a digital phase detector, a digital loop filter, and a digital controlled oscillator (DCO) of a direct digital synthesized (DDS) manner. The present apparatus employs an all-digital loop architecture and a high sampling clock to recover a signal with a phase orthogonal with the mains signal and a frequency the same as the mains signal. And jitters in the recovered signal are less than 10 us. The present apparatus is capable of implementing signal tracking of a zero frequency error and a zero phase in a wide range, and can provide a detection result of excellent performance for the power line carrier communication, mains frequency detection, etc.

Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract: A phase/frequency comparator is described which includes two edge-triggered storage elements, each set by an edge of a reference frequency signal of a phase—or frequency-locked loop (PLL) and by an edge of an output frequency signal of the PLL. The storage elements are each reset by an output signal of a resetting logic unit, which is activated when both output signals of the storage elements are activated and then deactivated when the output signals are deactivated.

Abstract: A phase detection method for detecting a phase difference between a data strobe signal and a clock signal, includes: latching the clock signal according to the data strobe signal to generate a phase lead/lag detection result; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal according to the delayed data strobe signals to generate a plurality of phase detection results corresponding to the delayed data strobe signals, respectively; and if the phase lead/lag detection result indicates that the data strobe signal leads the clock signal, utilizing the phase detection results to represent the phase difference between the data strobe signal and the clock signal. A memory control method and a memory control circuit respectively corresponding to the phase detection method are further provided.

Abstract: A phase-controlled current source for phase-locked loop is provided. The phase-locked loop includes a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal. The phase-controlled current source includes a status memory receiving the loop signal and the reference signal so as to output an energy-triggering/energy-removing signal; and a controllable current source, under the control by energy-triggering/energy-removing signal so as to decide whether a charging and discharging action should be performed, wherein after the charging action or discharging action is decided, the charging path or the discharging path is generated through the reference signal and the loop signal.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a phase error detected in response to a received output signal and a reference signal. The control signal is coupled to the frequency control input of said voltage controlled oscillator. The phase comparator includes a first and a second predefined phase step value to a first accumulated phase value, and the phase comparator has means for determining the phase error. The phase comparator may further have circuit means for performing a first and a second AND operation on the outputs from the first and second accumulators and for obtaining analogue signals corresponding to the outputs of the AND operations. The invention also relates to a method for obtaining information on a phase error between two signals.

Abstract: A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in response to unassertion of the first signal. The phase detector may include combinatorial logic gates, thereby to generate the third and fourth signals in response to logic levels of the first and second signals. The phase detector may include sequential logic gates, thereby to generate the third and fourth signals in response to transitions of the first and second signals.

Abstract: A phase detector detects a phase difference between a first and second signal received by a phase detector. A charge is supplied by a charge pump circuit that corresponds to the phase difference using a phase difference to charge conversion that is substantially linear and nonzero in a phase error region that includes a phase error transition region around a phase error of zero having both negative and positive phase error values. Dual determinations, q1 and q2, offset from each other are made of an appropriate charge for a given phase error between the first and second signals. The charge pump supplies as the total charge pump output a charge value representing a combination of q1 and q2, thereby providing a phase error to charge conversion that is substantially linear in the phase error transition region around zero.

Abstract: A phase detecting device includes a power input unit that receives an AC voltage; a phase detector that detects zero-crossing points of the AC voltage, and outputs a phase detecting signal when the zero-crossing points of the AC voltage are detected; and a power switch that selectively cuts off a flow of AC into the power input unit in response to a mode control signal.

Abstract: A method for comparing phases of two signals including placing a first output node in a floating state, detecting a first edge of a first signal on a first input node after placing the first output node in the floating state, coupling the first edge of the first signal to the first output node and resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node. A system for comparing phases of two signals can also be included.

Abstract: In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 ?m CMOS technology.

Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.