Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.

Abstract: Apparatus for generating two output signals with a selective predetermined constant phase difference therebetween from an input reference signal having a predetermined frequency and phase includes, in one embodiment, a first and a second Programmable Delay, and a first and a second Synthesizer. The input reference signal is provided as separate inputs to the first and second Programmable Delays which generate first and second output signals, respectively, with selective predetermined delay differences therebetween for transmission to the respective first and second Synthesizers. Each of first and second Synthesizers are phase locked loops with a Programmable Divider and an optional Prescaler added to the loop to divide a high frequency output signal generated by a Voltage Controlled Oscillator (VCO) to a frequency of the output signal from the associated Programmable Delay in order to correct for any phase difference between the output signal of the VCO and the input signal from the Programmable Delay.

Abstract: A phase modulated signal is split into quadrature components Savg+SaSin(.phi.(t)+kx(t)) and Cavg+CaCos((.phi.(t)+kx(t)). The average value for each signal is compared with the signal to produce a data bit whose meaning is that the average value was exceeded at a sampling instant. The bits at successive times (t.sub.0 and t.sub.1) are separated by an interval set by the Nyquist rate on the peak rate of change of the phase for the signal. Four bits at two sample times t.sub.0 and t.sub.1 are processed to determine the phase quadrants modulo 360 degrees to determine the direction of the phase change. The determination is used to produce a counter enable signal, counter direction control signal (up/down) and optionally an error signal if the phase change during one clock period is more than plus or minus one quadrant. A tracking counter counts the number of quadrants of change from those signals.