Abstract: A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.

Abstract: A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the power supply voltage is lowered, a sufficient output signal amplitude can be obtained. An increase in circuit scale can be prevented and the power consumption can be reduced. An output-stage operating voltage supply source, including an N-channel MOS transistor having a first threshold voltage, applies an operating voltage lower than a power supply voltage to the output stage of the output circuit. A drive-circuit operating voltage supply source, including an N-channel MOS transistor having a second threshold voltage lower than the first threshold voltage, applies a drive-circuit operating voltage higher than the output-stage operating voltage to a drive circuit.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Embodiments of the present invention relates to an integrated mixer. A problem with producing low power consumption mixers is that they require a relatively high operating voltage due to the number of layers of transistor between the power rails.

Abstract: A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input signals have equivalent voltage levels. The radiation hardened inverter and its output signal produce a radiation hardened node that drives either one of the duplicated inverter paths back to an appropriate voltage level in the event of an SET. Because, the radiation hardened node and duplicated inverter paths are isolated, the latch may be optimized for factors such as signal speed and driving strength. These factors may be optimized without affecting radiation hardness. The radiation hardened latch may also be used to build more complex circuits such as a flip-flop.

Abstract: RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and at least one region of a second conductivity type in the body, with a conductive layer over at least part of the body and the region of the second conductivity type and insulated therefrom. The MOS device may be coupled into a phase distortion circuit individually or in back-to-back pairs and biased to invert the body under the conductive layer for small signal amplitudes and not for large signal amplitudes, or to not invert the body under the conductive layer for small signal amplitudes and to invert the body under the conductive layer for large signal amplitudes. Various embodiments are disclosed.

Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

Abstract: In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The input of a second inverter is connected to the output of the first inverter. When the input to the first inverter is disturbed by a soft error event, a signal tristates the first inverter.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A high-speed semi-dynamic flip-flop circuit uses a keeper transistor to replace the back-to-back inverter keeper circuit of prior art semi-dynamic flip-flop circuits to avoid the fight between a first node, or OUTBAR node, and the prior art back-to-back inverter keeper circuit. The result is a faster semi-dynamic flip-flop circuit that is also immune to noise.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A state saving circuit includes a state saving latch powered by an un-interruptible power supply, and a cut-off control device powered by the un-interruptible power supply that selectively connects the state saving latch to a pair of latch nodes based upon a control signal. The control signal determines whether the state-saving latch is in one of a state saving mode and a state restoring mode.

Abstract: Methods for implementing familiar electronic circuits at nanoscale sizes using molecular-junction-nanowire crossbars, and nanoscale electronic circuits produced by the methods. In one embodiment of the present invention, a 3-state inverter is implemented. In a second embodiment of the present invention, two 3-state inverter circuits are combined to produce a transparent latch. The 3-state inverter circuit and transparent-latch circuit can then be used as a basis for constructing additional circuitry, including master/slave flip-flops, a transparent latch with asynchronous preset, a transparent latch with asynchronous clear, and a master/slave flip-flop with asynchronous preset.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A multiple trip point fuse latch device and method is disclosed. Multiple read inputs to a fuse latch enable the altering of the resistive trip point of the fuse latch. A multiple trip point fuse latch may be combined with a slave latch to form a master-slave flip-flop, and multiple master-slave flip-flops may be connected in series to form a shift register. Changing the trip point permits the use of a test procedure that may analyze the margins of a fuse latch during the fuse read operation.

Abstract: A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto. By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%.

Abstract: A logic circuit includes a data-enable controller for outputting a data value. When implemented as a master-slave flip-flop, a data enable signal controls the activation of a master stage of the flip-flop in conjunction with the transitioning edge of an input clock signal. The data enable signal also controls the feedback of a logical value stored in the slave stage to a storage node of the master stage. Operation of the slave stage may be controlled by the input clock signal only. Through this structural configuration, the flip-flop or latch outputs logical values without requiring any additional forward-path delay elements. As a result, these devices are faster and more efficient than conventional circuits.

Abstract: A CMOS implemented passive mixer circuit for improving linearity performance in wireless communication systems is described, including dual pairs of NMOS FETs and dual pairs of PMOS FETs. Each NMOS FET is connected in parallel with a corresponding PMOS FET. A local oscillator signal is provided to the gate of one FET while a 180-degree phase shifted local oscillator signal is provided to the gate of its complementary FET. Because the complementary FETs are driven by local oscillator signals that are 180 degrees out of phase, the NMOS FET is turned on for at least a portion of the positive cycle of the local oscillator signal and the PMOS FET is turned on for at least a portion of the negative cycle of the 180-degree phase shifted local oscillator signal. Distortion in the mixed output signal is thereby reduced.

Abstract: A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.

Abstract: A static, double-edged triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loop share a forward path having a data-inverting circuit and a feedback loop having a switch. In addition, each loop has a feedback path having a weak transistor. For the upper data path, the feedback transistor is operated on the basis of a skewed clock signal. For the lower data path the feedback transistor is operated on the basis of a complementary skewed clock signal. The use of clock skew and feedforward assist in race resolution. The use of extra resistance in the feedback transistor of the shared path similarly ensures that a race will be correctly resolved.

Abstract: A tristable latch circuit fabricated utilizing standard MOS process technology includes a biasing element for identically biasing the MOS transistors in triode (as opposed to saturation) to implement a third stable operating point.

Abstract: A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating circuit, a second transistor having a source or drain connected to the clock signal generating circuit, a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal, and a latching circuit that latches a latch voltage value based on voltages at the first transistor and the second transistor. The charge storage area supplies a first voltage representing a state of the storage voltage to a gate of the first transistor and supplies a second voltage to a gate of the second transistor.

Abstract: A delay circuit includes an output circuit including first and second output elements. The first and second output elements are connected serially between a first power supply source and a second power supply source. The delay circuit further includes a delay element, which is coupled between a first input circuit and an output circuit to generate a first control signal that is delayed with respect to the input signal. The delay circuit still further includes a first node coupled between the delay element and one of the first and second output elements; and a second node, coupled to the other output elements to supply a second control signal having substantially no delay with respect to the input signal.

Abstract: The present invention encompasses a bus hold and weak pull-up circuit. A resistor having a first node and a second node is coupled to a bi-directional I/O pin at the first node. The weak pull-up circuit is directly coupled to the resistor at the first node. The bus hold circuit is coupled to the resistor at the second node.

Abstract: A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

Abstract: A low power, high performance flip-flop which does not require a full feedback path in the master stage includes a master stage driven by a data input, and an inverter. A slave stage includes a pass device for isolating the slave stage and the master stage, the slave stage having a feedback path for holding a data value passed to the slave stage.

Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.

Abstract: A high-speed D flip-flop includes first and second precharge circuits, and first to fifth switching circuits. The first precharge circuit precharges first and second internal nodes to a first supply voltage in response to a clock signal, and the first switching circuit provides a first discharge path between the first internal node and a third internal node in response to an input signal. The second switching circuit provides a second discharge path between the second and third internal nodes in response to a potential of the first internal node, and the second precharge circuit precharges an output terminal to a first supply voltage in response to a potential of the second internal node. The first switching circuit provides a third discharge path between the output terminal an the third internal node in response to the potential of the second internal node, and the fourth switching circuit connects the first to third discharge paths with a second supply voltage in response to the clock signal.

Abstract: A CMOSFET switch includes a NMOSFET, a PMOSFET, an input formed at the connection of the source terminals of the MOSFETs, and an output formed at the connection of the drain terminals of the MOSFETs. At least one of the MOSFETs is characterized by a small magnitude inherent threshold voltage, or the CMOSFET switch has at least one circuit that is capable of reducing a voltage difference between the source and body terminals of a MOSFET, or both. The variations in on resistance can be reduced over a wide common mode range by reducing the threshold voltages of the NMOSFET and the PMOSFET of the CMOSFET switch.

Abstract: Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength, latches according to the invention include feedback stages with multiple inverters. By using only transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latches of the invention is increased significantly over that of prior art latches.

Abstract: A mixer circuit (100) includes two balanced transmission gate mixers (102, 104). The mixer circuit (100) balances charge injection mechanisms which reduces carrier feedthrough in the preferred embodiment. The inputs signals provided to the second transmission gate mixer (104) are reversed as compared to those provided to the first transmission gate mixer (102). By reversing the forward path through the second transmission gate mixer (104), charge injection parasitics seen by the first transmission gate mixer (102) are canceled by those in the second transmission gate mixer (104).

Abstract: A method and apparatus for storing data in a master flip flop, comprising in combination receiving a clock signal having a first and second state, storing a master data state in a master storage device having a master storage input and a master storage output, storing a master complement data state in a master complement storage device having a master complement storage input and a master storage complement output, receiving a data input signal by a transmission gate, receiving a complement data input signal by a complement transmission gate, overriding the master storage complement output with the data input signal when the clock is in the first state, overriding the master storage output with the complement data input signal when the clock is in the first state, disconnecting the master storage complement output from the data input signal when the clock is in the second state, and disconnecting the master storage output from the complement data input signal when the clock is in the second state.

Abstract: Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals Ssns.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: Latch circuitry has a data input stage for sampling a first input signal responsive to a first timing signal and generating a signal on an intermediate node in the latch circuitry. The latch circuitry also has a scan input stage for sampling a second input signal responsive to a second timing signal, and generating a signal on the intermediate node. The latch circuitry also has an output stage for generating an output signal on an output node of the latch circuitry responsive to the signal on the intermediate node and a third timing signal. The data input signal has a maximum voltage level and at least one stage of the latch circuitry is operable to effectively shift the voltage level so that the output signal has a higher maximum voltage level than that of the data input signal.

Abstract: A latch that is insensitive to alpha particle strikes. The latch comprises input circuitry that receives an input data value to be stored in the latch, a transfer gate that is closed when the input circuitry is driving the latch to store the received data value, and a feedback circuit that drives the latch when the transfer gate is opened and the input circuitry is no longer driving the latch. When the input circuitry is driving the latch, the strength of the input circuitry is sufficient to prevent an alpha strike error from occurring in the latch. When the input circuitry is not driving the latch, the transfer gate is opened and the feedback circuit generates a feedback signal that drives the latch with sufficient strength to prevent an alpha strike error from occurring.

Abstract: The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Abstract: A latch includes a pair of inverters cross-coupled between a storage node and a feedback node. A capacitor is conditionally coupled to the feedback node through a pass gate such that the capacitor is coupled to the feedback node when the latch holds data and is not coupled to the feedback node when the latch is loading. The capacitor reduces the latch's susceptibility to soft errors when holding data, and does not appreciably slow the latch when data is loading. The capacitor is implemented using the gate capacitance of complementary transistors. A flip-flop includes cascaded latches, one or more of which have a switched capacitor on a feedback node.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A storage element includes a forward inverter and a feedback inverter cross-coupled between a storage node and a feedback node. A capacitive load within the feedback inverter is coupled to the storage node when the storage element holds data and is not coupled to the storage node when the storage element is loading. The capacitive load reduces the storage element's susceptibility to soft errors when holding data, and does not appreciably slow the storage element when data is loading. The capacitive load is implemented using the gate capacitance of complementary transistors connected to stack nodes within the feedback inverter. A flip-flop includes cascaded latches, one or more of which have the internal capacitance.

Abstract: Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: A static, double-edge-triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loops share a forward path having a data-inverting circuit. In addition, each loop has a feedback path which contains only one element in the form of a switch. However, no data-inverting circuit is included in either of the feedback paths. Advantageously, all the elements of the flip-flop may be constructed using MOSFET transistors implemented according to any one of a variety of semiconductor technologies. In more than one particularly advantageous embodiments, the flip-flop is constructed using a total of twelve transistors.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An integrated circuit device for synchronization of data in a data path includes a driver and a storage element coupled to the driver for driving the storage element. The storage element is coupled to the data path outside the data path. The integrated circuit employs a method of operation including passing a time pulse, sampling data during the time pulse, passing the data to a computation logic along a data path, and storing the sampled data in a storage element connected to but outside the data path.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.