Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

Abstract: A latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time. This is preferably accomplished by providing both a data input signal and a complement data input signal to the latch or flip-flop. The data input signal and the complement data input signal are selectively connected to opposite sides of a pair of cross-coupled gates via a switch or the like. The switch is preferably controlled by an enable signal, such as a clock. With the switch elements enabled, the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal. Because the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal, the clock-to-q time may be reduced.

Abstract: A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation.

Abstract: An a new dynamic logic entry latch or new “ELAT” and a method to capture a static input and convert it to a single rail dynamic signal with improved functionality and reduced clock and input load. The new ELAT utilizes a pulsed evaluate concept to enable more complex pull-down stack configurations and other improvements. The pulsed evaluate concept uses a pulse generators driven by the static input and a clock waveform to evaluate the static input and appropriately drive field effect transmitters on the pull-down stack. Utilizing multiple-input pulse generators or multiple pulse generators, the new ELAT can allow a wider variety of input functions and their inverses to be constructed without over-loading the pull-down stack.

Abstract: A latch device having a selectable feedback path includes a retaining device and system isolation device. The retaining device retains within the feedback path a logical value to be written out. The logical value is latched during an active clock signal. The system isolation device disconnects the retaining device from the feedback path during a write operation. Then, when the logical value is written out, the system isolation device reconnects the retaining device. Thus, the feedback path of the latch device may be disconnected to allow for a change in the latch state without overdriving a feedback inverter.

Abstract: The present invention provides a single-event upset (SEU) hardened integrated circuit. The integrated circuit includes an SEU hardened asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, where upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state. A switch may be provided for changing the latch from the first logic state to the second logic state.

Abstract: The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.

Abstract: A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.

Abstract: A p-type MOS transistor 40 in a CMOS inverter 50 of a load circuit 20 has a threshold voltage whose absolute value |Vtp| is higher than the threshold voltage Vtn of an n-type MOS transistor 30 forming a pass-transistor logic circuit 10. Therefore, even when the output signal V1out from the pass-transistor logic circuit 10 is HIGH, a leak current can be prevented from flowing into the CMOS inverter.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

Abstract: Differential receiver having a pair of cross coupled amplifiers improves signal detection in CMOS circuits. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. A signal input node is coupled to a source region for the first transistor. A signal output node is coupled to drain regions for the first transistor and the second transistor. The differential receiver further includes a third transistor of a first conductivity type. The signal input node for each amplifier is coupled to a gate of the third transistor of the respective amplifier. A drain region of this third transistor is coupled to a positive voltage supply and a source region is coupled to a low voltage potential. The drain region of the third transistor is also coupled to the gate of the first transistor of the respective amplifier.

Abstract: In a current comparison type latch, during a reset mode of the current comparison type latch where the clock signal is at the “L” level, transistors which are disposed along the current path extending from the high potential power supply line to the low potential power supply line are turned OFF while transistors which connect the high potential power supply line to two output terminals are turned ON, so as to bring the potential of each of the two output terminals to a logic level (the “H” level or the “L” level), thereby preventing a through current from flowing from the high potential power supply line to the low potential power supply line. Therefore, a high-speed and high-precision current comparison is made while reducing the through current during a reset mode.

Abstract: Circuit for reducing a standby current, is disclosed, including a PMOS transistor connected to a power supply voltage terminal, an NMOS transistor connected to a ground voltage terminal, and a switching device between the PMOS transistor and the NMOS transistor for cutting off a leakage current flowing to the NMOS transistor through the PMOS transistor, whereby minimizing a leakage current and shortening a time period for going from a standby state to an active state.

Abstract: A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the “output side” and the “reference side,” are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion.

Abstract: An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.

Abstract: D flip-flop structures are provided which respond to a DATA signal and a clock (CLK) signal by generating an output signal whose state during each clock pulse is that of the DATA signal at that pulse's leading edge and whose state between clock pulses is reset to a selected logic value. Accordingly, these flip-flops can function (e.g., monitor events in the DATA signal or generate sequences of trigger pulses) at the clock rate.

Abstract: A novel latch circuit configuration that substantially reduces inverter-based setup and hold times. The latch circuit includes first and second input switches connected to an effective sense amplifier configuration. It is possible for the input switches to receive complementary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a “buffer” and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract: In a non-volatile memory capable of electrically rewriting data, a timer circuit for determining writing time that is operable at any time at a voltage of under 1.0 V. The timing circuit has a regulated voltage circuit for outputting a regulated output voltage no greater than 1.0 V, a constant current circuit for producing a constant current having a value determined by the regulated output voltage, a voltage comparing circuit for comparing an input voltage input to one terminal with a reference voltage input to another terminal, and a capacitive element connected to a constant current output terminal of the constant current circuit.

Abstract: A latch circuit for eliminating slew current flowing in between power sources during period when clock signal changes. In the latch circuit, an input terminal is formed in such a way that dual transfer gates are connected to respective nodes remaining differential signal of bistable circuit which is constituted that one pair of clocked.cndot.CMOS inverter is subjected to mesh connection. An output terminal of holding signal of latch circuit is drains of PMOS and NMOS transistors being adjacent to end terminal of power source, which transistors are member of the one pair of clocked.cndot.CMOS inverter. Gates of PMOS and NMOS transistors being adjacent to side of output terminal are taken to be input terminal of gate signal of the latch circuit. During period of sampling calculation, since there exists MOS transistor which is connected in series between power sources and which is sure to stand of OFF state, it is capable of cutting transient slew current flowing between power sources.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q.sub.A).

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit includes a selection circuit for selecting one circuit from among the plurality of circuit alternatives. The selection circuit is controlled by a bistable circuit having a preferred state. A disactivatable forcing circuit associated with the bistable circuit is provided for forcing the bistable circuit into a state opposite than the preferred state, so that when the forcing circuit is disactivated, the bistable circuit automatically switches to the preferred state.

Abstract: An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.

Abstract: The present invention discloses a Schmitt-trigger circuit with less power consumption by reducing the amount of the required DC current. The Schmitt-trigger circuit disclosed in the present invention basically encompasses a comparison circuit, a first current cutting circuit, and a second current cutting circuit. The comparison circuit receives the input signal and then generates the output signal. Both the first and second current cutting circuits feed in the output signal, and then generate feedback signals to feed the comparison circuit for cutting the DC current path when the input signal rises or falls to predetermined trigger points. When there is only one of the first and second current cutting circuits is required, the higher or lower trigger point can be adjusted without necessary to vary the size-ratio of the PMOS and NMOS transistors.

Abstract: A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.

Abstract: A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.

Abstract: In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC current. In one embodiment a pull-up/pull-down circuit is provided that powers up to a first state with the pull-up node high and the pull-down node low, and that can be toggled from one state to another. A second embodiment provides a pull-up or pull-down circuit that powers up to the desired state and can be disabled by pulling the pull-up node low or pulling the pull-down node high. The circuits remain disabled until the power to the circuit is cycled.

Abstract: A CMOS latch circuit comprises a data input node, an output node, and first and second inverters, each of which have an input coupled to the data input node, and an output coupled to the output node. Pairs of feedback NFETs and PFETs are each coupled in series between V.sub.CC and ground. Intermediate nodes between each of the NFET and PFET feedback pairs are coupled to the data input node. The gate of the first feedback NFET is coupled to the data input node, and the gate of the second NFET is coupled to the output node. Similarly, the gate of the first PFET is coupled to the output node, and the gate of the second PFET is coupled to the data input node. The CMOS latch circuit maintains a logic state at the output node regardless of a high-energy particle strike.

Abstract: A novel latch circuit configuration that substantially reduces inverter-based setup and hold times. The latch circuit includes first and second input switches connected to an effective sense amplifier configuration. It is possible for the input switches to receive complementary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: An integrated, low power bus holder circuit implemented in low voltage technology is capable of interfacing with a relatively high voltage bus. In an illustrative embodiment, the bus holder circuit includes a first inverter for inverting a logic voltage present on a data bus and a second inverter for inverting the output of the first inverter. The second inverter is comprised of a series string of first and second pFETS and first and second nFETS, with the gates of the first pFET and first nFET coupled to the output of the first inverter. The data bus is coupled to a first circuit node between the second nFET and second pFET, and the bus logic level is maintained thereat. A third pFET is coupled to the second inverter and conducts current when a high logic voltage is present on the bus. A resistance device is coupled between a drain of the third pFET and a point of low reference potential.

Abstract: A flip-flop with enhanced support for dynamic circuits. The flip-flop comprises at least one data input node along with at least one inverting and at least one non-inverting output node. A clock input node receives an external clock signal and transmits it to a clocking unit which, in turn, generates a clock signal therefrom for gating an input signal received at the data input node. A storage unit holds the input signal value upon assertion of the clock signal and simultaneously transmits that value in appropriate logic level to inverting and non-inverting outputs. It is understood that the inverting and non-inverting outputs represent complementary signal values as is normally known in the art. The flip-flop further comprises a clear input node which is coupled to an edge-sensitive quiescent state control unit. A predetermined logic state transition, i.e.

Abstract: A soft latch circuit having a first and second inverter is disclosed. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The first inverter includes a complimentary pair of field-effect transistors (FETs). The second inverter includes either a complimentary pair of current mirrors, or a current mirror and a complimentary FET, the latter providing improved noise immunity characteristics when the soft latch is set in only one direction.

Abstract: A full-swing high voltage data latch for operation at relatively high power supply voltages. The full-swing high voltage data latch has a high voltage rail for supplying an upper voltage level and a low voltage rail for supplying a lower voltage level. A latch circuit is coupled to the upper voltage rail and to the lower voltage rail. The latch circuit is used for generating an output signal. The output signal switches with respect to an input signal when the high voltage rail and the low voltage rail operate in a low voltage mode and is latched in a state that the output signal is currently at when the high voltage rail and the low voltage rail changes state from said low voltage mode to a high voltage mode. An input circuit is coupled to the latch circuit for sending an input signal and a complementary input signal to the latch circuit. An output driver circuit is coupled to the latch circuit for receiving the output signal from the latch circuit and for providing a full-swing output data latch signal.

Abstract: A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers.

Abstract: A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a precharge phase and an evaluation phase. The dynamic input stage has a NMOS logic block coupled to receive one or more data signals. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the NMOS logic block of the dynamic input stage causes the dynamic input stage to generate an output signal that either remains at a logic high level or else transitions from high-to-low by performing a logic operation of the data signals. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop.

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal.

Abstract: A high voltage data latch with complementary outputs that are each set to one of two voltage levels (V.sub.pp and V.sub.b). The high voltage data latch is designed using CMOS technology wherein no PMOS transistors have a voltage level greater than V.sub.pp /2 volts across any node. This will allow PMOS transistors with lower voltage breakdown levels to be used. The high voltage data latch has two modes of operation. In a low voltage mode (V.sub.pp =V.sub.DD and V.sub.b =Ground) the outputs switch with respect to the inputs. In a high voltage mode (V.sub.pp >V.sub.b >V.sub.dd) the outputs will be latched to the state they were in when the voltage rails changed states from the low voltage mode to the high voltage mode.

Abstract: A fast data transmission circuit for a semiconductor memory minimizes voltage variations of a data transmission line without the use of a separate data transmission voltage. The data transmission circuit includes a pair of input nodes, a data transmission line pair, a pair of sensing nodes, a pair of output nodes, and a control electrode. Prior to data transmission, the output nodes are pulled up to a high voltage state, the data transmission line pair is pulled down to a low voltage state, and the sensing nodes are held between the high and low voltage states. When the control pulse is applied to the control electrode, the sensing node voltage levels are transferred to the data transmission line pair by the sensing voltage transfer circuit. When one input node is pulled to a low voltage state, a corresponding one voltage level on one transmission line is changed, causing a corresponding change of voltage at one of the sensing nodes.

Abstract: In a latching circuit including a first inverter having first input and output sides, a second inverter having second input and output sides, the first input side is connected to an input terminal, the second input side is connected to the first output side, the second output side is connected to the input terminal, and the second inverter further has first and second transistors having a primary conduction-type and are serially connected between first power supply terminal and the input terminal and including first and second gates having first and second gate lengths, respectively, third and fourth transistors having a secondary conduction-type reverse to the primary conduction-type and are serially connected between a second power supply terminal and the input terminal and including third and fourth gates having third and fourth gate lengths, respectively. The first gate length is greater than the second gate length while the third gate length is greater than the fourth gate length.

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract: An accurate, low-current integrated circuit comparator includes a differential input stage 10 comprising differential pair transistors 22 and 24, differential pair current mirror transistors 26 and 28, and a constant current source transistor 30. The comparator also includes an hysteresis stage 12 coupled to one of the current mirror transistors; the hysteresis stage comprises an hysteresis mirror transistor 34 and a switching transistor 36. The comparator additionally includes a gain stage 14 comprising a gain transistor 38 and a constant current source transistor 40. Finally, the comparator includes an output stage 15 comprising gain transistor 42 in an open-drain configuration. In the disclosed embodiment, the descending trip threshold is set entirely by the ratios of device geometries, and is therefore very accurate and is independent of temperature, lithography and processing variations.

Abstract: The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.