Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function.

Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.

Abstract: A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract: According to one embodiment, a transfer circuit includes a first inverter, a second inverter, a first line, a second line, a first holder, and a second holder. The first inverter inverts data at a first node and transfers the inverted data to a second node. The second inverter inverts the data at the second node and transfers the inverted data to the first node. The first line connected to the first node. The second line connected to the second node. The first holder may output data to the first node. The second holder may output data to the second node. When the first holder outputs the data to the first line, the first and second inverters are turned off. When the second holder outputs the data to the first line through the second node, the first inverter is turned off.

Abstract: A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

Abstract: A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node.

Abstract: A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract: A latch circuit has: a data input unit to which an input data is input; and a data retention unit including a node connected to the data input unit. The data input unit transmits a data depending on the input data to the node, when both of a first clock signal and a second clock signal that are driven independently from each other are at a first level. The data retention unit holds a data at the node, when at least one of the first clock signal and the second clock signal is at a second level that is an inverted level of the first level.

Abstract: An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.

Abstract: This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states.

Abstract: A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.

Abstract: A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.

Abstract: Pulse-generator circuit for generating an input signal for a flip-flop circuit from a clock-pulse signal and a data signal. The circuit includes a control unit for controlling a clock-pulse field effect transistor, a logic field effect transistor and a feedback field effect transistor. To generate the input signal, the control unit is configured in such a way that the clock-pulse field effect transistor is controlled chronologically after the logic field effect transistor and the feedback field effect transistor, thus generating the flip-flop signal.

Abstract: A flip-flop includes a sense amplifier stage and a latch stage. The sense amplifier includes a first P type transistor and generates a first sensed signal and a second sensed signal in a first node and a second node, respectively. When the first P type transistor is turned on, the first node is connected to the second node. The latch stage generates a first output signal and a second output signal according to the first and the second sensed signals.

Abstract: Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal.

Abstract: Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.

Abstract: Disclosed is a method and apparatus for amplitude modulation of an RF transmit signal using pulse width modulation to control an amount of energy within each period. The apparatus includes a signal processing circuit with an input port for receiving of information indicative of a carrier frequency and modulation data. The signal processing circuit has a first output port and a second output port for providing of output signals having a phase relationship therebetween. A power amplifier is provided for receiving the output signals and for generating a pulse width modulated signal in dependence thereon.

Abstract: Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.

Abstract: Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to receive a control signal, and a dynamic node to be driven by the ramped clock signal. The digital system further includes a static memory element having an input at the dynamic node and is configured to reside in an operational state in accordance with the data signal and the ramped clock signal. The input element further includes a switch coupled to the control input to condition updating of the operational state based on the control signal without decoupling the ramped clock signal from the dynamic node. In this way, distribution and delivery of the ramped clock signal to the digital system is continued to facilitate recovery of clock signal energy from the digital system.

Abstract: A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.

Abstract: A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal in response to a scan enable signal and an inversed scan input signal. A second pulse signal generator generates a second pulse signal in response to the scan enable signal and a scan input signal. A signal transmitter receives a data signal and transmits the data signal to a first node in response to either one of the first and second pulse signals. A signal latch unit receives the data signal transmitted to the first node, and latches and outputs the data signal in response to another one of the first and second pulse signals.

Abstract: A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area, formed on the semiconductor chip, which operates at a second voltage and a second frequency lower than the first voltage and the first frequency, respectively, and also operates after a shift to the first voltage and the first frequency; and a third area, formed on the semiconductor chip, which operates at the first voltage and a frequency which operates the second area and transmits and receives signals sent between the first area and the second area; the third area possessing a delay analysis endpoint that can analyze each of a first delay occurring between the first area and the third area and a second delay occurring between the second area and the third area.

Abstract: A sense amplifier based flip flop and method thereof are provided. The example sense amplifier-based flip-flop may include a first current passing unit receiving a first clock signal with a first delay, the first current passing unit configured to pass current from a first node to a ground terminal if the applied first clock signal is set to a first logic level and not to pass current from the first node to the ground terminal if the applied first clock signal is set to a second logic level and a second current passing unit receiving a second clock signal with a second delay, the second delay and the first delay not being the same, the second current passing unit configured to pass current from a second node to the ground terminal if the applied second clock signal is set to the first logic level and not to pass current from the second node to the ground terminal if the applied second clock signal is set to the second logic level.

Abstract: The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “implicit” pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “explicit” pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.

Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Abstract: A noise filter circuit includes a latch circuit that receives an input signal. The latch circuit includes first and second logic circuits (e.g., NAND circuits). The first and second NAND circuits are configured so that the capability of a P-type transistor that receives a set signal or a reset signal is lower than the capability of an N-type transistor that receives the set signal or the reset signal and the capability of an N-type transistor connected in series with the N-type transistor that receives the set signal or the reset signal (total capability). The noise filter circuit may include a waveform adjusting circuit that receives an output signal from the latch circuit.

Abstract: A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.

Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A frequency divider is disclosed herein. The frequency divider includes a first latch circuit and a second latch circuit coupled to the first latch circuit. Each of the first latch circuit and the second latch circuit includes a first level for generating a source current, a second level for receiving a pair of input signals and for generating a pair of output signals, and a third level for receiving the source current and a pair of clock signals. The second level is coupled between the first level and the third level. The first level includes a first transistor having a source terminal and a substrate both coupled to a source voltage. The third level includes a plurality of transistors controlled by the pair of clock signals. Each transistor in the third level has a source terminal and a substrate both coupled to ground.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.

Abstract: A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.

Abstract: Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

Abstract: In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.

Abstract: A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by raising the potential of the body terminal of the first input transistor, the threshold voltage is reduced so that the current flowing through the second input transistor is increased to shorten the time of the change of the signal status.

Abstract: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.

Abstract: A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.

Abstract: A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-flop outputs data on either the rising or falling edges of the applied clock. In the double data-rate mode, when a first latch disposed in the flip-flop operates in a sampling mode, the second latch disposed in the flip-flop operates in a holding mode to supply the output data, and when the second latch operates in the sampling mode, the first latch operates in the holding mode to supply the output data. Accordingly, with each of the rising or falling edge of the clock, one of the latches supplies an output data.