Abstract: A status latch with one-phase control signal is constructed only from purely static gates, thus has great security against interference in the stationary state, and is thus suited in particular for low-voltage operation. In the one-phase latch, the power loss is particularly low due to the lower wiring capacity of the control lines, for which reason it can be advantageously used in particular in digital circuits with high data rates. Advantageously, a low number of transistors is required.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

Abstract: A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.

Abstract: An input circuit (10) includes two inverters (12, 16) and an enable transistor (18). When a logic high enable signal is transmitted to a gate electrode of the enable transistor (18). The two inverters (12, 16) form a latch that holds the data at the input port (21) of the input circuit (10). When a logic low enable signal is transmitted to the gate electrode of the enable transistor (18), the latch formed by the two inverters (12, 16) is disabled, thereby allowing fast data transmission through the input circuit (10). When the voltage at the input port (21) is higher than a supply voltage of the input circuit (10), the enable transistor (18) switches off to protect a voltage supply coupled to the input circuit (10).

Abstract: A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: A latch circuit comprises, as a circuit corresponding to 1 bit, a flip-flop 50 which is composed of a plurality of NAND gates 11a, 11b, and holds a given signal value and outputs the positive logic value to a Q signal line 5a and the negative logic value to a /Q signal line 5b, and a differential amplifying circuit composed of a plurality of P-type FETs and N-type FETs and having a characteristics such that, an input voltage to the flip-flop 50, when the signal to be held is given, starts to fall before the time point when a drop in voltage of either an X signal line 4a or a /X signal line 4b becomes larger than the difference between a source voltage and a threshold voltage of the NAND gates 11a, 11b. The latch circuit is mainly used as internal elements of a data processor, whereby when the signal is inputted, an voltage of the input signal to the flip-flop 50 of the latch circuit approaches to the threshold voltage of the logic gates constituting the flip-flop 50.

Abstract: A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an output signal responsive to the signal transition. The second circuit section has a first circuit portion receiving the input signal and a second circuit portion, responsive to the input signal, and the output of the first circuit section, to accelerate the signal transition of the first circuit portion. Signal delay in a signal transition due to a large parasitic capacitance and resistance can be recovered by the drive circuit. The drive circuit has a large noise margin and operates at a high-speed and in a wide frequency range.

Abstract: A status register apparatus includes a control information register for holding one item of control information. An ON decoder is connected to receive a control word composed of a plurality of bits and for generating a set signal to the control information register when the ON decoder detects a first bit pattern for setting the control information register into an on condition. An OFF decoder is connected to receive the control word and for generating a clear signal to the control information register when the OFF decoder detects a second bit pattern for setting the control information register into an off condition. When the first bit pattern is detected by the ON decoder, the control information register is set to the on condition in response to the set signal. When the second bit pattern is detected by the OFF decoder, the control information register is set to the off condition in response to the clear signal.

Abstract: A circuit for comparing an input signal having a first voltage to a reference signal having a second voltage to determine whether the input signal voltage is greater than or less than the reference signal voltage. In a preferred embodiment, the circuit essentially employs only four transistors (two inverters). First and second complimentary transistors are coupled in series to form the first inverter. Third and fourth complimentary transistors are coupled in series to form the second inverter. Between the first and second complimentary transistors is a first node and between the third and fourth transistors is a second node. The first and third transistors are coupled to together at a third node. The second and fourth transistors are coupled together at a fourth node. In a first phase of operation, the circuit receives the input voltage and the reference voltage.

Abstract: A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the drains of each PFET-NFET pair and two low impedance conductive paths provide a direct coupling between the drains of each transistor of one invertor to common gate node of the other invertor.

Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: A flip-flop circuit includes a first switch for controlling passing of input data in response to a single clock signal, a first inverter for inverting the data passed through the first switch, a second inverter for inverting the data output from the first inverter into inverted data and for inputting the inverted data to the first inverter, a second switch for controlling passing of the data output from the first inverter in response to the single clock signal, a third inverter for inverting the data passed through the second switch, and a fourth inverter for inverting the data output from the third inverter into inverted data and for inputting the inverted data to the third inverter, where the first inverter has a driving capability larger than that of the second inverter, and the third inverter has a driving capability larger than that of the fourth inverter.

Abstract: A system and method is provided which includes a set of N and P type transistors connected such that both positive active and negative dynamic logic input pulses may be received. The pulse catcher circuit of the present invention then outputs a static logic level based upon the input pulses. A first input circuit is included that receives the data signal and outputs a level (voltage or absence of a voltage) to an output invertor circuit which is used in conjunction with a feedback circuit as a latch to maintain the output at the desired level. The feedback circuit ensures that the level will be maintained in a stable state (i.e. ground potential for a logical "0" and Vdd for a logical "1"). In this manner the static logic levels output from the circuit will be maintained until another dynamic pulse is received. Additionally, the pulse catcher circuit will always provide a consistent static logic output, even when both of the dynamic logic input signals are in their active states.

Abstract: An input buffer circuit with first and second inverters serially connected between an input terminal and an output terminal of the circuit. The input buffer circuit includes a level detector circuit for detecting that the level of a signal inputted to the input terminal is logically unsteady, and an output level holding circuit for detecting the level of a node where the first and second inverters are connected together and controlling the level of the node to maintain the level, when the level detector circuit detects that the level of the signal is logically unsteady.

Abstract: A high-voltage switching circuit comprising two arms, wherein each arm has a P-channel load transistor, a forward biased diode and an N-channel switching transistor series-connected between the high voltage and the ground. The gate of the N-channel transistor is controlled by a switching signal C in one arm and by the complementary switching signal C in the other arm. Such a structure enables the stress undergone by the load and switching transistors of the switching circuit to be reduced by several magnitudes.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.