Abstract: An RMS to DC converter squares an a-c input signal to obtain a squared direct current voltage signal. The squared direct current voltage signal is applied to successive stages, each stage amplifying its received signal and detecting the amplified level of the signal within a confined range. The detected levels detected in the successive stages are added to produce an output d-c signal that is variable in linear proportion to logarithmic change in RMS voltage of the input signal. The voltage level of the squared direct current voltage signal can be clamped to a predetermined maximum voltage. To expand the range of detection, the squared direct current voltage signal is attenuated prior to detection in one or more of the stages.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: A conventional multiplier which uses a MOS transistor has a subject that, in order to compensate for a variation of a bias voltage or the like, it is necessary to add a complicated correcting circuit to an outputting section or the like, and the circuit scale becomes great and the power consumption increases. A multiplier includes NMOS transistors (3, 4, 5) and constant voltage sources (6, 9, 12) connected to the gates of the NMOS transistors (3, 4, 5), respectively, and the voltage value of a constant voltage source (9) and the voltage value of another constant voltage source (12) are set equal to each other. Further, the NMOS transistor (4) and the NMOS transistor (5) are formed same as each other.

Abstract: A mixer circuit configured to operate in a bypass or mixing mode, and which comprises a mixer core, and a mode select circuit. The mixer core includes first and second switches, each of which has an input, and first and second outputs. The mode select circuit is coupled to the mixer core and includes third and fourth switches, which are collectively configured to operate in either a first state corresponding to the bypass mode, or a second state corresponding to the mixing mode. The input of the first switch is configured to receive a signal at a first frequency, wherein the first and second switches are configured to switch between their respective first and second outputs at a second frequency, and wherein, responsive to the state of the third and fourth switches, the first output of the first switch, and the second output of the second switch are each configured to output a signal which is either (i) at the first frequency, or (ii) a mixing product of the first and second frequencies.

Abstract: When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signal is inputted to input terminals and an output is matched with a frequency as high as that of the original frequency in a Gillbert cell double-balanced mixer, so that a doubled output is obtained with no DC offset. According to the circuit configuration of the present invention, it is possible to provide a circuit readily performing integration and to efficiently output only a double frequency merely by inputting a simple differential signal without the need for the original signal which has been phase controlled. Further, a DC short circuit in the resonance circuit makes it possible to eliminate a DC offset voltage in an output.

Abstract: A mixer includes two transistor circuits, two control inputs, two RF inputs and two IF outputs, wherein, for switch-support, there are provided positive feedback elements and impedance elements, by which intermodulation strength, stability and noise performance of the mixer circuit are improved.

Abstract: The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement, wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement. Thus, a controllable extraneous imbalance is created between the output loads of the balanced circuit arrangement to thereby obtain a linearization by means of even-order non-linearity.

Abstract: Attenuation cell comprising first and second differential pairs of bipolar transistors. A gain control device applies a voltage VA?VB between the bases of both differential pairs and comprises a set of three diodes in which a current IA, a current IB and the sum IA+IB of both preceding currents flow, respectively. The two diodes seeing current IB and IA+IB generate a voltage, respectively VB and VC, and the difference between these two voltages is used to generate a value Iz used in a control loop. A desired value Vct is transformed into information Ix, then into information Iy proportional to absolute temperature T, and an error amplifier uses information Iy?Iz and generates currents IA and IB by minimizing this difference.

Abstract: The collectors of transistors are connected via respective resistances to a power supply terminal receiving a power supply voltage. The emitters of the transistors are connected to a ground terminal via respective resistances. A shunt resistance, a FET, and a shunt resistance are connected in series between nodes connected to the respective emitters of the transistors. The gate of the FET is connected via a resistance to a control terminal receiving a control voltage. The shunt resistances and FET form a variable resistance circuit.

Abstract: A semiconductor physical quantity sensing device to perform electrical trimming at low cost by using a CMOS manufacturing process and a small number of terminals. The semiconductor physical quantity sensing device includes a wheatstone bridge circuit, which is a sensor element, an auxiliary memory circuit, which stores provisional trimming data, a main memory circuit, which stores finalized trimming data, an adjusting circuit, which adjusts the output characteristics of the sensor element based on trimming data stored in the auxiliary memory circuit or the main memory circuit, with the elements and circuits being only configured of active elements and passive elements manufactured by way of the CMOS manufacturing process formed on a same semiconductor chip.

Abstract: A power source circuit includes a power source wiring at a high potential side provided with a first power source voltage and a second power source voltage, a power source wiring at a low potential side and booster circuit as a charge pump installed between the power source wiring at a high potential side and the power source wiring at a low potential side and provided with a plurality of switching transistors and a plurality of capacitors. A control device is provided for controlling the booster circuit. A predetermined number of power sources includes the power source wiring at the high potential side are further provided with the power source circuit. An input voltage is selectively input to a part of the booster circuit from any one of the predetermined number of power sources.

Abstract: A sub-harmonic mixer comprises two field effect transistors (FETs) in which the drains are coupled together. The mixer includes a signal generator for generating two local oscillator signals in antiphase with each other and which is arranged to feed one local oscillator signal to the source of one of the FETs and the other local oscillator signal to the source of the other FET. An input and output port is coupled to the drains for receiving input signals for the mixer and outputting output signals from the mixer.

Abstract: The present invention introduces an integrated analog multiplier-divider circuit. The multiplier-divider block according to the present invention is ideal for use in the power factor correction (PFC) controllers of many switch-mode power supplies. The analog multiplier-divider according to the present invention is built with CMOS devices. Because of this, it has many advantages over prior-art multiplier-dividers. One important advantage is that the die-size and the cost can be reduced. Another important advantage of the multiplier-divider according to the present invention is substantially reduced temperature dependence.

Abstract: A clock generation system includes an oscillator and one or more clock generators. The oscillator provides inphase and quadrature oscillator signals having a fixed frequency. Each clock generator receives the oscillator signals and generates a respective output clock signal. Within each clock generator, two weight generators receive two sequences of phase values and generate weights for two analog signals. Two signal generators multiply the inphase and quadrature oscillator signals with the weights from the two weight generators and provide the two analog signals having leading edges determined by the two sequences of phase values. A digital clock generator generates a DCLK signal based on the two analog signals. A divider divides the DCLK signal by N in frequency and provides the output clock signal. A phase generator generates the two sequences of phase values for the two analog signals based on a frequency control value and a phase offset value.

Abstract: A transconductance amplifier (620) includes four transistors each operating in saturation and strong inversion. A first transistor (622) has a first current electrode and a control electrode both receiving an input voltage, and a second current electrode coupled to a power supply voltage terminal. A second transistor (624) has a first current electrode, a control electrode coupled to the first current electrode of the first transistor (622), and a second current electrode coupled to the power supply voltage terminal. A third transistor (626) has a first current electrode for providing a negative differential current, a control electrode for receiving a bias voltage, and a second current electrode coupled to the first current electrode of the first transistor (622).

Abstract: A multiplier having a simple constitution, excellent performance with respect to high-frequency characteristics and distortion characteristics, and allows low-voltage operation. Transistor Q11, resistors R11 and R12 form a common-emitter circuit. One signal of differential signal v1 is amplified by the common-emitter circuit, and the amplified signal is input to an emitter follower composed of transistor Q12. The output current of the emitter follower is input through resistor R13 into the current mirror circuit composed of transistors Q13 and Q14. Output current I5 of said current mirror circuit is input to the transistor pair of transistor Q19 and npn transistor Q20. By selecting an appropriate gain for the common-emitter circuit, currents I5 and I6 generated in this way become independent of the base-emitter voltage, and performance is improved with respect to distortion characteristics.

Abstract: The synthesizer and method provide a relatively wideband swept frequency signal and include generating a first swept frequency signal with a first generator, and successively switching between different frequency signals with a second generator. Such switching creates undesired phase discontinuities in the output swept frequency signal. The first swept frequency signal is combined with the successively switched different frequency signals to produce the relatively wideband swept frequency signal, and the second generator is calibrated to reduce the undesired phase discontinuities during switching based upon the output swept frequency signal.

Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.

Abstract: A linear multiplier circuit comprises a first, a second, a third and a fourth transistor, each having a drain, a source, a gate and substantially an identity threshold voltage. Each of these four transistors operates with a fixed drain-to-source voltage applied between the drain and source, a gate-to-source voltage applied between the gate and source. The sources of the first and second transistors, and the drains of the third and fourth transistors are coupled to form the output terminal.

Abstract: Methods, systems, and apparatuses for down-converting and up-converting an electromagnetic signal. In embodiments, the invention operates by receiving an electromagnetic signal and recursively operating on approximate half cycles of a carrier signal. The recursive operations can be performed at a sub-harmonic rate of the carrier signal. The invention accumulates the results of the recursive operations and uses the accumulated results to form a down-converted signal. In embodiments, up-conversion is accomplished by controlling a switch with an oscillating signal, the frequency of the oscillating signal being selected as a sub-harmonic of the desired output frequency. When the invention is being used in the frequency modulation or phase modulation implementations, the oscillating signal is modulated by an information signal before it causes the switch to gate a bias signal. The output of the switch is filtered, and the desired harmonic is output.

Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.

Abstract: A multiplier circuit has an analog multiplier with two signal inputs. A respective switching device is connected to each one of the two signal inputs of the analog multiplier for periodically reversing the polarity of the input voltages. A clock signal that can be fed to the switching devices has a changeover frequency that is preferably greater than or equal to twice the useful signal frequency. This suppresses offset-governed crosstalk of the input signals to the output of the analog multiplier. This principle can also be employed in quadricorrelators.

Abstract: A signal synthesizer includes a high frequency offset stage having a high frequency offset source and frequency translation element in the feedback path of a dual-oscillator offset loop synthesizer. The signal synthesizer achieves low phase noise via noise cancellation when used to provide the first local oscillator of a spectrum analyzer and when the second local oscillator of the spectrum analyzer provides the high frequency offset source to the signal synthesizer.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.

Abstract: Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output signal and a second voltage source, having a higher voltage than the first voltage source, to drive the select signals. The higher voltage source reduces the impedance of each transistor driven by the select signals, thus reducing the propagation delay at the output of the phase mixer. For a non-differential digital phase mixer, the propagation delay is reduced in the rising edges of the output signal. For a differential digital phase mixer, the propagation delay is reduced in the rising and falling edges of the output signal.

Abstract: A current-mode synapse multiplier circuit multiplies each of a plurality of pulse signals with each of a corresponding plurality of weight signals. The synapse multiplier includes a plurality of first switches each coupled to a corresponding pulse signal and the corresponding weight signal. An integral circuit is coupled to the first switches to receive the weight signals that pass through the first switches and integrates the sum of the weight signals that pass through the first switches over a period of time. A voltage-to-current (V-I) converter is coupled to the integral circuit to convert the integral of the sum of the weight signals that pass through the first switches into a current signal, wherein the current signal represents the sum of the multiplication products of each pulse signal and the corresponding weight signal. An external reset signal is coupled to the synapse multiplier through a second switch to reset the synapse multiplier.

Abstract: A folded cascode device senses the drain current of a source follower, and a current mirror device multiplies the sensed drain current for application to an output load. The source follower and the current mirror device are preferably of the same type (e.g., both NMOS). The resulting composite source follower provides relatively wide bandwidth at relatively low power. The folded cascode allows (NMOS) source and sink control. Using current mirror feedback reduces the stability problems associated with other solutions that rely on a voltage feedback stage. Composite source followers of the present invention can be used in any traditional buffer applications, such as in operational amplifiers, regulators, or high-speed signal paths.

Abstract: A sub-harmonic mixer comprises two field effect transistors in which the sources of the transistors are connected together and the drains of the transistors are connected together. The mixer includes signal generating means for generating a local oscillator (LO) signal coupled to the gate of one of the FETs. Circuit means is provided for maintaining the potential of the gate of the other FET at a substantially constant value relative to the local oscillator signal applied to the gate of the driven FET, and the FET's are arranged to permit the local oscillator signal applied to gate of the driven FET to drive a voltage across the gate-source of both FET's. An input and output port is coupled to the drains for receiving input signals for the mixer and outputting output signals from the mixer.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: A current-mode synapse multiplier circuit multiplies each of a plurality of pulse signals with each of a corresponding plurality of weight signals. The synapse multiplier includes a plurality of first switches each coupled to a corresponding pulse signal and the corresponding weight signal. An integral circuit is coupled to the first switches to receive the weight signals that pass through the first switches and integrates the sum of the weight signals that pass through the first switches over a period of time. A voltage-to-current (V-I) converter is coupled to the integral circuit to convert the integral of the sum of the weight signals that pass through the first switches into a current signal, wherein the current signal represents the sum of the multiplication products of each pulse signal and the corresponding weight signal. An external reset signal is coupled to the synapse multiplier through a second switch to reset the synapse multiplier.

Abstract: An analog multiplier for multiplying a first analog voltage signal at a first frequency by a second analog voltage signal at a second frequency, comprising a first stage for converting the first analog voltage signal into a first and a second current signals, and a second stage comprising a first and a second cross-coupled current-switching pairs, driven by the second voltage signal, the first and second current-switching pairs having respective current inputs for receiving the first and the second current signals, respectively. Parasitic capacitances are inherently associated with each current input of the current-switching pairs. A compensation circuit is coupled to the current inputs of the current-switching pairs for compensating the parasitic capacitances.

Abstract: A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.

Abstract: The switched charge multiplier-divider according to the present invention is constructed of CMOS devices. Capacitor charge theory is employed to implement the circuit of the switched charge multiplier-divider. The switched charge multiplier-divider includes an output capacitor and controls the voltage across the output capacitor, so that it is proportional to the product of the charge current and the charge-time interval. The switched charge multiplier-divider is ideal for use in the power factor correction (PFC) of switching mode power supplies. Potentially, it can also be applied to automatic gain control (AGC) circuits.

Abstract: Digitally-controlled, variable-gain mixers and amplifiers are provided which couple transconductance cells to receive respective tap signals from a fixed attenuator that receives a first input signal. A gain interpolator provides first and second control currents with amplitudes that correspond to a segment of a control word and a multiplexer responds to another control-word segment by routing the control currents to a selected pair of adjacent transconductance cells. In response, the transconductance cells provide amplifier current signals which can also be routed to a transistor switch that mixes them with a second input signal to generate a mixer output signal whose amplitude corresponds to the control word.

Abstract: The analog multiplier has a MOS input stage. This makes it possible to increase the linearity range of the multiplier. In a development, a cascode circuit having an additional pair of bipolar transistors is provided, which makes it possible to achieve a higher linearity without increasing the supply voltage. The analog multiplier is particularly suitable as a down-converter in a reception path of a mobile radio system.

Abstract: A system and method to extract a threshold voltage for a MOSFET include first and second stages, which include inputs that receive functionally related input currents, are connected to each other. The first stage includes a second input that is coupled to a corresponding input of the second stage through part of a voltage divider. Another part of the voltage divider is coupled between an internal gate node and the input of the second stage that receives the respective input current. The input of the second stage that receives the respective input current also provides an output voltage substantially equal to the threshold voltage for one or both of the MOSFETs.

Abstract: A direct frequency synthesizer provides an output signal derived from a high frequency reference signal that is frequency divided and mixed to satisfy the coarse step synthesis requirements of an offset loop synthesizer. The absence of a VCO within the direct frequency synthesizer, provides the direct frequency synthesizer with lower phase noise than a typical PLL-based coarse step synthesizer. Though applicable to a variety of types of synthesizers and signal generators, the direct frequency synthesizer provides especially advantageous noise performance when used to generate an offset signal for an offset loop synthesizer of the first local oscillator of a spectrum analyzer, where the second local oscillator of the spectrum analyzer provides the reference signal for the direct frequency synthesizer.

Abstract: A multiplier circuit with a multiplier core with two cross-coupled transistor pairs (2, 3; 4, 5) is specified, wherein a first and a second signal source (10, 11, 13, 14), which are driven by a first and, respectively, second signal to be multiplied, are in each case connected to control inputs of the transistors (2 to 5) of the multiplier core for diversion between the transistor pairs (2, 3; 4, 5) or, respectively, differentially between the transistors (2, 4; 3, 5) of the differential amplifiers. Due to the high degree of symmetry which can be achieved at the input gates of the circuit, a particularly precise multiplication with good linearity is possible. The multiplier described can be used, for example, as radio-frequency mixer circuit or as 90° phase detector circuit.

Abstract: A BJT operating as a mixer has its collector biased at the knee of the IC vs VCE characteristic. A local oscillator voltage is applied to the base and an RF signal voltage is applied to the collector through a singled-ended emitter follower. The nonlinear curvature at the knee produces a beat frequency current. The base of the emitter follower can be fed from a current mirror or through an ohmic resistor. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Alternatively, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain. Sometimes, it is more desirable to invert the collector and the emitter, or to connect a normal transistor and an inverted transistor in parallel to optimize conversion gain.

Abstract: A vestigial-sideband (VSB) signal is down-converted to generate a VSB signal including a carrier frequency offset from zero frequency by an amount greater than the bandwidth of the VSB signal. The carrier of this final I-F signal has a carrier offset from zero-frequency, which carrier offset exceeds the highest modulating frequency of the VSB signal and is adjusted to a prescribed carrier offset value. The down-converted VSB signal is digitized to generate a digital multiplicand signal for a digital multiplier circuit. The digital multiplier circuit is supplied a digital multiplier signal descriptive of a system function composed of a constant term and a second harmonic of the carrier frequency offset from zero frequency. Digital product signal from the digital multiplier circuit is descriptive of a double-sideband amplitude-modulation final I-F signal in the digital regime, which DSB AM final I-F signal is subsequently detected to generate a baseband demodulation result.

Abstract: A switching mode N-order circuit comprises a first unit, a second unit and a comparator. The first unit includes an operational amplifier integral circuit to integrate a first voltage. The second unit has one or more stages of subunits in cascade each including an operational amplifier integral circuit to integrate a second voltage stage by stage. Each of the operational amplifier integral circuits is equipped with a switch to be controlled by the comparator to be discharged. The output of the N-order circuit is derived from the output of the second unit.

Abstract: A frequency doubler includes a first Gilbert cell, a second Gilbert cell coupled to the first Gilbert cell, a frequency generator configured to apply a first sinusoidal wave to the first Gilbert cell, and a phase shifter applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell. A method of doubling frequency without using a feedback loop includes providing a first Gilbert cell, providing a second Gilbert cell coupled to the first Gilbert cell, applying a first sinusoidal wave to the first Gilbert cell, and applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell.

Abstract: A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee2) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. The CML circuit has an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by the first power supply and a third power supply (Vee3) that is approximately equal to Vcc−(0.4+(level of series gated logic)(0.9 volts)).

Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.

Abstract: A radio frequency (RF) mixing device wherein RF core circuit elements requiring signal splitting are provided with one or more signal splitting element(s) (“balun(s)”) integrated on-chip with the core RF circuit elements. The RF mixing device comprises one or more RF circuit element(s) integrated on a common substrate with one or more balun(s), wherein the common substrate is an insulating substrate further provided with associated silicon-based CMOS circuitry formed in a thin, highly crystalline silicon layer formed on the insulating substrate. The insulating substrate is selected from transparent crystalline materials such as sapphire, spinel, etc. The common substrate is preferably ultrathin silicon-on-sapphire.

Abstract: A mixer used in a millimeter-wave band and a microwave band capable of achieving loss reduction, a radar module, and a communication apparatus incorporating the mixer and having high efficiency. The mixer includes two electrodes formed on one main surface of a dielectric substrate and another electrode formed on another main surface thereof such that non-electrode portions on both main surfaces are opposed to each other via the dielectric substrate. Additionally, a diode is connected bridging a slit between the two electrodes on one main surface to constitute a circuit board. The circuit board and a dielectric strip are arranged between upper and lower conductive plates.

Abstract: A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.

Abstract: A mixer includes a first terminal and a second terminal forming a first input port for receiving a first signal having a first frequency; a second input port for receiving a second signal having a second frequency; a mixer output port for a resulting signal; a first group of valves having their control inputs coupled to the first terminal for receiving the first signal; a second group of valves having their control inputs coupled to the second terminal for receiving the first signal; and a third group of two valves having their control inputs coupled for receiving the second signal. The valves co-operate such that in operation the mixer produces the resulting signal responsive to the first and second signals. The mixer also includes at least one passive low pass filter having an inductor, the low pass filter being connected to the control input of a valve in the first and second groups.

Abstract: A system and method for a mixer circuit places the RF and mixer core LO transistors on the same level in anti-series. The mixer circuit provides increased headroom, excellent linearity, controllable conversion-gain, and operates with a reduced supply voltage requirement.