Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Abstract: In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node.

Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

Abstract: Embodiments provide a mixer cell, which is implemented to logically combine a data signal with an oscillator signal and a sign signal to obtain a mixer cell output signal based on the logical combination. Further embodiments provide a modulator with a plurality of mixer cells.

Abstract: According to some embodiments, an up-conversion mixer includes a mixer cell having an output node arranged to provide an output. An input stage is coupled to the mixer cell and arranged to receive an input signal. The mixer cell is configured to generate the output with an up-converted frequency compared to an input frequency of the input signal. The input stage is configured to reduce a third order harmonic term of the output so that an output power plot of the third order harmonic term with respect to an input power has a notch with a local minimum.

Abstract: A signal processing circuit includes a differential input circuit, a first DC filter, a second DC filter, a differential transconductance circuit, and a differential converting circuit. The differential input circuit includes first and second input circuits respectively for receiving first and second input signals to generate first and second processed signals. The first DC filter and the second DC filter, respectively coupled to the first and the second input circuits, receive the first and the second processed signals and output first and second voltage signals. The differential transconductance circuit includes first and second transconductance circuits, respectively coupled to the first and the second DC filters, for converting the first and the second voltage signals to first and second current signals.

Abstract: Very low phase noise radio frequency (RF) source having multiple discrete frequency outputs used, for example, to calibrate phase noise measurement systems. The calibrator output frequencies can be tailored for a particular application using a scalable architecture.

Abstract: A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

Abstract: A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter.

Abstract: A system and method for signal mixing using high-order harmonics of a local oscillation (LO) signal. In a radio frequency (RF) system, the input RF signal is converted to a lower frequency signal such as an intermediate frequency (IF) signal or a baseband signal for further processing. A voltage controlled oscillator (VCO) is often used to generate a VCO signal which is then divided down to provide the needed LO signals for down conversion. The present invention discloses a system and method for generating a composite harmonic signal based on a linear combination of divided down LO signals with specific phase shifts. Consequently a VCO signal with lower frequency can be used to conserve power. The composite harmonic signal is mixed with the input RF signal to generate a series of mixed signal including one associated with a high-order harmonic of the divided down LO signal.

Abstract: In a mixer circuit, addition of analog signals by capacitive coupling is used and square-law characteristics of the drain current of a MOS transistor operating in a saturated region are used. With this configuration, the voltage and power of the mixer circuit can be reduced.

Abstract: A transistor-based switch is coupled to a replica circuit that includes transistor circuitry similar to that of the switch. The replica circuit biases a switched transistor to promote linear operation of the switch.

Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a difference between a supply voltage and a first input voltage and a constant current supply. The current passing through the voltage controlled resistance circuit is based upon a difference between the voltage supply and a second input voltage. The first transistor may be configured to mirror the current passing through the voltage controlled resistance circuit.

Abstract: A double balanced mixer circuit comprising a differential pair of first amplifier elements responsive to an RF differential input signal, double differential pairs of second amplifier elements responsive to an LO differential input signal, and differential output terminals connected with the second amplifier paths. Coupling elements provide first and second parallel DC connections between DC voltage supply rails for the first and the double second amplifier paths respectively and a series RF connection of the first and second amplifier paths between the supply rails so as to produce a mixed differential amplified signal at the differential output terminals. The coupling elements include respective transmission lines in the first amplifier paths connected between one of the DC voltage supply rails and respective ones of the first amplifier elements and a common transmission line connected between the other of the DC voltage supply rails and both the first amplifier elements.

Abstract: A mix mode wide range multiplier and method are provided for multiplying a first signal by a second signal to generate an output signal. A reference signal is generated according to a first gain and a reference value, the output signal is generated according to a second gain and the first signal, a target value is generated according to the second signal, the first gain is adjusted to make the reference signal equal to the target value, and the second gain is adjusted to maintain a ratio of the second gain to the first gain.

Abstract: This invention provides an quadrature mixer which does not require a long time to adjust the amplitude value at the time of demodulation of the IQ signal. The quadrature mixer, comprising a first frequency-conversion unit that outputs a sixth signal derived by multiplying a first signal by a second and a fourth signals, a second frequency-conversion unit that outputs a seventh signal derived by multiplying the first signal by a third and a fifth signals, a first amplitude adjustment unit that outputs a eighth signal derived by multiplying the sixth signal by the third and fifth signals and a second amplitude adjustment unit that outputs a ninth signal derived by multiplying the seventh signal by the second and fifth signals.

Abstract: A method (1300) is provided for generating one or more waveforms (130, 140). The method includes: generating a first toggle signal (1130, 1330) in response to a clock signal (1110), the first toggle signal having one of a first positive shape, a null shape, and a first negative shape for each cycle of the clock signal; multiplying the first toggle signal by a first coefficient signal to create a first intermediate signal (1440); generating a second toggle signal (1140, 1330) in response to the clock signal, the second toggle signal having one of a second positive shape, the null shape, and a second negative shape for each cycle of the clock signal; multiplying the second toggle signal by a second coefficient signal to create a second intermediate signal (1440); and generating a first output signal (1170) by adding the first intermediate signal and the second intermediate signal together (1350).

Abstract: Consistent with an aspect of the present disclosure, an optical signal carrying data or information is supplied to photodetector circuitry that generates a corresponding analog signal. The analog signal may be amplified or otherwise processed and supplied to analog-to-digital conversion (ADC) circuitry, which samples the analog signal to provide a plurality of digital signals or samples. The timing of such sampling is in accordance with a clock signal supplied to the ADC circuitry. A phase detector is provided that detects and adjust the clock signal to have a desired phase based on frequency domain data that is output from a Fast Fourier transform (FFT) circuit that receives the digital samples. Preferably, the phase detector circuit is configured such that it need not receive all the frequency domain data output from the FFT at any given time in order to determine the clock phase.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. Differential RF power amplifiers are also provided with inductive networks coupled at various nodes of the power amplifiers.

Abstract: A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier.

Abstract: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.

Abstract: A system and method for signal mixing using high-order harmonics of a local oscillation (LO) signal. In a radio frequency (RF) system, the input RF signal is converted to a lower frequency signal such as an intermediate frequency (IF) signal or a baseband signal for further processing. A voltage controlled oscillator (VCO) is often used to generate a VCO signal which is then divided down to provide the needed LO signals for down conversion. The present invention discloses a system and method for generating a composite harmonic signal based on a linear combination of divided down LO signals with specific phase shifts. Consequently a VCO signal with lower frequency can be used to conserve power. The composite harmonic signal is mixed with the input RF signal to generate a series of mixed signal including one associated with a high-order harmonic of the divided down LO signal.

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: A signal transformation arrangement comprises a first input tap (1) to receive a first input signal (IN_P), a first output terminal (3) to provide a first output signal (OUT_P) and a first coupling circuit (10) which couples the first input tap (1) to a first energy storing device (11) depending on a first clock signal (CLK—1) and which couples the first energy storing device (11) to the first output terminal (3) depending on a first inverted clock signal (XCLK—1). The signal transformation arrangement further comprises a second coupling circuit (20) which couples the first input tap (1) to a second energy storing device (21) depending on a second clock signal (CLK—2) and which couples the second energy storing device (21) to the first output terminal (3) depending on a second inverted clock signal (XCLK—2).

Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein.

Abstract: Very low phase noise radio frequency (RF) source having multiple discrete frequency outputs used, for example, to calibrate phase noise measurement systems. The calibrator output frequencies can be tailored for a particular application using a scalable architecture.

Abstract: Delivered power detection for power amplifiers (PAs) and related systems and methods are disclosed. The disclosed embodiments and techniques provide a delivered power indication for systems using PAs, including such systems for cellular telephone applications, allow power detection circuitry to be integrated on the same integrated circuit die as the PA, and provide power detection circuitry with output signals at baseband frequencies. In one embodiment, the delivered power detection circuitry includes output voltage level detection circuitry and output current level detection circuitry that provide current signals to multiplier circuitry, which in turn provides current output signals proportional to the actual delivered power to the load as represented by the incident power to the load reduced by the reflected power.

Abstract: The invention relates to devices comprising field effect transistors to detect the power of an electromagnetic high frequency signal VRF. According to the prior art, the high frequency signal is coupled into the gate G and via a capacitor CGD into the drain D of the field effect transistor FET, the gate G being biased with a direct voltage Vg which corresponds to the threshold value of the FET transistor. The resulting current at the source S contains a direct current portion Ids which is proportional to the square of the amplitude of the high frequency signal. The operating frequency of said power detectors is limited to a few gigahertz (GHz) by the discrete arrangement and especially by the predetermined gate length of the field effect transistor. The aim of the invention is to improve a resistive mixer in such a manner that it can be operated at high gigahertz and terahertz frequencies.

Abstract: Disclosed are an addition circuit that makes it possible to add two vector signals in a high-frequency region, a power amplifier circuit using the same, and a transmission device and communication device using the power amplifier circuit.

Abstract: A MMIC (microwave monolithic integrated circuit) based FET mixer and method for the same is provided. In particular, adjacent transistors, such as FETs (field effect transistors) share terminals reducing physical layout separation and interconnections. A smaller die size is realized with the improved system geometry herein provided.

Abstract: A peak suppression device includes: a peak determination unit which determines a peak value of a waveform of an input signal; an impulse signal generation unit which generates an impulse signal corresponding to a difference between the peak value and a predetermined value if an absolute value of the peak value is greater than the predetermined value; a multiplication unit which multiplies the generated impulse signal by a predetermined impulse response waveform so as to generate a peak suppression signal; and a subtraction unit which subtracts the peak suppression signal from the input signal.

Abstract: A mixer includes a magnetoresistive effect element, a magnetic field applying unit, and an impedance circuit. The magnetoresistive effect element includes a fixed magnetic layer, a free magnetic layer, and a nonmagnetic spacer layer disposed between the fixed magnetic layer and the free magnetic layer, is operable when a first high-frequency signal and a second high-frequency signal as a local signal are inputted, to multiply the first high-frequency signal and the second high-frequency signal according to a magnetoresistive effect to generate a multiplication signal. The magnetic field applying unit applies a magnetic field to the free magnetic layer. The impedance circuit has a higher impedance for the multiplication signal than an impedance for the first high-frequency signal and the second high-frequency signal and is disposed between an input transfer line, which transfers the first high-frequency signal and the second high-frequency signal, and the magnetoresistive effect element.

Abstract: A mixer includes: a magnetoresistive effect element including a fixed magnetic layer, a free magnetic layer, and a nonmagnetic spacer layer disposed between the fixed magnetic layer and the free magnetic layer; and a magnetic field applying unit that applies a magnetic field to the free magnetic layer. The mixer is operable, when a first high-frequency signal and a second high-frequency signal as a local signal are inputted, to multiply the first high-frequency signal and the second high-frequency signal using the magnetoresistive effect element and to generate a multiplication signal. A frequency converting apparatus includes the mixer and a filter operable, when a higher frequency and a lower frequency out of frequencies of the first high-frequency signal and the second high-frequency signal are expressed as f1 and f2 respectively, to pass one out of a frequency (f1+f2) and a frequency (f1?f2) out of the multiplication signal.

Abstract: Very low phase noise radio frequency (RF) source having multiple discrete frequency outputs used, for example, to calibrate phase noise measurement systems. The calibrator output frequencies can be tailored for a particular application using a scalable architecture.

Abstract: A mix mode wide range multiplier and method are provided for multiplying a first signal by a second signal to generate an output signal. A reference signal is generated according to a first gain and a reference value, the output signal is generated according to a second gain and the first signal, a target value is generated according to the second signal, the first gain is adjusted to make the reference signal equal to the target value, and the second gain is adjusted to maintain a ratio of the second gain to the first gain.

Abstract: The technology relates to analog processing of a sum of products.

Abstract: A digital frequency generator is described.

Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.

Abstract: The low voltage mixer circuit can be fitted to a UWB signal transmission device. The circuit includes first and second differential pairs of NMOS transistors (M5, M6, M7, M8), wherein the source of the transistors (M5, M6) of the first pair is connected to the output of a first MOS transistor reverser arrangement (M1, M3) of a transconductance stage, and the source of the transistors (M7, M8) of the second pair is connected to the output of a second MOS transistor reverser arrangement (M2, M4) of the transconductance stage. The drain of the first NMOS transistor (M5) of the first pair and the drain of the second NMOS transistor (M7) of the second pair are connected to a first resistor (R0) for supplying a first output signal (RF0). The drain of the first NMOS transistor (M8) of the second pair and the drain of the second transistor (M6) of the first pair are connected to a second resistor (R1) for supplying a second output signal (RF1).

Abstract: An analog multiplier includes a bias circuit, a level shifter, a multiplying circuit, and a current mirror. The analog multiplying circuit is used for inputting a first voltage and a second voltage, and outputting a product current. The product current is proportional to a product of the first voltage and the second voltage. The analog multiplier is implemented by a few devices, thereby having a simple architecture and being capable of being driven by a small amount of power.

Abstract: A mixer used in a Radio Frequency (RF) receiver is provided. The mixer includes a first harmonic rejecter for rejecting a harmonic signal component from a first input signal; and a second harmonic rejecter for rejecting a harmonic signal component from a second input signal. The first harmonic rejecter and the second harmonic rejecter are connected in parallel to reject an image signal component from the first input signal and the second input signal. Thus, the RF receiver can reject the harmonic signal and the image signal without using an external element.

Abstract: A mixer is provided. The transconductance stage receives an input signal through an input node and outputs an output signal through an output node. The transconductance stage includes a first transistor coupled between the output node and a first power node, having a first gate coupled to the input node, and operating in a saturation region, a second transistor coupled to the first power node, having a second gate coupled to the input node, and operating in a sub-threshold region, a first biasing circuit providing a first bias voltage, and a third transistor coupled between the output node and the second transistor, and having a third gate coupled to the first bias voltage. The switching quad is coupled to the output node and generates a translation current according to the output signal. The transimpedance amplifier transforms the translation current to a corresponding voltage.

Abstract: Regarding N-channel first transistor and a P-channel second transistor, their first terminals are connected to each other and their second terminals are connected to each other. Regarding third transistor and a fourth transistor, their first terminals are also connected to each other and their second terminals are also connected to each other. For the first transistor through the fourth transistor, a first capacitor through a fourth capacitor used for coupling are provided. A first impedance element through a fourth impedance element are provided in a path where a bias voltage is applied to the first transistor through the fourth transistor. A fifth capacitor is provided between the first terminals of the first-fourth transistors and a first input terminal. A fifth impedance element and a sixth impedance element are provided as differential pair loads.

Abstract: A circuit includes an input terminal adapted to receive an input voltage, a MOSFET having its drain terminal and its source terminal connected together, a first switching arrangement configured to be controlled by a first clock signal and adapted to selectively couple the gate terminal to the input terminal, and a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal and adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.

Abstract: An RF squarer circuit comprises a first RF multiplier and a first variable gain transimpedance amplifier (TIA). The first RF multiplier receives an RF input signal RFIN and provides a first output current. The first TIA receives the first output current as an input. The first TIA provides an output voltage VOUT.

Abstract: A multiplier is provided, for example, for use as a mixer in a modulator of a radio frequency transmitter. The multiplier multiplies a first alternating signal of constant amplitude by a second signal, for example, in the form of a carrier wave from a local oscillator. The multiplier comprises a transconductance stage for converting the first signal to a differential output current and a current switching stage for switching the differential output current in accordance with the second signal. The transconductance stage comprises a plurality of offset pairs of transistors, whose inputs and outputs are connected in parallel. The switching stage comprises cross-coupled pairs of transistors which, together with the transconductance stage, form a Gilbert cell. The relative gains of the transistors of each offset pair are such that a minimum in the third harmonic distortion characteristic of the multiplier occurs substantially at the amplitude of the first signal.

Abstract: An embodiment is directed to a zero IF down converter circuit. The circuit comprises a voltage-to-current converter, a mixer, and a suppression circuit. The voltage-to-current converter converts an RF voltage signal to an RF current signal. The mixer changes the frequency of the current signal to a lower frequency current signal. The suppression circuit removes a lower frequency distortion component from the RF current signal before sending the RF current signal to the mixer.

Abstract: A circuit arrangement for signal mixing. One embodiment provides a circuit arrangement for mixing an input signal with at least one carrier signal. The circuit arrangement includes a current source and a current sink. The current source and the current sink have a mixer core coupled between them which provides cross-coupling between mixer input connections and mixer output connections.

Abstract: A mixer includes a magnetoresistive effect element, a magnetic field applying unit, and an impedance circuit. The magnetoresistive effect element includes a fixed magnetic layer, a free magnetic layer, and a nonmagnetic spacer layer disposed between the fixed magnetic layer and the free magnetic layer, is operable when a first high-frequency signal and a second high-frequency signal as a local signal are inputted, to multiply the first high-frequency signal and the second high-frequency signal according to a magnetoresistive effect to generate a multiplication signal. The magnetic field applying unit applies a magnetic field to the free magnetic layer. The impedance circuit has a higher impedance for the multiplication signal than an impedance for the first high-frequency signal and the second high-frequency signal and is disposed between an input transfer line, which transfers the first high-frequency signal and the second high-frequency signal, and the magnetoresistive effect element.