Abstract: A circuit and a method for implementing frequency tripled I/Q signals are proposed, including receiving two input I/Q signals through frequency multipliers so as to generate two frequency multiplied signals and mixing the input I/Q signals and the corresponding frequency multiplied signals through mixers for generating and outputting two I/Q signals with a frequency three times that of the input I/Q signals. The invention eliminates the requirement for high amplitude of the input signals as in the prior art and has lower power consumption and broader bandwidth and can be used as high frequency signal sources in any single chip processes.

Abstract: In a mixer circuit, addition of analog signals by capacitive coupling is used and square-law characteristics of the drain current of a MOS transistor operating in a saturated region are used. With this configuration, the voltage and power of the mixer circuit can be reduced.

Abstract: A method (1300) is provided for generating one or more waveforms (130, 140). The method includes: generating a first toggle signal (1130, 1330) in response to a clock signal (1110), the first toggle signal having one of a first positive shape, a null shape, and a first negative shape for each cycle of the clock signal; multiplying the first toggle signal by a first coefficient signal to create a first intermediate signal (1440); generating a second toggle signal (1140, 1330) in response to the clock signal, the second toggle signal having one of a second positive shape, the null shape, and a second negative shape for each cycle of the clock signal; multiplying the second toggle signal by a second coefficient signal to create a second intermediate signal (1440); and generating a first output signal (1170) by adding the first intermediate signal and the second intermediate signal together (1350).

Abstract: An upconverter has a low noise amplifier, a two port mixer and an antenna. The two port mixer comprises a first port to receive from the low noise amplifier an amplified input signal to be upconverted and a second port to receive a local oscillator signal and to output the amplified, upconverted signal at upper and lower sideband frequencies. The low noise amplifier is coupled to the first port; and the antenna is coupled to the second port.

Abstract: An apparatus and method is disclosed to calculate the actual received desired channel power from the downstream transmit power of a Cable Modem Termination System (CMTS) when operating at the nominal line voltage and/or at the normal room temperature as per the DOCSIS specification. A Set-top Device produces a Downstream Power Management (DPM) gain measurement signal having a known power level. The Set-top Device embeds the DPM gain measurement signal onto a received downstream multi-channel communication signal. After embedding the DPM gain measurement signal onto the downstream multi-channel communication signal, the Set-top Device downconverts the combined DPM gain measurement signal and downstream multi-channel communication signal to recover one or more communication channels containing information of a broadcast.

Abstract: A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. In the physical quantity detection circuit (12), an analog-to-digital converter (104) converts an analog sensor signal (Ssnc) to a digital sensor signal (Dsnc). A digital filter (100) attenuates a frequency component of the digital sensor signal (Dsnc) that is higher than a predetermined cutoff frequency. A multiplier (106) multiplies a digital sensor signal (Dps) having passed the digital filter (100) by a digital detection signal (Ddet) to detect a digital physical quantity signal (Dphy).

Abstract: A monolithic substrate contains an integrated circuit comprising an amplifier having input and output, a mixer and a hybrid coupler for coupling the amplifier to the mixer. Metallic pads on the substrate are connected to each of two ports of the coupler and separate metallic pads are also connected to each of the input and output of the amplifier. The metallic pads allow the amplifier and mixer to be separately tested by a probe and the input or the output of the amplifier to be selectively connected to the mixer to enable the circuit to operate either as a receiver or transmitter. Alternatively, connections between the mixer and both input and output of the amplifier may be preformed and one of the connections subsequently severed depending on whether the circuit is to operate in receive or transmit mode.

Abstract: A signal transformation arrangement comprises a first input tap (1) to receive a first input signal (IN_P), a first output terminal (3) to provide a first output signal (OUT_P) and a first coupling circuit (10) which couples the first input tap (1) to a first energy storing device (11) depending on a first clock signal (CLK—1) and which couples the first energy storing device (11) to the first output terminal (3) depending on a first inverted clock signal (XCLK—1). The signal transformation arrangement further comprises a second coupling circuit (20) which couples the first input tap (1) to a second energy storing device (21) depending on a second clock signal (CLK—2) and which couples the second energy storing device (21) to the first output terminal (3) depending on a second inverted clock signal (XCLK—2).

Abstract: Disclosed is a multiplier circuit including first and second squaring circuits comprising first and second differential MOS transistors respectively connected in cascode to first and second diode-connected MOS transistors. The first squaring circuit receives a differential sum voltage of a first input voltage and a second input voltage. The second squaring circuit receives a differential subtraction voltage of the first input voltage and the second input voltage. Outputs of the first and second squaring circuits are first and second terminal voltages of the first and second diode-connected MOS transistors. A differential voltage between the first and second terminal voltages corresponds to the product of the first and second input voltages.

Abstract: A system that includes: multiple transistors that comprise a first transistor that is maintained in a weak inversion state; wherein sources of the multiple transistors are coupled to a low current source; wherein drains of the multiple transistors are coupled to a voltage supply source; a first amplifier that has a positive input, negative input and an output; wherein the positive input receives an input voltage; wherein the negative input is coupled to a source of the first transistor; wherein the output is coupled to a gate of the first transistor and to a multiplication and subtracting circuit; a multiplication and subtraction circuit that is coupled to the first amplifier and outputs an output signal that equals a difference between the input voltage and a product of a current reduction variable and a voltage reduction signal; wherein the voltage reduction signal is associated with a current reduction factor; wherein the output signal is provided to a second transistor that is maintained in weak inversion

Abstract: A down-converter mixer may include a Gilbert cell, two transistor differential pairs, which drive output loads, and transistors defining respective tail generators coupled to common source nodes of the differential pairs. The transistors may receive a radio-frequency signal mixable with a local oscillator signal applied symmetrically between the differential pairs to produce in the loads, a signal deriving from down-converting the radio-frequency signal of an amount given by the frequency of the local oscillator signal. An inductor may be coupled to the common source nodes and which resonates with a capacitive load also coupled to the common source nodes, increases the impedance of such common nodes at the local oscillator signal frequency. The inductor may be in an open loop configuration in the absence of feedback from the mixer, and thus may be active both against noise at radio-frequency and distortion at low frequency.

Abstract: The mixer includes mixers constructed with variable gain amplifiers having two transistor pairs Qp+/Qp? and Qn+/Qn? to have a predetermined gain by using LO+ and LO? signals; and LO bias circuits connected to have bias voltages different from each other with respect to the LO+ and LO? signals of the mixers and share an input signal.

Abstract: A signal processor includes a frequency converter of the multiphase type. A first phase mixer (SWC1, TIS1) has a pair of switches (M11, M12). A second phase mixer (SWC2, TIS2) also has a pair of switches (M21, M22). The pair of switches of the first phase mixer and the pair of switches of the second phase mixer have a joint common switch node (CN1). A local oscillator generates an individual mixer driver signal (MD1+, MD1?, MDQ+, MDQ?) for each switch (M11, M12, M21, M22) in the aforementioned pairs. Each individual mixer driver signal comprises periodically occurring pulses, which are phase shifted with respect to the periodically occurring pulses in the other individual mixer driver signals. Preferably, there is substantially no overlap between the periodically occurring pulses in the individual mixer driver signals.

Abstract: A technique wherein when signals, the modulation schemes of which are different, are to be combined, performing the peak suppression using amounts of the respective modulation schemes can effectively reduce the PAPR of a resulting combined signal. A peak suppressing method for use in a peak suppressing circuit, which combines input signals of different modulation schemes in a time domain to provide a combined signal, comprises detecting, as a peak, that portion of the combined signal which excesses a threshold value to generate a peak signal in accordance with the peak; converting the peak signal into a frequency domain signal and then dividing it into signals originating from the input signals to use these input-signal-originated signals as respective suppression signals; and adding, to the input signals, the suppression signals having different suppression amounts for the respective modulation schemes, thereby performing the peak suppression.

Abstract: A circuit and a method for implementing frequency tripled I/Q signals are proposed, including receiving two input I/Q signals through frequency multipliers so as to generate two frequency multiplied signals and mixing the input I/Q signals and the corresponding frequency multiplied signals through mixers for generating and outputting two I/Q signals with a frequency three times that of the input I/Q signals. The invention eliminates the requirement for high amplitude of the input signals as in the prior art and has lower power consumption and broader bandwidth and can be used as high frequency signal sources in any single chip processes.

Abstract: A two-terminal semiconductor device is formed on a semiconductor substrate. Two wiring patterns are respectively connected to terminals of the semiconductor device, and two electrode pads are respectively connected to the wiring patterns for connecting a signal input/output circuit formed on a separate substrate. Two parallel wiring patterns are respectively connected to the wiring patterns, and two reactance-circuit connection electrode pads are respectively connected to the parallel wiring patterns for electrically connecting a reactance circuit formed on the separate substrate separately from the signal input/output circuit.

Abstract: A signal generation system suitable for use in a radar system comprises a local oscillator (LO) and an intermediate frequency (IF) oscillator, wherein the IF oscillator is a Direct Digital Synthesiser (DDS), and the LO is a free running oscillator not itself locked to another oscillator but which acts as a clock reference for the DDS and is the highest frequency oscillator in the system. The LO may also act as a reference for a receive chain digitiser. The invention exploits phase noise advantages of a free running oscillator at some distance from the carrier whilst maintaining coherency with other system components. The system typically finds application in FMCW radars.

Abstract: Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.

Abstract: Regarding N-channel first transistor and a P-channel second transistor, their first terminals are connected to each other and their second terminals are connected to each other. Regarding third transistor and a fourth transistor, their first terminals are also connected to each other and their second terminals are also connected to each other. For the first transistor through the fourth transistor, a first capacitor through a fourth capacitor used for coupling are provided. A first impedance element through a fourth impedance element are provided in a path where a bias voltage is applied to the first transistor through the fourth transistor. A fifth capacitor is provided between the first terminals of the first-fourth transistors and a first input terminal. A fifth impedance element and a sixth impedance element are provided as differential pair loads.

Abstract: A passive mixer includes a transconductance amplifier having a source degeneration capacitance. The transconductance amplifier has an input for receiving an input signal and an output for outputting a current signal. A multiplier is provided for mixing a local oscillator signal with the current signal so as to provide an output signal at an output of the passive mixer. A capacitive load is connected to the output of the passive mixer.

Abstract: Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: Heterodyne mixer comprising: a divider of a signal RF for generating a signal RF1 and a signal RF2; a reference means comprising a local oscillator generating a reference signal LO; a second division means for dividing the reference signal into a reference signal LO1 and into a reference signal LO2; at least two mixture cells mixing on the one hand the signal RF1 with the reference signal LO1 so as to create an intermediate signal IF1 and on the other hand the signal RF2 with the reference signal LO2 so as to create an intermediate signal IF2; a combiner for recombining the intermediate signal IF1 and the intermediate signal IF2 into an intermediate output signal IF. The mixer comprises at least one configurable phase-shifting device for phase-shifting a signal via a remote control.

Abstract: A signal adjusting circuit is provided. The signal adjusting circuit includes a first operational unit, a second operational unit, an auto-gain controller (AGC), a first clamp circuit, and a second clamp circuit is provided. The first operational unit performs an operation to a digital signal and a first gain value, to obtain a first adjusting signal. The second operational unit performs an operation to the digital signal and a second gain value, to obtain a second adjusting signal. The AGC generates a third gain value according to the first adjusting signal. The first clamp circuit receives and restricts the third gain value between a first upper limit and a first lower limit for generating the first gain value. The second clamp circuit receives and restricts the third gain value between a second upper limit and a second lower limit for generating the second gain value.

Abstract: A square cell comprises first and second bipolar transistors each having an emitter, collector and base, the bases of the transistors being connected for receiving an input voltage, and first and second resistors in series with the first and second bipolar transistors respectively and with a source of reference voltage. The collectors are commonly connected to an output node to supply an output current having a component proportional to the square of the input voltage. Enhanced square law conformance may be produced by adding further pairs of bipolar transistors to the cell, with offset voltage elements coupled between bases of successive transistors on each side of the cell.

Abstract: Electronic devices are provided with ejectable component assemblies. The ejectable component assembly may include a tray that can be loaded with one or more removable modules, wafers coupled to circuit boards, cages and retaining plates to assist in retaining the tray within the assembly. The ejectable component assembly may include springs operative to engage detents in the tray to retain the tray in the assembly. The ejectable component assembly may include a tray ejector mechanism for ejecting the tray from the assembly.

Abstract: A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.

Abstract: A mixer includes: a magnetoresistive effect element including a fixed magnetic layer, a free magnetic layer, and a nonmagnetic spacer layer disposed between the fixed magnetic layer and the free magnetic layer; and a magnetic field applying unit that applies a magnetic field to the free magnetic layer. The mixer is operable, when a first high-frequency signal and a second high-frequency signal as a local signal are inputted, to multiply the first high-frequency signal and the second high-frequency signal using the magnetoresistive effect element and to generate a multiplication signal. A frequency converting apparatus includes the mixer and a filter operable, when a higher frequency and a lower frequency out of frequencies of the first high-frequency signal and the second high-frequency signal are expressed as f1 and f2 respectively, to pass one out of a frequency (f1+f2) and a frequency (f1-f2) out of the multiplication signal.

Abstract: A conversion mixer includes a mixing circuit, a duplicating circuit and a loading circuit. The mixing circuit receives a couple of first input signals and a couple of second input signals and mixes the couple of first input signals with the couple of second input signals to output a couple of mixed signals. The duplicating circuit coupled to the mixing circuit receives the couple of mixed signals and duplicates the couple of mixed signals to output a couple of duplicated signals. The loading circuit coupled to the duplicating circuit receives the couple of duplicated signals and outputs a couple of output signals according to the couple of duplicated signals.

Abstract: A mixer includes a first field effect transistor (FET) having a gate that receives a first signal of a balanced local oscillator (LO) signal, a first source/drain coupled to a ground voltage, and a second source/drain; and a second FET having a gate that receives a second signal of the balanced LO signal, a first source/drain that floats, and a second source/drain connected to the second source/drain of the first FET to form a mixing node, the second signal being out of phase with the first signal. A diplexer is connected between the mixing node and each of a radio frequency (RF) port and an intermediate frequency (IF) port. A first LO leakage caused by the first FET is substantially canceled by a second LO leakage caused by the second FET at the mixing node.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: A third-order transconductance (gm3) cancellation is utilized to obtain a highly linear mixer. Transistors obtain good linearity with complementary gm3 values. The transistor thus obtained can be operated in a wide bandwidth and is applicable to various frequency specifications of systems, like Bluetooth, wireless LAN, Ultra-Wide Band (UWB), etc. Then the transistors are applied to design a transconductance-stage input of the mixer. Hence, the present invention can be widely applied to receiver modules and be realized with a low-cost CMOS transistor.

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.

Abstract: A mixer (114) includes an input amplifier (620) and a barrel shifter (640). The input amplifier (620) has an input for receiving an input signal, and first through fourth output terminals respectively providing first through fourth current signals. The barrel shifter (640) has first through fourth input terminals for respectively receiving the first through fourth current signals, first through fourth control terminals for respectively receiving first through fourth clock signals, and first through fourth output terminals for respectively providing positive and negative in-phase output signals and positive and negative quadrature output signals.

Abstract: A mixer circuit includes: a rat race circuit including a ring-shaped transmission line with a first terminal, a second terminal, a third terminal, and a fourth terminal, the first to fourth terminals being disposed, in that order, clockwise along the transmission line and equally spaced ?LO/4 from one another, except that the first terminal is spaced 3*?LO/4 from the fourth terminal, where ?LO is the wavelength of the LO signal applied to the mixer circuit; an LO terminal connected to the first terminal; a first diode and a second diode connected in the same polarity to the second terminal and the fourth terminal, respectively; and an RF terminal and an IF terminal both connected to the third terminal. The frequency of the LO signal is one-half of the frequency of the RF signal applied to the mixer circuit.

Abstract: Disclosed is a multiplier circuit including first and second squaring circuits comprising first and second differential MOS transistors respectively connected in cascode to first and second diode-connected MOS transistors. The first squaring circuit receives a differential sum voltage of a first input voltage and a second input voltage. The second squaring circuit receives a differential subtraction voltage of the first input voltage and the second input voltage. Outputs of the first and second squaring circuits are first and second terminal voltages of the first and second diode-connected MOS transistors. A differential voltage between the first and second terminal voltages corresponds to the product of the first and second input voltages.

Abstract: A balun circuit includes a first CPW line 11, a second CPW line 12a, and a third CPW line 12b that serve as signal input/output ports; a first CPS line 14a that is a differential transmission line, the first CPS line 14a relaying the first CPW line 11 to the second CPW line 12a; a second CPS line 14b that is a differential transmission line, the second CPS line 14b relaying the first CPW line 11 to the third CPW line 12b; and at least one connection section that connects grounded conductors of each of the first CPW line 11, the second CPW line 12a, and the third CPW line 12b.

Abstract: An up-conversion mixer includes a first and a second hybrid couplers and a first and a second traveling-wave mixers is disclosed. The first hybrid coupler receives an input intermediate frequency (IF) signal and produces a first IF signal (IF1) and a second IF (IF2) signal, the second IF signal being 180 degree off-phase compared to the first IF signal. The first traveling-wave mixer mixes the first IF signal (IF1) and a first local oscillator (LO1) signal to produces a first radio frequency signal (RF1). The second traveling-wave mixer mixes the second IF signal (IF2) and a second local oscillator signal (LO2) to produces a second RF signal (RF2). The second hybrid coupler to combines the first RF signal and the second RF signal to produce an output RF signal. The use of the traveling-wave mixers allow for a wide bandwidth operation of the up-conversion mixer.

Abstract: An image rejection mixer including a first and a second hybrid couplers and a first and a second traveling-wave mixers is disclosed. The first hybrid coupler divides an input radio frequency (RF) signal to a first RF signal and a second RF signal, the second RF signal being in quadrature to the first RF signal. The first traveling-wave mixer mixes the first RF signal and a local oscillator (LO) signal to produces a first intermediate frequency (IF) signal. The second traveling-wave mixer mixes the second RF signal and the local oscillator signal to produces a second IF signal. The second hybrid coupler combines the first IF signal and the second IF signal to produce an upper sideband of the IF signals and a lower sideband of the IF signals. The use of the traveling-wave mixers allow for a wide bandwidth operation of the image rejection mixer.

Abstract: Methods, systems, and apparatuses, for down-converting and up-converting an electromagnetic signal. In embodiments the invention operates by receiving an EM signal and recursively operating on approximate half cycles of the carrier signal. The recursive operations can be performed at a sub-harmonic rate of the carrier signal. The invention accumulates the results of the recursive operations and uses the accumulated results to form a down-converted signal. In embodiments, up-conversion is accomplished by controlling a switch with an oscillating signal, the frequency of the oscillating signal being selected as a sub-harmonic of the desired output frequency. When the invention is being used in the frequency modulation or phase modulation implementations, the oscillating signal is modulated by an information signal before it causes the switch to gate the bias signal. The output of the switch is filtered, and the desired harmonic is output.

Abstract: A mixer has a cascode configuration. With the configuration, the mixer is operated under a low voltage. And, the present invention has a good circuit gain, a good broadband operation and a low power consumption. The mixer can be realized with a CMOS transistor. Hence, the present invention is fit to be applied in a receiver module.

Abstract: A mixer circuit includes: a rat race circuit including a ring-shaped transmission line with a first terminal, a second terminal, a third terminal, and a fourth terminal, the first to fourth terminals being disposed, in that order, clockwise along the transmission line and equally spaced ?LO/4 from one another, except that the first terminal is spaced 3*?LO/4 from the fourth terminal, where ?LO is the wavelength of the LO signal applied to the mixer circuit; an LO terminal connected to the first terminal; a first diode and a second diode connected in the same polarity to the second terminal and the fourth terminal, respectively; and an RF terminal and an IF terminal both connected to the third terminal. The frequency of the LO signal is one-half of the frequency of the RF signal applied to the mixer circuit.

Abstract: A mixer (114) includes a phase clock generator (404), a latch (420), and a multiplier (118). The phase clock generator (404) provides a plurality of phase clock signals. The latch (420) is coupled to the phase clock generator (404) via a first plurality of conductors (410) and provides a plurality of resynchronized phase clock signals. The multiplier (118) is coupled to the latch (420) via a second plurality of conductors (430) and mixes an input signal using the plurality of resynchronized phase clock signals to provide a mixed output signal. The second plurality of conductors (430) is characterized as having a lower end-to-end impedance than an end-to-end impedance of the first plurality of conductors (410).

Abstract: A subharmonic mixer circuit having an input stage (52) and a current modulating stage (64) is disclosed. The input stage (52) receives an RF input signal (RF+, RF?) at a first frequency and generates output currents (i1, i2) varying in dependence upon the Rf input signal. The current modulating stage (64) comprises a first transistor (Q3) for receiving a first local oscillator signal (LOO) respective and a second transistor (Q4) for receiving a second local oscillator signal (LOI 80), 180 degrees out of phase with the first local oscillator signal, such that a modulating current signal (i0), having twice the local oscillator frequency, is superimposed onto the output currents.

Abstract: Provided is a mixer for use in a direct conversion receiver. The mixer includes Field Effect Transistors (FETs), a current source (IBias), two load resistors (RLoad), another FET, and two inductors L1 and L2. The FET M21 constitutes a current bleeding circuitry and the other components except for the two inductors L1 and L2 constitute a so-called Gilbert cell mixer.

Abstract: A circuit includes a multi-tanh cell having a common-emitter node to receive a bias current, and an extra transistor coupled to the common-emitter node to dynamically divert a portion of the bias current from the multi-tanh cell. The circuit may be arranged as a multiplier with an input network arranged to apply two or more input signals to the multi-tanh cell. A second multi-tanh cell with an extra transistor may be arranged in a feedback loop where the outputs of the first and second multi-tanh cells are coupled together at an integrating node. A buffer drives the final output and feedback cell to cancel nonlinearities in the multiplier cells.

Abstract: An analog real-time signal processing device and method are presented. The device is configured to perform electrical signal processing. The device comprises an electronic circuit including at least one basic unit of electrodes, the basic unit being configured to be sensitive to an external field, such as input photon flux, indicative of a first input signal to cause emission of charged particles and configured to define at least one electrical input for a second input signal and one electrical output, thereby providing the electrical output in the form of an approximation of a product of the first and second input signals.

Abstract: Methods, systems, and apparatuses, for down-converting and up-converting an electromagnetic signal. In embodiments the invention operates by receiving an EM signal and recursively operating on approximate half cycles of the carrier signal. The recursive operations can be performed at a sub-harmonic rate of the carrier signal. The invention accumulates the results of the recursive operations and uses the accumulated results to form a down-converted signal. In embodiments, up-conversion is accomplished by controlling a switch with an oscillating signal, the frequency of the oscillating signal being selected as a sub-harmonic of the desired output frequency. When the invention is being used in the frequency modulation or phase modulation implementations, the oscillating signal is modulated by an information signal before it causes the switch to gate the bias signal. The output of the switch is filtered, and the desired harmonic is output.

Abstract: A mixer capable of detecting or controlling a common mode voltage thereof, includes at least: a mixing module for mixing a first set of differential signals and a second set of differential signals to generate at least one mixed signal; and a compensation module for compensating at least one operation point of the mixing module.

Abstract: Mixer circuits with direct-current bias are disclosed. An example embodiment of such a mixer includes a first differential transistor pair and a second differential transistor pair. The example mixer also includes first and second local oscillator signal terminals and first and second mixed signal terminals. The first and second local oscillator signal terminals are coupled with the first and second differential transistor pairs. The first mixed signal terminal is coupled with the first differential pair and the second mixed signal terminal is coupled with the second differential pair. The mixer further includes first and second baseband signal terminals, where each baseband signal terminal is coupled with the first differential pair and the second differential pair. The mixer still further includes a first current source and a second current source.