Abstract: A push-pull switch including a first N-channel MOS transistor, the drain-source path of which is connected between a high voltage terminal and an output terminal, a first resistor connected between the gate of the first transistor and the high voltage, a diode having its anode connected to the output terminal and its cathode connected to the gate of the first transistor, a second N-channel MOS transistor having its drain connected to the cathode of the diode, its source connected to a reference potential, and its gate connected to a control terminal, and a second resistor connected between the gate of the second transistor and the output terminal.

Abstract: An integrated circuit output driver provides high speed communication, such as between integrated circuits in spite of appreciable interconnection capacitance. The output driver reduces the current sourced or sunk from a circuit node during its switching as its voltage approaches power supply or ground voltages. This reduces the voltage swing and ringing at the circuit node during high speed communication, thus reducing switching time. The output driver provides full voltage swing under quiescent conditions, preserving minimum leakage currents in steady state.

Abstract: A buffer circuit having an input and output terminals includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.

Abstract: An analog switch includes two complementary MOS field-effect transitors (10, 12) whose source-drain circuits are located in parallel between the input terminal (18) and the output terminal (20) of the switch. A control signal for controlling the switch is applied to the gate of the MOS field-effect transistor (12) of the one channel type directly and to the gate of the MOS field-effect transistor (10) of the other channel type via a negator (16). Between the input terminal (18) and output terminal (20) of the switch the series source-drain circuits of three MOS field-effect transistors (22, 24, 26) are inserted, whereby the MOS field-effect transistor (24) located in the middle of the series circuit has a channel type opposite that of the other two MOS field-effect transistors (22, 26). The gates of all MOS field-effect transistors of the other channel type are each interconnected.

Abstract: A semiconductor switching device has a first semiconductor element, a second semiconductor element, and a comparator. The first semiconductor element has a first main electrode, a second main electrode, and a control electrode. The second semiconductor element has a first main electrode connected to the first main electrode of the first semiconductor element, a control electrode connected to the control electrode of the fist semiconductor element, and a second main electrode connected to a circuit that consists of a resistor and a constant current source that are connected in parallel with each other. The comparator compares potentials of the second main electrodes of the first and second semiconductor elements with each other. If the potential of the second main electrode of the first semiconductor element exceeds the potential of the second main electrode of the second semiconductor element, it is determined that there is a break in the load.

Abstract: A semiconductor device capable of executing size comparison operations on a plurality of data at high speed and in real time and using simple circuitry. An inverter circuit group is used containing a plurality of inverter circuits constructed using neuron MOS transistors. Predetermined signal voltages are applied from the exterior to the first input gates of the inverter circuits, and the output signals of all inverters contained in the inverter circuit group are inputted into a first logical arithmetic circuit and a second logical arithmetic circuit, and the output signal of the first logical arithmetic circuit is inputted into a third logical arithmetic circuit controlled by the output signal of the second logical arithmetic circuit, and the output of the third logical arithmetic circuit is fed back to the second input gates of the inverter circuits contained in the inverter circuit group.

Abstract: The present invention is composed of: positive and negative control power sources P and N, first and second semiconductor device groups A and B in which a plurality of semiconductor devices 12 and 13 and also 15 and 16 are series-connected to these positive and negative control power sources P and N, switching signal source 17 that supplies ON/OFF control signals to semiconductor devices 12 and 13 and also 15 and 16 of these first and second semiconductor device groups A and B, and delay circuits 18 and 19 that delay for a specified time the ON/OFF control signals supplied to any one of semiconductor devices 12 and 13 and also 15 and 16 of first or second semiconductor device groups A and B from this switching signal source 17.

Abstract: A transient current producing method, a transient producing circuit, a related semiconductor integrated circuit and logical circuit are provided, which are capable of preventing a flow of a steady state current, consuming little power and switching at high speed. A transient current occurring at a time of switching of a CMOS circuit is amplified to a predetermined value. This amplification prevents the flow of the steady state current in the circuit. The transient current occurring at the time of switching of the CMOS circuit is converted to a transient voltage. The conversion of the transient current to the transient voltage having a predetermined value and the amplification of the transient current allow a simple configuration of the circuit. The transient current is a feedthrough current which flows from a terminal of a power supply to a ground at the time of switching of the CMOS circuit.

Abstract: A high-frequency switch for blocking or transmitting a high frequency input signal. The switch includes a common-base transistor having an emitter, base, and collector, the emitter being connected to an input node and the base being connected to a power rail that is preferably ground. The input node is coupled to the input signal. The present invention utilizes a shunt having a switching element with closed and open states to route the input signal either to the collector of the common-base transistor or to the power rail. The switching element connects the input node to the power rail in the closed state and isolates the input node from the power rail when the switching element is in the open state. The open and closed states are selected by the application of a control signal to the switching element. A bias circuit sets the input node to be at a first bias potential when the switching element is in the open state and a second bias potential when the switching element is in the closed state.

Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.

Abstract: A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

Abstract: A signal transition accelerating driver circuit firstly charges a signal line to a precharging level, thereafter, maintains the precharging level or discharges the signal line depending upon the potential level of the data/bus status signal, for this reason, any gate circuit is required, and the circuit configuration is simple.

Abstract: An active drive circuit for high power IGBTs provides optimized switching performance for both turn-on and turn-off by incorporating a three-stage action to improve performance characteristics. The gate drive circuit includes a semiconductor switch such as a MOSFET connected in series with a low resistance gate turn-on resistor between the supply line and the gate input line, and a parallel connected bipolar transistor. During the first and third stages of turn-on, the MOSFET switch is turned on to provide rapid charging of the gate, whereas during the second stage the bipolar transistor is turned on to provide a controlled level of current charging of the gate. Similarly, a switch such as an MOSFET is connected in series with a low resistance gate turn-off resistor between the turn-off supply voltage line and the gate input line, and a bipolar transistor is connected in parallel therewith across the supply line and the gate input line.

Abstract: An output buffer for a line driver uses transmission gates for active termination. A large p-channel driver is pulsed on during a low-to-high output transition, but this driver is turned off once the output voltage reaches a threshold. A feedback circuit includes a sensing inverter that has its input connected to the output node. The sensing inverter causes the gate of the p-channel driver to be driven high once the output swings past the threshold. A similar n-channel driver transistor is pulsed on during a low-going output transition but is disabled by a feedback circuit that senses the output voltage falling below a threshold. A pullup transmission gate is also connected between the output and the power supply, while a pulldown transmission gate is connected between the output and ground. Each transmission gate contains a p-channel and a n-channel transistor in parallel.

Abstract: A transfer gate or pass gate circuit for transferring logic signals between nodes for a range of available high-potential supply levels. The primary transfer gate is designed to protect against potentials that either exceed either a high-potential or a low-potential level or that undershoot such potential levels. For overshoot (overvoltage) tolerance, this is achieved by coupling a NMOS transistor in parallel with a pair of PMOS transistors that are coupled in series. All three transistors are located between two nodes, either of which can be the input or the output of the transfer gate. The NMOS transistor is designed to be larger than the PMOS transistors and carries most of the transfer capability. The smaller PMOS transistors are designed to eliminate potential drops that would otherwise occur with a single NMOS transistor or with a complementary pair of transistors.

Abstract: A power switching device which decreases both surge voltage and switching loss. As the inductor is connected to the emitter electrode of the IGBT element, the potential of the emitter electrode changes in the direction in which the IGBT element maintains the ON state with the attenuation of the main current when the IGBT element turns OFF from ON. Furthermore, as the inductor is included in the path of the OFF driving current for bringing the IGBT element to OFF, the OFF driving current once raises and then decreases. As a result, because the transition from ON to OFF calmly proceeds, the occurrence of the surge voltage is suppressed. On the other hand, since the inductor is not included in the path of the ON driving current, the transition from OFF to ON of the IGBT element is rapidly made. Accordingly, the switching loss occurring in the transition period is decreased. The decrease in the surge voltage and the decrease in the switching loss are compatibly realized.

Abstract: A high-speed current switch has complementary switching stages for collectively producing a square-wave output current. Spurious currents and charging delays caused by intrinsic capacitances in one stage substantially cancel those in the other stage.

Abstract: Methods and circuitry for implementing output buffers with low voltage CMOS transistors capable of handling signal overshoot and undershoot conditions. The circuit detects the level of the signal at an external terminal and adjusts the voltage at the gate terminals of the output transistors connecting to the external terminal in response thereto, such that oxide stress conditions are alleviated.

Abstract: An input circuit (20) and a method for protecting the input circuit (20) from positive and negative overvoltages. The input circuit (20) includes an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (12), a P-channel MOSFET (13), a Zener diode (21), and a diode-connected transistor (22). The P-channel MOSFET (13) protects the N-channel MOSFET (12) from negative overvoltages. The Zener diode (21) and the diode-connected transistor (22) protect the N-channel MOSFET (12) from positive overvoltages. In addition, the Zener diode (21) protects the P-channel MOSFET (13) from positive overvoltages.

Abstract: An electronic relay for use with an ultrasonic transducer. The electronic relay selectively couples the ultrasonic transducer to an electronic circuit. The transducer includes an input/output port for receiving excitation signals from the circuit and for transmitting echo signals back to the circuit. The electronic relay comprises a solid state switch and a leakage control circuit. The solid state switch is connected between the transducer and the electronic circuit. The switch is responsive to an actuation signal from the circuit for opening and closing the switch. The leakage control circuit is coupled to the switch and functions to control leakage current when the switch is open so as to electrically isolate the transducer from the electronic control circuit.

Abstract: The present invention provides improved output buffers for use on IC Chips. These output buffers incorporate a compensation circuit for compensating the performance characteristics of transistors included in the output buffers. The compensation circuit determines whether the output buffer is operating at a desired slew-rate. In response to this determination, the compensation circuit supplies a compensation voltage or voltages. The compensation voltages control a variable quantity of power delivered by a voltage controlled power source (VCPS). By increasing or reducing this power, the slew-rate of the output buffers are respectively increased or reduced. The compensation voltages maintain this slew-rate within narrow tolerances. This allows the improved output buffers of the present invention to meet very narrow input tolerances of circuitry coupled to receive signals from the IC Chip.

Abstract: An electrical switching device including a switch having a control terminal, a control circuit coupled between a first voltage source terminal and a second voltage source terminal and a control signal input coupled to receive a binary switching control signal.

Abstract: A trigger circuit for a field-effect-controlled power semiconductor component has a controllable gate resistor for the power semiconductor component, which has low impedance in a normal situation and is switched to high impedance in the event of a short circuit. As a result, the turn-on time in the normal situation is shortened, and limiting the gate-to-source voltage of the power semiconductor component in the short-circuit situation is made possible.

Abstract: A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount. The pull-down circuit is a transistor connected to a low voltage source, which limits the pull-down voltage. Additional transistors are provided to turn on and off the pull-down transistor, with a circuit connected to a fail-safe low voltage source being used to protect these transistors.

Abstract: A bias circuit that generates a dynamic bias voltage for driving low-voltage transistors in an output buffer that interfaces with high-voltage signals is disclosed. Various circuits have been devised to ensure that no transistor in the bias and the output buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the output signal voltage may swing well beyond the tolerable voltage levels. This is accomplished with minimal increase in power consumption and without compromising the speed of operation of the output buffer circuit.

Abstract: A pre-driver circuit in an I/O circuit for an integrated circuit performs the combined functions of voltage level shifting, slew rate control, and tri-state capability, in a single circuit to avoid additional delay caused by implementing any combination of these functions in two or more circuits.

Abstract: A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.

Abstract: A transistor output circuit comprises a first insulated gate transistor having a control electrode connected to an input terminal, one main electrode connected to a first diode, and the other main electrode connected to a reference voltage source, and a second insulated gate transistor having a control electrode connected to the input terminal, one main electrode connected to an output terminal, and the other main electrode connected to the reference voltage source. A ratio (W.sub.1 /L.sub.1) of a gate width (W.sub.1) to a gate length (L.sub.1) of the first insulated gate transistor is larger than a ratio (W.sub.2 /L.sub.2) of a gate width (W.sub.2) to a gate length (L.sub.2) of the second insulated gate transistor.

Abstract: An integrated circuit driver drives a differential signal over a communication cable, such as a twisted-pair cable. The integrated circuit driver includes a differential pre-driver that receives an input signal having an about 50% duty cycle and produces an amplified differential signal that swings between a power rail level and a ground level. A signal conditioner circuit receives the amplified differential signal and outputs a conditioned differential signal. The conditioned differential signal swings between the power rail level and an intermediate power level. The integrated circuit driver further includes an output driver that receives the conditioned differential signal that swings between the power rail level and the intermediate power level. The output driver produces a differential output signal that is communicated to the communication cable. The differential output signal has an about zero signal crossing and maintains the about fifty percent duty cycle.

Abstract: A first FET is connected between first and third nodes, a second FET is connected between second and fourth nodes, a third FET is connected between third and fifth nodes and a fourth FET is connected between fourth and fifth nodes. A fifth FET is connected between first and sixth nodes and a sixth FET is connected between second and sixth nodes. The gates of the first, fourth and sixth FETs are connected to a first control terminal and the gates of the second, third and fifth FETs are connected to a second control terminal. A power-supply terminal is connected to the fifth and sixth nodes. The first and second nodes are connected to a common terminal through first and second capacitors, respectively. The fifth and sixth FETs form a pull-up switching circuit. The pull-up switching circuit pulls up the source of an FET in an OFF state to the power-supply voltage and isolates the source of an FET in an ON state from the power-supply voltage.

Abstract: A CMOS circuit prevents feedthrough current and has a small-scaled circuit constitution. An output stage has a P-channel MOS transistor and an N-channel MOS transistor with drains connected to each other to form an output terminal and gates respectively connected to output terminals of first and second series circuits. The first and second series circuits control supply of power and each includes an N-channel MOS transistor and a P-channel MOS transistor with drains connected together to form the output terminal and gates connected together to form an input terminal. A delay circuit receives an input signal and produces a delayed input signal which drives the input terminals of the first and second series circuits. P-channel and N-channel MOS transistors control power potentials applied to sources of the respective P-channel and N-channel MOS transistors of the second and first series circuits and are driven by the input signal which is applied to their gates.

Abstract: Circuits and method for isolating internal nodes of an integrated circuit from external signals applied to I/O terminals of the IC even under no-power conditions are disclosed. The invention senses the most positive voltage level (in case of a p-channel implementation) or the most negative voltage level (in case of an n-channel implementation) at two input or input/output (I/O) pads and uses that voltage to isolate the internal nodes of the integrated circuit from the pad, without requiring the circuit power supply for its operation.

Abstract: A fast insulated gate bipolar transistor (IGBT) driver circuit for trunking waveforms in external defibrillators is provided. An input circuit is provided to receive input signals. An isolation transformer is provided to isolate the output from the input. A biasing circuit is connected to the isolation transformer for biasing the IGBT. In response to the biasing circuitry, the IGBT rapidly switches between operational states to truncate waveforms at any point during the delivery of energy to a patient.

Abstract: A CMOS integrated circuit regulator for mixed mode integrated circuits reduces digital switching noise through use of a clamped dual source follower circuit and a charge reservoir bypass capacitor. Relatively constant current is provided to the CMOS logic during transitions to minimize switching noise.

Abstract: A voltage-controlled transistor drive circuit includes a gate-voltage generating circuit for outputting on and off gate signal voltages in response to an input signal, switching a voltage-controlled transistor by applying the gate voltage to the gate of the voltage-controlled transistor; and a current limiting circuit limiting current flowing from the gate of the voltage-controlled transistor to the gate-voltage generating circuit when the gate-voltage generating circuit outputs an off gate signal voltage.

Abstract: Data-outputting buffer circuit suitable for reducing noise which is generated in an output buffer circuit part when minus electric filed is applied to a data output pad in inputting data is disclosed, including a noise generation restraining part detecting a level of a signal applied to an input/output pad inputting and outputting data for outputting first and second noise generation restraining signals, a pullup transistor having a source connected to the input/output pad and a drain electrode connected to a power voltage terminal, a pulldown transistor serially connected to the pullup transistor with both sources of the pullup and pulldown transistors connected to the input/output pad, first and second driving parts for driving the pullup transistor and the pulldown transistor, and a clamp transistor turned on by the first noise generation restraining signal for restraining increase of substrate bias due to voltage difference between a gate and the source of the pullup transistor.

Abstract: Disclosed is an integrated circuit comprising storage circuits, these circuits themselves comprising insulation transistors to which a determined positive bias voltage may be applied. This bias voltage is determined by means of a first bias circuit. The disclosed circuit comprises a second bias circuit whose time constant in response to a voltage step is smaller than the time constant of the first circuit in response to the same step, this second circuit making it possible to reduce the response time of the first bias circuit.

Abstract: An electrostatic protection circuit in a internal circuit isolated from a substrate bias which protects the internal circuit from static electricity with regard to any of three different sources of bias voltage. An electrostatic protection circuit is constructed for each source of bias voltage so that the internal circuit is protected from static electricity flowing through bonding pads of the isolated circuit. The protective circuit comprises a plurality of NMOS or PMOS transistors for protecting input/output buffers and drivers from the static electricity flowing through the bonding pads. The respective NMOS or PMOS transistors are connected to the respective source voltage terminals and the input/output drivers.

Abstract: An output buffer with pull-up and push-down circuits. The pull-up circuits includes an initial voltage circuit providing an initial voltage to the pull-up terminal of the pull-up driver driving the output of the output buffer. The pull-up circuit also includes a circuit loop insuring that the ability of the pull-up circuit to drive the output terminal to the source voltage does not diminish in the latter half of the pull-up circuit's operation. The push-down circuit also insures that the drive capability of the push-down circuit does not diminish over the latter half of the push-down circuit's operation.

Abstract: A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.

Abstract: A circuit for operating a polyphase DC motor, such as the type having a plurality of "Y" connected stator coils, has circuitry for charging the coils at a rate which will reduce EMI and other noise, while maintaining an acceptable charge rate. The gate of a selected high side driving transistor is charged at a relatively high rate during a ramping phase. During the ramping phase, the gates of the selected transistor is charged to a voltage near the voltage needed to form a channel in the transistor for conduction. After the ramping phase, the gates are charged at a lesser rate in order to control the rate of charging of the stator coils to prevent noise.

Abstract: An additional MOS transistor receiving at its control electrode a signal complementary to that applied to control electrodes of MOS transistors is provided between a power supply node and a control electrode line formed by resistors having a significant resistance and interconnecting respective control electrodes of MOS transistors which are connected in parallel and each of which is connected between output signal line and power supply node. When MOS transistors are rendered non-conductive, the additional MOS transistor is rendered conductive. As a result, internal nodes are driven by an inverter and the additional MOS transistor to a power supply voltage, thereby turning off MOS transistors at the same timing. Consequently, through current in a semiconductor output circuit can be suppressed and an output signal has no ringing.

Abstract: A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.

Abstract: An output buffer circuit of the present invention comprises a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, a control input terminal receiving a control signal, an output terminal outputting an output signal, a first transistor coupled between the output node and a first potential source and a second transistor coupled between the output node and a second potential source. The output buffer of the present invention further includes a first gate circuit and a second gate circuit. The first gate circuit has a first input node coupled to receive the first input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the second input signal and an output node coupled to the control terminal of the first transistor. The first gate circuit outputs the signal received by the enable input node when the signals received by the first and second input nodes have predetermined level.

Abstract: A power MOSFET includes common source and drain terminals and a selection circuit. The sources and drains of a plurality of insulated gate field-effect transistors are respectively connected in parallel to the common source and drain terminals. The selection circuit selectively connects the gates of the insulated gate field-effect transistors to a gate terminal common to a source.

Abstract: A power transistor driving circuit for a single power source drives a predetermined load and prevents each of the drive circuit transistors from being damaged because they are not turned on simultaneously.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1,/.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients ("ringing"), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit's output NMOS transistor over the entire positive operation voltage range.

Abstract: Decoupling capacitors are activated by high current impulses that occur due to electrical over stress or electrostatic discharge, which occurs when the chip is powered off with no additional control signal or feedback elements. The high current or high voltage impulse is used to activate a rise time network, which turns on an electric switch, enabling the capacitor network. The basic circuit can be modified to address the situation where a failed decoupling capacitor needs to be switched out. In this modification, there is in addition to the three basic elements listed above, a feedback element connected between the decoupling capacitor and the switch. This feedback element operates to turn the electronic switch off when the decoupling capacitor is leaky. A further modification of the basic invention allows the decoupling capacitor to be used as a decoupling transistor during chip operation and as a capacitor during electrostatic discharge (ESD) testing or an ESD event.

Abstract: A decoupling capacitor and protection circuit is provided that will assist the power supply network in stabilizing the voltage near circuits that demand short rapid transitions in electrical current. The protection circuit also significantly reduces the amount of electrical current drawn by defective large area decoupling capacitors. An inverter stage controls a switching circuit connected in series with a decoupling capacitor. A feedback circuit is provided from the output of the capacitor to the switching circuit. If the capacitor goes bad, then a voltage is present on the feedback circuit and the switching circuit ensures that the output of the failed capacitor is presented with an open circuit so that the short circuit current flow through the capacitor is eliminated. In this manner, the integrity of the other circuits located near the failed capacitor will operate appropriately.