Abstract: The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer.

Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Abstract: A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.

Abstract: A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.

Abstract: An integrated single channel or multi-channel ultrasound transmitter that minimizes the number of input connections to a controller such as an FPGA, field programmable gate array, or a custom integrated circuit in an ultrasound system. The method is accomplished by integrating, in low voltage logic, a means to store and or program the patterns required for the transmitter output. The number of logic input connections can be further reduced by further integrating, in low voltage logic, programmable individual time delays and frequency divider for each transmitter output.

Abstract: A multiplexer for voltage measurement includes: a first switch disposed on a first channel extending between at least one high-voltage input terminal and an output terminal; a plurality of second switches respectively disposed on second channels each extending between each of input terminals other than the high-voltage input terminal and the output terminal; and a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch. Each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage.

Abstract: A gate driver of a switching element includes a first capacitor having a first end connected to a DC power source, a first switch having a first electrode connected to the first end of the first capacitor and a second electrode connected to a negative electrode of the DC power source, a second switch having a third electrode connected to the second electrode and the negative electrode of the DC power source and a fourth electrode connected to the first capacitor, a second capacitor connected in parallel with the third and fourth electrodes of the second switch and having a first end connected to the DC power source, and a negative voltage controller connecting the gate of the switching element to the second end of the first capacitor and a second end of the second capacitor when the switching element is turned off.

Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

Abstract: An apparatus selectively outputs one negative voltage from among a plurality of negative voltages. The apparatus includes a first switching unit configured to perform a switching operation and output a first voltage-on signal and a first voltage-off signal according to a selection signal and a first negative voltage signal, and a second switching unit configured to perform a switching operation and to output a second voltage-on signal and a second voltage-off signal according to the selection signal and a second negative voltage signal. The apparatus also includes a driving unit to select and output one negative voltage signal from among the first and second negative voltage signals according to the first negative voltage signal, the second negative voltage signal, the first voltage-on signal, the first voltage-off signal, the second voltage-on signal, and the second voltage-off signal.

Abstract: A switching circuit comprises a control and bias stage configured for receiving a first input voltage signal, a second input voltage signal and a selection signal and for generating therefrom a first bulk bias signal substantially equal to the first input voltage signal or to the second input voltage signal depending on the selection signal. The switching circuit further comprises a switching stage connected to the control and bias stage, including a transistor having a bulk terminal, and configured for receiving the bulk bias signal and generating an output signal having the first input voltage signal when the selection signal indicates the selection of the first input voltage signal or having the second input voltage signal when the selection signal indicates the selection of the second input voltage signal. The bulk bias signal is electrically coupled to the bulk terminal of the transistor.

Abstract: In one general aspect, an apparatus can include a complementary switch circuit including a first portion and a second portion, and a first driver circuit coupled to the first portion of the complementary switch circuit. The apparatus can include a positive charge pump device coupled to the first driver, and a second driver circuit coupled to the second portion of the complementary switch circuit. The apparatus can also include a negative charge pump device coupled to the second driver circuit.

Abstract: An active matrix panel includes a gate line connected to control electrodes of a plurality of transistors; and a drive circuit supplying the gate line with a conducting voltage and a non-conducting voltage. The drive circuit includes a shift register including a plurality of shift register unit circuits connected to each other, and a demultiplexer including a plurality of demultiplexer unit circuits into which output signals of the shift register unit circuits are input. The demultiplexer unit circuit includes a first transistor for supplying the gate line with the conducting voltage, and a second transistor for supplying the gate line with the non-conducting voltage. The first transistor is changed from a non-conducting state into a conducting state when the second transistor is in the conducting state.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon.

Abstract: A semiconductor device includes a multiplexer and an output buffer. The multiplexer includes: n switches (n is an integer of 2 or greater) each including an input node receiving a different data signal and an output node coupled to an input node of the output buffer; and a plurality of switch control circuits each corresponding to a respective one of the n switches. Each of the plurality of switch control circuits turns on a corresponding one of the n switches based on a corresponding one of the signals each having a first cycle and a phase different by 1/n of the cycle from adjacent phases. When each of the plurality of switch control circuits detects that an input-side data signal of the corresponding one of the n switches appears at a corresponding output-side node, each of the plurality of switch control circuits turns off the corresponding switch.

Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.

Abstract: Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.

Abstract: A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.

Abstract: There is provided a high frequency switch which is satisfactory in terms of both insertion loss characteristics and harmonic characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units includes a plurality of series-connected MOSFETs formed on a silicon substrate, the plurality of MOSFETs are any one of body contact-type FETs and floating body-type FETs, and each of the switching units includes both of the body contact-type FETs and the floating body-type FETs.

Abstract: A multiplexer is provided. The multiplexer includes an output coupled to a complementary driving unit and a plurality of switch circuits. Each switch circuit includes a channel unit and two switches. The two switches respectively conduct two input signals to a channel end of the channel unit during different switch conduction periods, and the channel unit conducts the channel end to an output end during a channel conduction period. The switch conduction period of the first switch in the first switch circuit equals the switch conduction period of the second switch circuit, the switch conduction period of the second switch in the second switch circuit equals the switch conduction period of the first switch circuit, and the first and second switches are coupled to the same input signal.

Abstract: Disclosed is a mixer able to simultaneously suppress self-mixing and low-order harmonic response in a charge sampling circuit. Specifically disclosed is a multiphase mixer provided with a transconductance amplifier (101) for converting a voltage signal into a current signal, an N number (where N is a natural number that is 2 or more) of first integrators (401, 402) which are connected in parallel to the subsequent stage of the transconductance amplifier (101), and a 2N number of mixers (102, 103, 104, 105) connected in parallel in pairs to the respective N number of first integrators (401, 402), wherein two mixers connected to the same first integrator of any of the N number of first integrators (401, 402) are controlled by driving signals comprised of pulse trains with the same frequency and phases differing by 180°.

Abstract: A switching circuit, a charge sense amplifier, and a photon counting device are provided. The switching circuit configured to close and open a connection between a first terminal and a second terminal of a predetermined circuit element, includes: a first transistor comprising a source connected to the first terminal, a drain connected to the second terminal, and a gate; a second transistor comprising a drain, a source, and a gate connected to the drain of the second transistor; a current source configured to supply a current flowing through the drain and the source of the second transistor, to generate a gate voltage of the gate of the second transistor; and a multiplexer configured to receive the gate voltage, a reference voltage, and a control signal, and selectively apply the gate voltage or the reference voltage to the gate of the first transistor based on the control signal.

Abstract: A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.

Abstract: Provided is a power supply switching circuit with a smaller circuit scale. When a detector (11) detects that a voltage (V1) as an input power supply voltage is higher than a detection voltage (VDET), a control circuit (41) operates with a voltage (V4) output from a diode OR circuit (42), supplies a voltage (V2) as an input power supply voltage to a gate of a PMOS transistor (17), supplies a voltage (V3) to a gate of a PMOS transistor (18), and supplies a ground voltage to a gate of a PMOS transistor (19). Then, the PMOS transistors (17 and 18) are turned OFF and the PMOS transistor (19) is turned ON. In this case, the voltage V1 of a first terminal (T1) is output from a third terminal (T3) as the voltage (V3), which is an output power supply voltage.

Abstract: A system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage signal.

Abstract: Circuits, methods, and apparatus that provide isolation between receive and transmit circuits in a wireless transceiver. One example provides switches that can be included on an integrated circuit with at least portions of a wireless transceiver. These switches vary the impedance of transmitter and receiver circuits between a termination impedance and a high impedance by inserting or removing components in parallel with matching networks. Signal losses are minimized since these switches are shunt connected to input and output paths on the wireless circuit and are not connected directly in either signal path.

Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular. This signal reproducing device (1) includes: N FETs (61 to 6N) each receiving a common input signal (VIN) at a gate terminal and having a bias voltage (VDD) applied to a drain terminal; and an adder circuit (4) connected to source terminals of the FETs (61 to 6N), for combining currents between the drain terminals and the source terminals of the FETs (61 to 6N) and outputting the resulting current, wherein the FETs (61 to 6N) and the bias voltage (VDD) are set so that a voltage at the gate terminal having the common input signal (VIN) applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the FETs (61 to 6N).

Abstract: A capacitively and conductively coupled multiplexer (C3mux) circuit is described. This C3mux circuit includes a set of nonlinear coupling capacitors, such as metal-oxide-semiconductor (MOS) transistors, that can multiplex multiple input signals while minimizing the parasitic capacitance penalty associated with the ‘off’ paths. In particular, the capacitance of a given MOS transistor depends on whether its channel is present or absent. Furthermore, this channel is formed based on whether the gate-to-source and drain voltages for the MOS transistor are greater than the MOS transistor's threshold voltage. Note that the capacitance of the MOS transistors in the C3mux circuit is low for the unselected inputs. Consequently, the parasitic loading and the delay increase slowly as a function of the number of inputs. Moreover, the conductive feedback can be used to maintain a DC level of the input signals.

Abstract: A power switch circuit includes a voltage selecting circuit, an auxiliary transistor and a control circuit. The control circuit includes an inverter, or a first inverter and a second inverter forming a latch. The power switch circuit is capable of tracing a higher supply voltage and outputting the voltage level of the higher supply voltage without a voltage drop, so the junction leakage can be eliminated and the drive capability of the power switch circuit is ensured.

Abstract: A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: An output circuit includes a first transistor coupled to an external terminal and including a gate terminal that receives a first drive signal. The first transistor drives a potential at the external terminal in accordance with the first drive signal. A first capacitor includes a first end coupled to the gate terminal of the first transistor and a second end coupled to the external terminal. The output circuit also includes a circuit portion coupled to the first transistor. The circuit portion maintains the first transistor in an inactivated state when the gate terminal of the first transistor is in a floating state.

Abstract: A biasing circuit of an integrated circuit includes a well of the integrated circuit and a plurality of transistors disposed in the well. The transistors couple the well to three signals providing corresponding voltages. The transistors bias the well to an extreme one of the corresponding voltages for the three signals.

Abstract: A reverse current preventing circuit of an N channel type switching MOS transistor connected between a voltage input terminal and an output terminal to control a conduction state between the voltage input terminal and the output terminal, the circuit comprises: a first MOS transistor connected between a substrate of the switching MOS transistor and a ground point; and a second MOS transistor connected between the substrate of the switching MOS transistor and a point having a piece of predetermined constant potential higher than that of the ground point, wherein the piece of predetermined constant potential higher than that of the ground point is applied to the substrate of the switching MOS transistor while the switching MOS transistor is made to be in its on-state, and ground potential is applied to the substrate of the switching MOS transistor while the switching MOS transistor is made to be in its off-state.

Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Abstract: A system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage signal.

Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.

Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.

Abstract: A switching circuit comprises a control and bias stage configured for receiving a first input voltage signal, a second input voltage signal and a selection signal and for generating therefrom a first bulk bias signal substantially equal to the first input voltage signal or to the second input voltage signal depending on the selection signal. The switching circuit further comprises a switching stage connected to the control and bias stage, including a transistor having a bulk terminal, and configured for receiving the bulk bias signal and generating an output signal having the first input voltage signal when the selection signal indicates the selection of the first input voltage signal or having the second input voltage signal when the selection signal indicates the selection of the second input voltage signal. The bulk bias signal is electrically coupled to the bulk terminal of the transistor.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a secondary input switch for selectively coupling the input node to the shared node, wherein the secondary input switch comprises one or more transistor switches. The parasitic drain and source diodes of one or more transistor switches in secondary input switch in a selected input circuit are coupled to a voltage that is distinct from an input signal of the selected input circuit.

Abstract: A multi-mode output transmitter includes a pair of driving circuits and a pair of common circuits. Each of the driving circuits includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and each of the common circuits includes a p-channel MOSFET. In one transmission mode, one of the pair of common circuits and one of the pair of driving circuits complementarily conduct; and in another transmission mode, the pair of common circuits simultaneously conduct to provide termination resistors.

Abstract: A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in parallel. In at least one embodiment, the selector circuits are responsive to the clock signals to transfer the data serially to the output line. Such apparatus and methods can also include a control unit to influence a portion of a signal that represents at least a portion of the data at the output line. Additional apparatus and methods are described.

Abstract: A power switch circuit includes a voltage selecting circuit, an auxiliary transistor and a control circuit. The control circuit includes an inverter, or a first inverter and a second inverter forming a latch. The power switch circuit is capable of tracing a higher supply voltage and outputting the voltage level of the higher supply voltage without a voltage drop, so the junction leakage can be eliminated and the drive capability of the power switch circuit is ensured.