Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed.

Abstract: In a synchronous rectifier package, a Schottky diode is situated in parallel, i.e., with like polarity, with the body diode of a synchronous rectifier. The anode of the Schottky diode is connected directly to the source pad of the synchronous rectifier, and the cathode is directly connected to the drain pad. As a result, the synchronous rectifier package has minimal parasitic inductances and resistances, resulting in a highly efficient synchronous rectifier over a wide range of operating frequencies, even at high frequencies. More precise synchronization of gating signals to each individual cell of the synchronous rectifier is also achieved, further increasing rectification efficiency. The synchronous rectifier package is implemented in either a metallized ceramic structure, or a high-density interconnect structure.

Abstract: A receiving comparator for a data-transmission system comprising at least one control unit and data-transmission lines, in particular for at least one Controller Area Network (CAN) controller and one CAN bus system having a CAN bus (CB) is proposed, which is distinguished by the feature that the individual circuit elements are monolithically integrated. By generating a switching threshold which is independent of the operating voltage and temperature with the aid of a current source (I.sub.S), one prevents the CAN bus potentials from being asymmetrically influenced. The arrangement guarantees a processing of digital signals with a high data rate, whereby the input common-mode range extends up to above the supply voltage and to below ground.

Abstract: A gate driver circuit includes a timing circuit, an anti-Miller surge protection circuit, and charging and discharging circuits for driving an output transistor, such as an IGBT. The anti-Miller surge protection circuit prevents the output transistor from being accidentally turned on. The gate driver circuit provides a high impedance input, so as to allow such a gate driver circuit to be driven by a relatively smaller isolation transformer. Further, the timing circuit in the gate driver circuit of the present invention allows such isolation transformer a relative lower frequency of operation. In one embodiment, the capacitance of the output transistor's gate terminal is used to determine the time constant of the timing circuit.

Abstract: An active clamp circuit for controlling over-voltage, surge conditions in electrical circuits. The active clamp includes a varistor which is switched into a circuit by a high power switch upon the detection of a surge condition. The use of a MOS Controlled Thyristor ("MCT") as a means for the switching the varistor permits the circuit to withstand a high di/dt and surge current while maintaining both on and off gated control of the switch.

Abstract: A monolithically integrated MOS output-stage component is proposed which is provided with an output-stage element (10) having a GATE connection, a SOURCE connection, and a DRAIN connection, and having an overload-protection device. An integrated GATE series resistor (11) is provided which connects an outer GATE connection (Ga) of the output-stage component with the GATE connection (Gi) of the output-stage element (10). The overload-protection device is integrated in the output-stage component and has a level matching stage (30) which, by a defined flow through the GATE series resistor (11), effects a displacement of the transmission characteristic of the output-stage element (10) by a defined voltage offset value. Furthermore, a limiting stage (34) is provided which limits the sum value of the DRAIN-SOURCE voltage and a voltage proportional to the DRAIN current to a determinable value.

Abstract: An analog switch includes first and second thin film field effect transistors having their gate connected in common to a control terminal. Current paths of the first and second thin film field effect transistors are connected in series between an input terminal and a capacitive load. A voltage adjusting capacitive element is connected to a common connection between the current paths of the first and second thin film field effect transistors.

Abstract: A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the f

Abstract: A gate drive circuit for a bidirectional blocking MOSFET, the bidirectional blocking MOSFET being characterized in the source region is not shorted to the body region. In one embodiment, the gate drive circuit includes diodes connected between the source/drain regions and a charge pump, the charge pump generating a gate drive voltage applied to a gate of the bidirectional blocking MOSFET. In a second embodiment, a charge pump generates a gate drive voltage which is applied to the gate of the bidirectional blocking MOSFET, and is also connected to the source/drain regions through zener diodes. In the second embodiment, the potential applied to the gate of the bidirectional blocking MOSFET is limited to a zener diode drop above the lower of the voltages of the source/drain regions. In a fourth embodiment, a charge pump generates a floating gate drive voltage which is applied to gate of the bidirectional blocking MOSFET through first and second depletion mode MOSFETS.

Abstract: A high voltage circuit for an electronic erasable programmable read only memory (EEPROM) integrated circuit (IC) is implemented using lower voltage semiconductor components. In the preferred embodiment, the circuit is capable of switching a twenty-four volt signal using p-channel metal-oxide semiconductor field effect transistors (MOSFETs) with a rated breakdown voltage not exceeding twelve volts. In the preferred embodiment, the circuit switches a driver signal in response to a first control signal.

Abstract: An latch circuit includes an input line receiving electrical signals from a bus, a latch for conducting electrical signals from the precharged bus to a receiving circuit, and a structure for enabling the latch only when data is driven onto the bus.

Abstract: A semiconductor device includes a main insulated gate type switching element having a gate electrode and controllable by a gate voltage applied to the gate electrode, a current detecting insulated gate type switching element connected in parallel to the main insulated gate type switching element, a detecting resistor for detecting a current flowing in the current detecting insulated gate type switching element, a gate controlling element capable of controlling the gate voltage by a drop voltage in the detecting resistor, and a gate control relieving element for relieving a varying speed of the gate voltage varied based on an operation of the gate controlling element.

Abstract: An improved Schmitt trigger, especially useful for large scale integrated circuit applications, includes a buffer (inverter) having a pull up device and two pull down devices all connected between a voltage supply and ground, and each receiving the input signal at its gate terminal. A node between the output terminals of the pull down devices is connected to the output terminal of the Schmitt trigger. A feedback line connects the output terminal of the Schmitt trigger to the gate of an N-channel depletion device connected between the pull-up and pull-down devices. Also provided are two devices to control the timing of the Schmitt trigger; these two control devices are connected between the output terminal of the Schmitt trigger and the output terminal of the inverter.Also provided in one embodiment is electrostatic discharge protection connected to the Schmitt trigger input and output terminals, and in another embodiment a control device for turning on and off the supply voltage to the inverter.

Abstract: Embodiments of the present invention bias a field effect transistor with only a single voltage source and generally do not have the disadvantages of traditional "floated source" bias techniques. Furthermore, some embodiments of the present invention are capable of automatically compensating for the normal manufacturing variations that occur in the physical characteristics of individual FETs.

Abstract: An isolated MOSFET gate drive includes circuitry to provide a negative gate bias during the off time of the MOSFET to enhance its immunity to inadvertent turn-on. The bias is generated by a self contained two terminal passive network which may be "floated" at any potential with respect to ground. This bias is automatically generated through the action of the network to the gate drive waveform, eliminating the need for an external bias supply to provide this voltage. The bias supply is located locally, thus eliminating the need for long interconnects which may interfere with circuit operation. The bias network in one implementation is a combination of a capacitor and non-linear semiconductor device with a fixed voltage breakdown characteristic. This two-component implementation maintains the capability of producing systems with high packaging densities.

Abstract: A smart power integrated circuit with dynamic isolation. A P-type isolation region surrounds the small signal devices (npn bipolar transistors and possibly other devices). This isolation region is held at ground in normal operation; but one or more pilot circuits continually monitor the collector voltages of the small-signal and power npn transistors, and instantly reconnect this isolation region, in real time, to the lowest collector voltage, whenever any of the collector voltages go below ground. Preferably a large capacitor provides a dedicated supply to the pilot circuit, so that the reconnection operation can proceed even when a power supply glitch occurs.

Abstract: A current divider for linearly dividing a first signal current (Ii10) into a second and a third signal current (Io11, Io12) includes a first terminal (I10) for the passage of the first signal current (Ii10), a second terminal (O11) for the passage of the second signal current (Io11) and for receiving a first potential, a third terminal (O12) for the passage of the third signal current (Io12) and for receiving a second potential, a first MOS transistor (M1) having a control electrode and a main current path, and a second MOS transistor (M2) having a control electrode and a main current path, the control electrodes of the first and the second MOS transistor (M1, M2) being coupled to a first reference terminal (R10) for receiving a first reference voltage (Rv10) to realize a conductive state of the first and the second MOS transistor (M1, M2) during a first active state of the current divider, the main current path of the first MOS transistor (M1 ) being coupled between the first terminal (I10) and the second te

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition.

Abstract: A circuit integrated on a semiconductor substrate in order to drive a load, (for example, a VFD) by means of a comparatively high voltage (for example, 35 V), includes a first and a second supply voltage terminal for application of the comparatively high voltage, an input, and a load output for connection of a load to be driven by the circuit. A switching transistor, a protection transistor and a sub-circuit are a part of the integrated circuit. The switching transistor and the protection transistor are connected in series with the gate of the switching transistor connected to the input. The source of the switching transistor is connected to a first supply voltage terminal, and the drain of the protection transistor supplies a signal for the sub-circuit during operation. The output of the sub-circuit is connected to the load output and the gate of the protection transistor receives a fixed voltage. The protection transistor is constructed so that it limits the voltage at the drain of the switching transistor.

Abstract: Disclosed is a switch circuit which has a depletion mode n-channel MOSFET which can be used in a circuit allowing only a positive voltage to be supplied thereto, comprising a first D-FET having a gate for receiving an input signal, a drain for outputting an output signal and a source; a first resistor connected between the drain of the first D-FET and a positive voltage source to bias the drain of the first D-FET; a second D-FET having a gate connected to an intermittence controlling voltage source, a drain and a source connected to the positive voltage source and the source of the first D-FET 201, respectively; a second resistor connected between the gate of the second D-FET and a ground to bias the gate of the second D-FET; a constant-current source connected between each of the sources of the first and second D-FET and the ground; a bypass capacitor connected in parallel with the constant-current source and between the drain of the constant-current source and the ground to bypass an RF signal to the ground

Abstract: A control circuit for an MOS semiconductor component having gate and source terminals has a load connected in series with the source terminal. A voltage source at fluctuating potential has first and second terminals. A first controllable semiconductor switch has a control input and is connected between the first terminal of the voltage source and the gate terminal of the MOS semiconductor component. The second terminal of the voltage source is connected to the source terminal of the MOS semiconductor component. A second switch is controllable by an input signal and has first and second load terminals. A line is connected to a fixed potential and to the first load terminal of the second switch. The second load terminal of the second switch is switched from a first to a second potential as a function of the input signal. The first and second potentials are between potentials of the first and second terminals of the voltage source.

Abstract: A circuit includes a high voltage energy source, a power transistor having a drain connected to the energy source and a source connected to a load, and a first capacitor connected between the power transistor gate and source. Also included is a first P-channel transistor connected in parallel with the first capacitor, and a second capacitor connected between the first P-channel transistor gate and drain. A transformer delivers positive voltage to the first capacitor to bias the power transistor ON, and delivers negative voltage to the second capacitor to bias the first P-channel transistor ON, which causes the energy stored in the first capacitor to discharge; thereby biasing the power transistor OFF.

Abstract: An electronic switch is disclosed for switching relatively high voltages, such as telecommunications voltages of the order of -48 volts, in response to logic levels of typically 0 to 5 volts. The switch comprises a MOSFET having a source-drain switching path and a gate; a control transistor controlled from a logic level control terminal; and a potential divider MOSFET source and the control transistor and having a tapping point coupled to the MOSFET gate. The potential divider includes a zener dime and/or a resistor connected between the MOSFET source and gate. The sinitch can be used with a current sensing resistor and a monostable circuit to fonn an automatically-reset circuit interrupter or electronic fuse.

Abstract: Reliability related problems such as destruction of the insulation film and shortened operating life of the MOSFET are prevented in a case where the voltage of an input signal is larger than a power source voltage for a semiconductor integrated circuit device. Where the voltage of an input signal which is received at an input signal terminal (3) is larger than a power source voltage V.sub.DD1, by causing a voltage drop between source-drain of an N channel MOS transistor (Tr4) which has a gate electrode fixed at the power source voltage V.sub.DD1, the voltage of the input signal is shifted. The shifted voltage is then applied to a gate electrode of an N channel MOS transistor (Tr2). That is, the voltage of the input signal is not directly applied to the gate electrode of the N channel MOS transistor (Tr2).

Abstract: A pull-down circuit for wide voltage operation including a ninth N-MOS transistor and a tenth N-MOS transistor each having a drain electrode connected to a data line and a source electrode grounded, an eleventh N-MOS transistor and a twelfth N-MOS transistor connected to each other in series between gates of the ninth and tenth N-MOS transistors and an output of a controller for controlling the pull-down circuit, each of the eleventh and twelfth N-MOS transistors having a gate electrode and a drain electrode connected with each other, and a thirteenth N-MOS transistor having a gate electrode adapted to receive a signal from the controller, a drain electrode connected to a source electrode of the twelfth N-MOS transistor, and a source electrode grounded. The pull-down circuit performs a pull-down operation at a voltage level of above 3 V and does not perform the pull-down operation at a voltage level of 3 V or below.

Abstract: A signal input/output circuit for a semiconductor integrated circuit being provided with a reset signal input/output terminal 1 which inputs external reset requesting signal REQ from the outside of the semiconductor integrated circuit 10 and outputs internal reset requesting signal TWD generated at the inside, and a reset signal input circuit 3 which is connected to the reset signal input/output terminal 1 through the protection resistance 4 and generates reset signal RST resetting the semiconductor integrated circuit 10 when the external reset requesting signal REQ is inputted to the reset signal input/output terminal 1.

Abstract: A circuit and method for driving an inductive load has a first transistor with a current flow path connected to provide drive current at an output node to the inductive load, and a control element for controlling the current in the first current flow path. The control element is adapted for connection to receive a control signal for turning the current in the first current flow path of the first transistor on and off. A second transistor has a current flow path connected between the output node and the control element of the first transistor, and has a control element for controlling the current in the current flow path. A capacitor is connected between the control element of the second transistor and a reference potential, the capacitor being much larger than an inherent capacitance at the control element of the first transistor divided by a current gain of the second transistor. Finally, a rectifier is connected between the output node of the first transistor and the capacitor.

Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates (high display resolutions), and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device.

Abstract: By disposing various current-sensing layers on a semiconductor element with a current-sensing function, wherein signals corresponding to the sensing currents derived from each current-sensing electrode are inputted independently into said over-current control circuit and short-circuit control circuit in a control circuit for said semiconductor element; or by constructing the current-sensing resistor in said control circuit with various resistors connected in series, wherein a single sensing current flows into this resistor to generate various detection voltages divided by the resistor, while detection voltages with different values are inputted independently into said main current turn-off command circuit and main current control circuit the value I.sub.oc of the over-current detection level for the semiconductor element with a current-sensing function and the value I.sub.sct at the short-circuit current detection level can be set independently of each other. Therefore, while increasing I.sub.oc, setting I.

Abstract: In a MOS integrated circuit is provided a first differential amplifying circuit for receiving complementary sets of input data at the gates of its two p-channel MOS transistors and for transmitting complementary sets of internal data. There is also provided a second differential amplifying circuit for receiving the complementary sets of internal data at the gates of its two n-channel MOS transistors and for transmitting complementary sets of output data. This realizes high-speed data transmission in which data transmission speed is independent of the generation of a clock signal. By preventing the flow of current from a power supply terminal to a ground terminal, a differential transmission circuit which consumes reduced current can be obtained.

Abstract: A circuit for switching the well in a CMOS circuit to one of two power supply rails. In, for example, an N-well CMOS process, when an output is driven by a PMOS pull-up transistor, the P+ (drain of the PMOS) to N-well junction may be forward biased if the rail drops to ground. This will cause the output to be pulled to ground. The switching circuit of the present invention avoids the grounding of the output by automatically switching the N-well to the higher power supply rail so that grounding the rail would not cause the output to fall. MOS switches connect the well to either of the power supplies. Therefore, there is no voltage drop from the power supply to the well as in the case of switching circuits using diodes. Also, this circuit connects the well to the highest power supply regardless of which power supply drops to ground. Therefore, it does not require one power supply to be always on for proper operation.