Abstract: A field-effect transistor includes a Ga2O3-based semiconductor layer, a source region and a drain region that are formed inside the Ga2O3-based semiconductor layer, a gate electrode that is formed, via a gate insulating film, on a channel region as the Ga2O3-based semiconductor layer between the source region and the drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region. An interface charge including a negative charge is formed between the gate electrode and the channel region, and a gate threshold voltage is not less than 4.5V.

Abstract: An electrostatic discharge protection circuit includes a pull-down switch, a dummy pattern arranged parallel to the pull-down switch in a first direction, clamp switches arranged parallel to each other in the first direction between the dummy pattern and the pull-down switch, and a resistor configured to transfer a power supply voltage supplied through a power terminal to a gate pattern of the pull-down switch by being arranged parallel to the pull-down switch. Drains of the clamp switches are coupled in common to the power terminal, sources of the clamp switches are coupled in common to a ground terminal, and a first end of the pull-down switch and a second end of the resistor are coupled to each other through a first conductive line extending in the first direction, the pull-down switch, the resistor and the first conductive line are formed in a same layer.

Abstract: A slew rate control device and a slew rate control method are provided. The slew rate control device includes a signal generating circuit, a comparator circuit, and a control circuit. The signal generating circuit generates a first voltage signal and a second voltage signal having a slew rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparator circuit outputs an enabling signal according to a relative positional relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock. The control circuit generates at least one control signal according to the enabling signal to control the signal generating circuit, such that the signal generating circuit changes the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal.

Abstract: A level shifter may include: a discharge circuit configured to receive an input signal on the basis of a first power supply voltage, and discharge an internal node on the basis of the input signal; a charge supply circuit configured to supply charge to an output node from which an output signal is outputted, on the basis of a second power supply voltage; and a voltage adjustment circuit including a first MOS transistor coupled between the internal node and the output node, and configured to adjust the voltage of the output node on the basis of a bias voltage applied to the first MOS transistor, and stop the operation of adjusting the voltage of the output node on the basis of the bias voltage, when the levels of the first and second power supply voltages are equal to each other.

Abstract: A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate of a first type, a first doped region embedded within the substrate and having a first portion and a second portion, and a first gate electrode disposed above the substrate. The semiconductor device further comprises a well region of a second type and embedded within the substrate. The well region is in contact with the second portion of the first doped region.

Abstract: Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.

Abstract: A switch circuit for use in a single-ended switched-capacitor circuit for front-end circuitry of a sensor device is disclosed. The switch circuit comprises a first transistor and a second transistor having a same channel-type as the first transistor. A first node is connected to a source of the first transistor and a drain of the second transistor and a second node is connected to a drain of the first transistor and a source of the second transistor. Also disclosed is a sampling circuit comprising the switch circuit and a sampling capacitor, wherein the switch circuit is configurable to electrically couple the sampling capacitor to an integrator circuit or to a voltage reference. An integrated circuit device and a light to frequency converter or light sensor comprising the switch circuit is also disclosed.

Abstract: In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

Abstract: Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

Abstract: An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.

Abstract: First and second switches are connected in series between first and second terminals. A third switch is provided between a first node between the first terminal and the first switch, and a first resistive-element. A fourth switch is provided between a second node between the first and second switches, and the reference power-source. A controller switches the first to fourth switches between conduction and non-conduction states. First, third, fifth, and seventh delay-circuits are provided between the first to fourth switches and the controller and delay first, second, third, fourth control signals for switching the first to fourth switches from a conduction state to a non-conduction state, respectively. Second, fourth, sixth, and eighth delay-circuits are provided between the first to fourth switches and the controller and delay the first, second, third, fourth control signals for switching the first to fourth switches to a non-conduction state to a conduction state, respectively.

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

Abstract: Disclosed is a low power consumption switching circuit with voltage isolation function for a PMOS transistor bulk, including a bulk voltage switching control unit, a bulk voltage switching unit, a first voltage input terminal, a second voltage input terminal, and a bulk voltage output terminal. The bulk voltage switching control unit includes a plurality of PMOS transistors and weak pull-down devices, and is configured to generate a control signal to control the bulk voltage switching unit to make the bulk voltage output terminal to be connected to a higher potential between the first voltage input terminal and the second voltage input terminal. The bulk voltage switching unit includes a plurality of PMOS transistors, and is configured to connect bulks of the PMOS transistors to the higher potential between the first voltage input terminal and the second voltage input terminal. Each of the PMOS transistors is a low-withstand-voltage device.

Abstract: In an integrated circuit, a bootstrapped switch includes a capacitor and first, second, and third transistors. The first transistor has a first current electrode coupled to a first voltage supply node and a gate electrode coupled to a first circuit node. The second transistor has a first current electrode coupled to a second voltage supply terminal, a second current electrode coupled to a top terminal of the capacitor, and a control electrode coupled to the first circuit node. The third transistor has a first current electrode coupled to the first voltage supply terminal, a control electrode coupled to the first circuit node, and a second current electrode coupled to a body terminal of the second transistor. The fourth transistor has a first current electrode coupled to the body terminal of the second transistor, and a second current electrode coupled to the top terminal of the capacitor.

Abstract: Unpowered switching module. A switching module can include a first input terminal, a second input terminal, and an output terminal. The output terminal can be configured to output a radio-frequency (RF) component of an input signal received on the first input terminal or the second input terminal in response to the input signal including a positive direct-current (DC) voltage.

Abstract: An electronic functional device such as an isolator arranged to offer configurable functionality for alteration of the function of the device. The device includes wireless reception means for receiving wireless configuration data for the selective configuration of the device, and can also include wireless transmission means for the wireless transmission of data identifying its configured state.

Abstract: A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

Abstract: A restraint control module is configured to communicate a sync pulse to a sensor. The control module includes a first sync pulse driver and a second sync pulse driver. The first sync pulse driver is connected to a first signal line and the second sync pulse driver connected to a second signal line. The first and second sync pulse drivers being configured to generate a differential sync pulse signal across the first signal line and second signal line using a first signal on the first signal line and a second signal on the second signal line.

Abstract: Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

Abstract: An oscillation device includes an oscillation circuit configured including an oscillation inverter, and adapted to oscillate a resonator, a frequency adjustment circuit adapted to perform frequency adjustment of the oscillation circuit, and a constant voltage circuit adapted to drive the oscillation circuit, in the oscillation circuit and the frequency adjustment circuit, a gate and a substrate of a field-effect transistor having a connection relationship with one of a gate and a drain of the oscillation inverter are driven with a constant voltage.

Abstract: A driving circuit for driving a power switch. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor corresponding to an input capacitor of the power switch, an equivalent inductor, and a second equivalent capacitor corresponding to a parasitic parameter of at least one driving switch. In the charging procedure or the discharging of the first equivalent capacitor, a change amount of charges in the first equivalent capacitor while a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a set voltage is larger than or equal to a change amount of charges in the second equivalent capacitor while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage.

Abstract: A subscriber station for a bus system and a method for reducing line-conducted emissions in a bus system are provided. The subscriber station includes a first delay element for delaying a signal of a bus of the bus system and a second delay element for delaying a signal of a bus of the bus system, the delay time of the first and second delay element being capable of being digitally set as a function of the bus state or independently for rising and falling signal edges at the bus of the bus system in order to carry out a signal symmetrization during the rising and falling signal edge at the bus.

Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

Abstract: A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.

Abstract: An electronic converter may include transformer with a primary winding and a secondary winding, wherein the primary winding is coupled to an input for receiving a power signal, and wherein the secondary winding is coupled to an output including a positive terminal and a negative terminal for providing a power signal. The converter moreover may include an electronic switch arranged between the input and the primary winding, wherein the electronic switch is configured to control the current flow through the primary winding. Specifically, the converter may include a snubber circuit arranged between the secondary winding and the output.

Abstract: A power supply, a controller, and a power element, wherein a DC compensation voltage is present at a first output of the power element to which a load having a variable current draw can be connected. A second output of the power element is thereby fed through a current measurement device, wherein a rechargeable battery is connected to the second output. A charging current or discharge current of the rechargeable battery measured by the current measuring device is set by controlling the DC compensating voltage. The charging current or discharge current of the rechargeable battery can thereby be determined even without a dedicated UPS assembly.

Abstract: A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus.

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract: A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and closed, when the first pn-junctions are not reverse biased.

Abstract: A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate. At least a first well region is formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate. The first well region is electrically connected to the first regions of the vertical transistor via a semiconductor switch. The semiconductor device comprises a detection circuit, which is integrated in the substrate and configured to detect whether the first pn-junctions are reverse biased. The switch is opened when the first pn-junctions are reverse biased and the switch is closed when the first pn-junctions are not reverse biased.

Abstract: A circuit for downscaling voltage comprising: a voltage regulator; a voltage reference register configured to provide a voltage reference value; a voltage comparator configured to output a logical one if a supply voltage of the voltage regulator is greater than the voltage reference value, wherein a first input of the voltage comparator is coupled to output of the voltage regulator and a second input of the voltage comparator is coupled to output of the voltage reference register; an AND gate, where a first input of the AND gate is coupled to output of the voltage comparator and a second input of the AND gate is coupled to a voltage reference ready signal; a switch configured to close based on output of logical one from the AND gate; and a pull-down resistor configured to couple to the output of the voltage regulator only if the switch is closed.

Abstract: An integrated circuit having a regulator circuit capable of tracking reference voltages is provided. The integrated circuit includes shunt regulator circuitry. The shunt regulator circuitry includes a shunt regulator circuit and a voltage tracking circuit. The shunt regulator circuit has an output on which a regulated voltage is provided. The shunt regulator circuit also provides electrical current to the output when the regulated voltage is outside of a voltage range bounded by first and second reference voltages. The voltage tracking circuit may be coupled to the shunt regulator circuit. The voltage tracking circuit may generate the first and second reference voltages. In one instance, the first voltage is greater than the regulated voltage and the second voltage is less than the regulated voltage.

Abstract: A bypass module including a plurality of P-Channel MOSFETs connected in parallel to form a P-Channel MOSFET array, a plurality of N-Channel MOSFETs connected in parallel to form a N-Channel MOSFET array, and a control module to control switching of the P-Channel MOSFET array and the N-Channel MOSFET array is disclosed. A battery or load management device used to switch higher current and low voltages is disclosed. A battery bypass and bypass method for charge, discharge, and charge limiting control for various types of batteries is disclosed.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.

Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.

Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.

Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.

Abstract: This document discusses, among other things, a switching device and method configured to receive a signal at a signal input, to provide the signal at an output in a first state without an applied voltage at a first control input, and to isolate the signal from the output in a second state with an applied voltage at the first control input. In an example, the switching device can include first, second, and third transistors, wherein the source of the first transistor is coupled to the drain of the second transistor and to the gate of the third transistor, wherein the signal input is coupled to the drain of the first transistor and to the drain of the third transistor, and wherein the output is coupled to the source of the third transistor.

Abstract: Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from GND to VDD can be reliably controlled.

Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.

Abstract: Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.

Abstract: Power switches operate with reduced power consumption. A circuit controls a power switch via its gate having a gate capacitor. The circuit comprises an on-control switch coupling the gate of the power switch with a charge supply to provide a gate charge to the gate capacitor of the power switch, thereby putting the power switch to the on-state; a transformer and an off-control switch coupling the gate of the power switch with ground via a primary winding of the transformer to discharge the gate capacitor of the power switch, thereby causing a discharge current through the primary winding and thereby putting the power switch to the off-state; wherein a secondary winding is coupled to the charge supply, such that a current, which is induced in the secondary winding, recharges the charge supply.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: An RF switch includes a transistor and a compensation capacitor circuit. The compensation capacitor circuit includes a first compensation capacitor and a second compensation capacitor of the same capacitance. The compensation capacitor circuit is used to improve voltage distribution between a control node and a first node of the transistor and between the control node and a second node of the transistor.

Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.

Abstract: An apparatus includes: a switch having a first transistor, the first transistor having a gate, wherein the switch is connected between a first pad and a second pad; and a first biasing circuit coupled to the gate of the first transistor, wherein the first biasing circuit is configured for outputting a first voltage, the first voltage being the lowest one of (1) a voltage of the first pad, (2) a voltage of the second pad, and (3) a ground voltage; wherein the gate of the first transistor is driven by the first voltage from the first biasing circuit in response to an enable signal being set for configuring the switch to be off.

Abstract: An electronic circuit includes a noise source and an analog circuit and a logic circuit that may be adversely affected by noise. At least a portion of the analog circuit and the logic circuit is formed on a buried impurity layer whose conductivity is different from that of a substrate, and at least a portion of the periphery of that portion is surrounded by an impurity layer that is different from the substrate. Thus, propagation of the noise from the noise source is prevented.