Complementary Metal-oxide Semiconductor (cmos) Patents (Class 327/437)
  • Patent number: 10127186
    Abstract: A subscriber station for a bus system and a method for reducing line-conducted emissions in a bus system are provided. The subscriber station includes a first delay element for delaying a signal of a bus of the bus system and a second delay element for delaying a signal of a bus of the bus system, the delay time of the first and second delay element being capable of being digitally set as a function of the bus state or independently for rising and falling signal edges at the bus of the bus system in order to carry out a signal symmetrization during the rising and falling signal edge at the bus.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: November 13, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Steffen Walker, Axel Pannwitz, Ingo Hehemann
  • Patent number: 10003192
    Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 19, 2018
    Assignee: NXP B.V.
    Inventors: Xueyang Geng, Ahmad Yazdi, Siamak Delshadpour, Abhijeet Chandrakant Kulkarni
  • Patent number: 9966911
    Abstract: A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 8, 2018
    Assignee: Dialog Semiconductor GmbH
    Inventor: Tim Morris
  • Patent number: 9960684
    Abstract: An electronic converter may include transformer with a primary winding and a secondary winding, wherein the primary winding is coupled to an input for receiving a power signal, and wherein the secondary winding is coupled to an output including a positive terminal and a negative terminal for providing a power signal. The converter moreover may include an electronic switch arranged between the input and the primary winding, wherein the electronic switch is configured to control the current flow through the primary winding. Specifically, the converter may include a snubber circuit arranged between the secondary winding and the output.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 1, 2018
    Assignee: OSRAM GmbH
    Inventor: Daniele Luccato
  • Patent number: 9774214
    Abstract: A power supply, a controller, and a power element, wherein a DC compensation voltage is present at a first output of the power element to which a load having a variable current draw can be connected. A second output of the power element is thereby fed through a current measurement device, wherein a rechargeable battery is connected to the second output. A charging current or discharge current of the rechargeable battery measured by the current measuring device is set by controlling the DC compensating voltage. The charging current or discharge current of the rechargeable battery can thereby be determined even without a dedicated UPS assembly.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: September 26, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wolfgang Böhm, Harald Schweigert
  • Patent number: 9520880
    Abstract: A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: December 13, 2016
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Bjoern Oliver Eversmann, Ralf Brederlow
  • Patent number: 9479168
    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 25, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
  • Patent number: 9406755
    Abstract: A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and closed, when the first pn-junctions are not reverse biased.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dorin Ioan Mohai, Adrian Finney, Adrian Apostol, Andrei V. Danchiv, Andrei Cobzaru
  • Patent number: 9406754
    Abstract: A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate. At least a first well region is formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate. The first well region is electrically connected to the first regions of the vertical transistor via a semiconductor switch. The semiconductor device comprises a detection circuit, which is integrated in the substrate and configured to detect whether the first pn-junctions are reverse biased. The switch is opened when the first pn-junctions are reverse biased and the switch is closed when the first pn-junctions are not reverse biased.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dorin Ioan Mohai, Ilie-Ionut Cristea, Adrian Finney, Bogdan-Eugen Matei, Andrei Cobzaru
  • Patent number: 9274538
    Abstract: A circuit for downscaling voltage comprising: a voltage regulator; a voltage reference register configured to provide a voltage reference value; a voltage comparator configured to output a logical one if a supply voltage of the voltage regulator is greater than the voltage reference value, wherein a first input of the voltage comparator is coupled to output of the voltage regulator and a second input of the voltage comparator is coupled to output of the voltage reference register; an AND gate, where a first input of the AND gate is coupled to output of the voltage comparator and a second input of the AND gate is coupled to a voltage reference ready signal; a switch configured to close based on output of logical one from the AND gate; and a pull-down resistor configured to couple to the output of the voltage regulator only if the switch is closed.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 1, 2016
    Assignee: ATMEL Corporation
    Inventors: Mickael Le Dily, Moise Carcaud
  • Patent number: 9128501
    Abstract: An integrated circuit having a regulator circuit capable of tracking reference voltages is provided. The integrated circuit includes shunt regulator circuitry. The shunt regulator circuitry includes a shunt regulator circuit and a voltage tracking circuit. The shunt regulator circuit has an output on which a regulated voltage is provided. The shunt regulator circuit also provides electrical current to the output when the regulated voltage is outside of a voltage range bounded by first and second reference voltages. The voltage tracking circuit may be coupled to the shunt regulator circuit. The voltage tracking circuit may generate the first and second reference voltages. In one instance, the first voltage is greater than the regulated voltage and the second voltage is less than the regulated voltage.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: September 8, 2015
    Assignee: Altera Corporation
    Inventors: Kok Siang Tan, Chuan Khye Chai, Wilfred Wee Kee King
  • Publication number: 20150137873
    Abstract: A bypass module including a plurality of P-Channel MOSFETs connected in parallel to form a P-Channel MOSFET array, a plurality of N-Channel MOSFETs connected in parallel to form a N-Channel MOSFET array, and a control module to control switching of the P-Channel MOSFET array and the N-Channel MOSFET array is disclosed. A battery or load management device used to switch higher current and low voltages is disclosed. A battery bypass and bypass method for charge, discharge, and charge limiting control for various types of batteries is disclosed.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Applicant: EAGLEPICHER TECHNOLOGIES, LLC
    Inventors: David Paul BACKUS, Jr., David BROWN
  • Patent number: 9020018
    Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 28, 2015
    Assignee: Apple Inc.
    Inventors: Gary Lang Do, David A. Donovan, Gurusubrahmaniyan Radhakrishnan
  • Publication number: 20150070077
    Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Ian Juso DEDIC, Gavin Lambertus ALLEN
  • Patent number: 8975950
    Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.
    Type: Grant
    Filed: July 6, 2013
    Date of Patent: March 10, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anuj Madan, Fikret Altunkilic, Guillaume Alexandre Blin
  • Patent number: 8963618
    Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 24, 2015
    Assignee: Ferfics Limited
    Inventors: John Keane, Ian O'Regan
  • Publication number: 20150043265
    Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Gregory Ameriada Uvieghara, Sei Seung Yoon
  • Patent number: 8928392
    Abstract: This document discusses, among other things, a switching device and method configured to receive a signal at a signal input, to provide the signal at an output in a first state without an applied voltage at a first control input, and to isolate the signal from the output in a second state with an applied voltage at the first control input. In an example, the switching device can include first, second, and third transistors, wherein the source of the first transistor is coupled to the drain of the second transistor and to the gate of the third transistor, wherein the signal input is coupled to the drain of the first transistor and to the drain of the third transistor, and wherein the output is coupled to the source of the third transistor.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: January 6, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tony Cheng Han Lee, Shawn Barden
  • Publication number: 20140361825
    Abstract: Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from GND to VDD can be reliably controlled.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventor: Yutaka SATO
  • Patent number: 8896363
    Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: November 25, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Da Chen, Zhengwei Zhang, Wei Mao
  • Publication number: 20140333367
    Abstract: Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Ricardo P. Coimbra, Edevaldo Pereira Silva, JR.
  • Patent number: 8872576
    Abstract: Power switches operate with reduced power consumption. A circuit controls a power switch via its gate having a gate capacitor. The circuit comprises an on-control switch coupling the gate of the power switch with a charge supply to provide a gate charge to the gate capacitor of the power switch, thereby putting the power switch to the on-state; a transformer and an off-control switch coupling the gate of the power switch with ground via a primary winding of the transformer to discharge the gate capacitor of the power switch, thereby causing a discharge current through the primary winding and thereby putting the power switch to the off-state; wherein a secondary winding is coupled to the charge supply, such that a current, which is induced in the secondary winding, recharges the charge supply.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 28, 2014
    Assignee: Dialog Semiconductor GmbH
    Inventor: Horst Knoedgen
  • Patent number: 8860495
    Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 14, 2014
    Assignee: Transphorm Inc.
    Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
  • Patent number: 8847668
    Abstract: An RF switch includes a transistor and a compensation capacitor circuit. The compensation capacitor circuit includes a first compensation capacitor and a second compensation capacitor of the same capacitance. The compensation capacitor circuit is used to improve voltage distribution between a control node and a first node of the transistor and between the control node and a second node of the transistor.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 30, 2014
    Assignee: RichWave Technology Corp.
    Inventor: Chih-Sheng Chen
  • Publication number: 20140268463
    Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel M. DREPS
  • Patent number: 8836409
    Abstract: An apparatus includes: a switch having a first transistor, the first transistor having a gate, wherein the switch is connected between a first pad and a second pad; and a first biasing circuit coupled to the gate of the first transistor, wherein the first biasing circuit is configured for outputting a first voltage, the first voltage being the lowest one of (1) a voltage of the first pad, (2) a voltage of the second pad, and (3) a ground voltage; wherein the gate of the first transistor is driven by the first voltage from the first biasing circuit in response to an enable signal being set for configuring the switch to be off.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Edward Cullen, April M. Graham, Ionut C. Cical
  • Publication number: 20140247001
    Abstract: An electronic circuit includes a noise source and an analog circuit and a logic circuit that may be adversely affected by noise. At least a portion of the analog circuit and the logic circuit is formed on a buried impurity layer whose conductivity is different from that of a substrate, and at least a portion of the periphery of that portion is surrounded by an impurity layer that is different from the substrate. Thus, propagation of the noise from the noise source is prevented.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 4, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Isamu MORIYA, Atsushi YAMADA
  • Publication number: 20140232710
    Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.
    Type: Application
    Filed: March 22, 2012
    Publication date: August 21, 2014
    Inventors: Chia How Low, Luke A. Johnson, Mun Fook Leong
  • Patent number: 8786361
    Abstract: An analog interface processing circuit includes a first and second signal processing interface, a processing system connected to the first and second signal processing interfaces, a biasing voltage source switchably coupled to said first signal processing interface via a first switch assembly and switchably coupled to said second signal processing interface via a second switch assembly, and a first control output of said processing system controllably coupled to said first switch assembly and a second control output of said processing system controllably couple to said second switch assembly.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 22, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Gary L. Hess
  • Publication number: 20140197879
    Abstract: Techniques for reducing crowbar current are disclosed. In one embodiment, a circuit for reducing crowbar current comprises an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail. The circuit also comprises a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state.
    Type: Application
    Filed: January 16, 2013
    Publication date: July 17, 2014
    Applicant: QUALCOMM Incorporated
    Inventor: Yu Huang
  • Patent number: 8766700
    Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: July 1, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vineet Mishra, Rajavelu Thinakaran
  • Publication number: 20140176227
    Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.
    Type: Application
    Filed: July 9, 2013
    Publication date: June 26, 2014
    Inventors: Tse-Hung Wu, Chao-Kai Tu, Chia-Wei Su
  • Publication number: 20140159799
    Abstract: A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: AU Optronics Corp.
    Inventors: Chung-Chun CHEN, Hsiao-Wen WANG
  • Patent number: 8749297
    Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Synopsys, Inc.
    Inventors: Agustinus Sutandi, Yanyi L. Wong
  • Patent number: 8742813
    Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: June 3, 2014
    Assignees: Samsung Electro-Mechanics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Yu Sin Kim, Sang Hee Kim, Dong Hyun Baek, Sun Woo Yun, Sung Hwan Park
  • Publication number: 20140145867
    Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
    Type: Application
    Filed: March 8, 2013
    Publication date: May 29, 2014
    Applicant: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Paul A. Baginski
  • Patent number: 8729954
    Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 20, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colin C. McAndrew, Michael J. Zunino
  • Patent number: 8729952
    Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 20, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Xiaomin Yang, James P. Furino, Jr.
  • Publication number: 20140117914
    Abstract: An analog-switch circuit (1) having: a resistor (R1); a resistor (R2); a CMOS analog switch (S1) in which a first end is connected to an input end (Vin) via the resistor (R1), and a second end is connected to an output end (Vout); and a CMOS analog switch (S2), in which a first end is connected to the first end of the analog switch (S1), and a second end is connected to a ground end via the resistor (R2). The CMOS analog switch (S2) is turned on or off in antiphase to the analog switch (S1).
    Type: Application
    Filed: June 8, 2012
    Publication date: May 1, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Masanori Tsuchihashi
  • Publication number: 20140113680
    Abstract: A switch control circuit has level shifters connected to a switch circuit to convert voltage levels of control signals, a negative potential generating circuit connected to the level shifter, to generate a negative potential, a negative potential output line supplying the negative potential to the level shifter, and a negative potential output line control circuit configured to control the potential of the negative potential output line. The negative potential output line control circuit has a power-supply setting circuit, an inverter inverting the output signal from the power-supply setting circuit, a first capacitor connected between an output terminal of the inverter and the negative potential output line, and a negative potential initialization circuit.
    Type: Application
    Filed: December 26, 2013
    Publication date: April 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiki SESHITA
  • Patent number: 8698358
    Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Marvin L. Peak, Jr., Bradley M. Harrington, Matthew R. Harrington
  • Patent number: 8698546
    Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vineet Mishra, Rajavelu Thinakaran
  • Patent number: 8686758
    Abstract: I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 1, 2014
    Assignee: Altera Corporation
    Inventors: Ket Chiew Sia, Choong Kit Wong, Boon Jin Ang
  • Publication number: 20140084988
    Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vineet Mishra, Rajavelu Thinakaran
  • Patent number: 8675811
    Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 18, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Etsuo Yamamoto, Yasushi Sasaki, Yuhichiroh Murakami, Shige Furuta
  • Patent number: 8659345
    Abstract: A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: February 25, 2014
    Assignee: Southeast University
    Inventors: Shen Xu, Weifeng Sun, Miao Yang, Sichao Liu, Youshan Jin, Shengli Lu, Longxing Shi
  • Patent number: 8653880
    Abstract: A switch circuit includes: first, second, and third input-output terminals; a first switching element connected between the first and second input-output terminals; a second switching element connected between the third input-output terminal and a grounding point; a third switching element connected between the first and third input-output terminals; a fourth switching element connected between the second input-output terminal and the grounding point; a first control voltage applying terminal connected to control terminals of the first and second switching elements; a second control voltage applying terminal connected to control terminals of the third and fourth switching elements; first and second resistors connected between the control terminals of the first and second switching elements and the first control voltage applying terminal, respectively; and first and second diodes connected in parallel with the first and second resistors, respectively, and having cathodes connected to the first control voltage
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 18, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshihiro Tsukahara
  • Publication number: 20140043094
    Abstract: A semiconductor device includes a first transistor having a p-channel type, a second transistor having an n-channel type, and a third transistor with low off-state current between a high potential power supply line and a low potential power supply line, and a source terminal and a drain terminal of the third transistor are connected so that the third transistor is connected in series with the first transistor and the second transistor between the high potential power supply line and the low potential power supply line, and the third transistor is turned off when both the first transistor and the second transistor are in conducting states.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 13, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Publication number: 20140043093
    Abstract: Direct-path current is reduced in a semiconductor device including CMOS circuits. One embodiment of the present invention is a method for driving a semiconductor device that includes a first CMOS circuit between power supply lines, a first transistor between the power supply lines, a second CMOS circuit between the power supply lines, and a second transistor between an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit. The first transistor and the second transistor each have lower off-state current than a transistor included in the first CMOS circuit. In a period during which the voltage of a first signal input to the first CMOS circuit is changed, a second signal is input to the first transistor and the second transistor to turn off the first transistor and the second transistor.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 13, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8648642
    Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: February 11, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Hugo Gicquel, Beatrice Lafiandra, Christophe Forel