Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.

Abstract: In a composite IC in which integrated are a power transistor, a bipolar analog circuit and a MOS logic circuit, a load-driving semiconductor device is provided which is capable of certainly placing the power transistor into an off-condition at power-on for stopping the driving of a load. In the semiconductor device, a high-side switch MOS transistor, a charge pump, a bipolar analog circuit, a charge pump driving CMOS logic circuit, a level conversion CMOS logic circuit and a forcibly stopping bipolar transistor 90 are made in the form of an IC, and the forcibly stopping bipolar transistor receives, through its base terminal, a signal which inverts when a drive voltage exceeds a predetermined value to turn to an on-condition. This operation places the bipolar analog circuit into a driving-stopped condition.

Abstract: A gate sink circuit includes a comparator for monitoring a gate voltage of a switching device in comparison with a predetermined threshold value; a sink switching device connected between the gate of the switching device and a ground line; an inverter for inverting an output of the comparator; another inverter for inverting an input signal for the switching device; an AND circuit for operating the logic product of each output from the inverters; and an RS flip-flop FF provided with the output of the AND circuit as a set signal and the input signal as a reset signal, thereby securely keeping an off-state of the switching device and greatly reducing flow-through current in turn-on.

Abstract: A circuit for controlling inrush current to a load is provided. The circuit includes a variable impedance device having a control input. The variable impedance device is coupled between a power supply interface and a load interface. The circuit also includes a control circuit coupled to the control input of the variable impedance device and also coupled to the load interface. The control circuit is adapted to provide a signal at the control input of the variable impedance device which results in a linear increase in applied voltage to the load when the circuit is coupled to an input power source. A resistor is coupled between the first and second terminals of the power supply interface to provide a current discharge path for the control circuit when the circuit is disconnected from the power supply.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: The present invention is a circuit comprising two series-coupled field effect transistor (FET) devices with a resistor network coupled in parallel forming a composite device (that can be substituted directly for a single FET device). In applications such as active loads or current sources, the composite device exhibits a greater breakdown voltage and superior high-frequency characteristics. The resistor network provides optimum direct current (DC) bias for depletion mode devices and superior high-frequency loading. Bandwidth and stability are both increased. Furthermore, this circuit is compatible with depletion mode FET processes having a single fixed threshold voltage.

Abstract: A clamping MOS transistor-based overvoltage protection circuit is provided for a bidirectional transmission gate FET coupled between input and output ports. When the voltage applied to the input port exceeds the supply voltage by a MOS gate threshold, the clamping MOS transistor is turned on, pulling the voltage applied to the gate of the transmission gate FET very close to the applied overvoltage level by a voltage differential less than a diode drop. This reduction in Vgs of the transmission gate FET reduces its source-to-drain current, as the device operates deeper in a sub-threshold region, increasing the overvoltage rating for the same leakage current specification. In a second embodiment, a clamping MOS device is coupled on either side of the source-drain path of the transmission gate's FET device.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: A switching circuit incorporating a high voltage transistor protection technique for use in an integrated circuit device having dual voltage supplies which extends the maximum pumped voltage (“VCCP”) for reliable MOS transistor operation to VCCP=VTN+(2*VCC), where VTN is the threshold voltage of the transistor and VCC is the supply voltage level. This is effectuated by adding an additional relatively thick gate oxide transistor in series with the relatively thin gate oxide MOS N-channel transistors in a conventional high voltage switching circuit to increase the reliable maximum voltage for the high voltage power supply.

Abstract: A one transistor, non-volatile programmable switch includes uni-directional and in some embodiments, bi-directional, states. The programmable switch is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch. The non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell), in which the data storage structure comprises a nitride layer, or other charge trapping layer, between oxides or other insulators.

Abstract: A semiconductor component performing interface functions between the controller and the power components of a power inverter, is designed for the control of semiconductor components, in particular for the control of IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power switches in different circuit topologies for intermediate and high power capacity. The component carries a monolithically integrated circuit performing the functions of signal processing (12), level transformation (13, 14), gate driver amplification, generation and monitoring of operating voltages, short-circuit monitoring by means of collector-emitter voltage detection, as well as the processing, storing and transmission of error signals for a power semiconductor switch.

Abstract: A method of control of the current and voltage switching trajectories of insulated gate power semiconductor switches, more specifically MOSFETs and insulated gate bipolar transistor devices (IGBTs), is disclosed. MOSFETs and IGBTs are used in switch mode power supplies because of their easy driving ability and their ability to handle high currents and voltages at high-switching frequencies. However, the switching trajectories for both types of devices are responsible for both common-mode electromagnetic emissions generated by the drain current waveform and power losses in the commutation cell. These two characteristics represent opposing design objectives for power converters. The current invention uses a hybrid voltage/current gate signal source with feedback of the gate charge (or discharge) current to dynamically and independently control the drain current and drain voltage of an insulated semiconductor device.

Abstract: A fast switching device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

Abstract: A circuit configuration produces an at least approximately ideal diode characteristic on the basis of a diode. A power MOSFET has a control path connected in parallel with the diode, a load path forming connection terminals of the ideal diode, and a gate connection to which a predetermined voltage potential is applied, for turning on the power MOSFET in the forward-bias direction of the diode and turning off the power MOSFET in the reverse-bias direction.

Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.

Abstract: In a semiconductor switch, a voltage detection circuit is provided so as to be in parallel with a first switching element for turning on/off a power supply to a load, in which a voltage detection portion for detecting a drain voltage of the first switching element by dividing a voltage upon a resistance ratio or the like and a second switching element are connected in series to each other. The second switching element is turned on/off in accordance with ON/OFF of the first switching element. Accordingly, detection of a drain voltage is performed normally when the first switching element is in an ON state. When the first switching element is in an OFF state, a leakage current can be reduced by the second switching element.

Abstract: Disclosed is a circuit for driving a gate of an IGBT (insulated gate bipolar transistor) inverter. The present invention includes a first IGBT of which collector is connected to a DC voltage, a second IGBT of which collector is connected to an emitter of the first IGBT, wherein an output signal is outputted from a connection point between the collector of the second IGBT and the emitter of the first IGBT, and of which emitter is connected to a ground, first and second driving circuits supplying gates and the emitters of the first and second IGBTs with DC driving voltages, respectively, through first and second gate resistors, and first and second noise interruption circuits connected between the gates-emitters of the first and second IGBTs and the first and second driving circuits, respectively, so as to interrupt noises.

Abstract: A power module is provided with an insulating substrate with a heat sink being bonded to one surface thereof and a circuit pattern being formed on the other surface. The circuit pattern is formed by an electrode layer. A switching semiconductor element and a free wheeling diode that is connected to a switching semiconductor element in anti-parallel therewith are placed on the circuit pattern. A controlling IC for controlling the switching semiconductor element is placed on the free wheeling diode. Thus, it is possible to make the entire power module compact, and it becomes possible to provide an inexpensive power module which can prevent the controlling IC from malfunctioning due to heat generated by the switching semiconductor element.

Abstract: In a parallel circuit (10) comprising a plurality of high-power IGBTs (T1, . . . ,T3) which are each driven by a dedicated gate drive circuit (GD1,. . . ,GD3), each of the gate drive circuits (GD1,. . . ,GD3) having, at its output, a p-channel MOSFET (M1, M3, M5) and an n-channel MOSFET (M2, M4, M6) in a push-pull arrangement and the outputs of the gate drive circuits (GD1, . . . ,GD3) being connected to the gates of the IGBTs (T1,. . . ,T3) in each case via a gate resistor (R1,. . . ,R3), a parallel circuit comprising more than two gate drive circuits is made possible by virtue of the fact that the outputs of the gate drive circuits (GD1,. . . ,GD3) are interconnected via a connecting line (11), and that the MOSFETs (M1,. . . ,M6) of the gate drive circuits (GD1,. . . ,GD3) are in each case connected to a positive or negative supply terminal (P1, . . . ,P3 or N1, . . . ,N3) via a constant-current source (CS1,. . . ,CS6).

Abstract: A multichip configuration in which a plurality of semiconductor chips in a module are connected together in such a way that the voltage drop across internal gate resistors is minimized, in order in the event of a short circuit to prevent the short circuit current rising with the gate voltage.

Abstract: An input protection circuit capable of precisely bypassing a surge current to a power source terminal and protecting the gate of a protective transistor from an electrostatic surge. The input protection circuit has an input terminal which receives an input signal, a first power source terminal which receives a first power source electric potential, and a first protective power source potential line connected to the first power source terminal for supplying the first power source electric potential to an input protection circuit. The input protection circuit has a first input protection transistor of a first conductive type having a drain connected to the input terminal, a gate and a source connected to the first protective power source potential line.

Abstract: An analog switch includes a MOSFET that serves as a switching transistor through which the signal received at an input terminal of the analog switch passes to an output terminal of the analog switch. A resistor is coupled to the gate of the switching transistor to prevent the discharge of gate capacitance when a control signal is activating the switching transistor in an ON state. A second MOSFET has its source and drain terminals coupled across the gate and substrate of the switching transistor. The second MOSFET is activated to an ON state to provide low-impedance driving of the switching transistor when the control signal is driving the switching transistor to an OFF state. The switching MOSFET and the second MOSFET may be NMOS devices in some embodiments, while in other embodiments, PMOS devices.

Abstract: A circuit and method for controlling a switch include a level shifter that controls a dynamic, bi-directional high voltage analog switch. The level shifter generally includes transistors, input terminals, a voltage source, a high negative voltage source, and a diode. The configuration of the level shifter, inter alia, allows the switch to be kept ON without a current/signal, prevents dissipation of transistors of the level shifter, and provides constant gate-to-source voltage on the switch transistors for improved linearity.

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: The buffer/driver for low dropout regulators (LDO) uses a feedback amplifier with low output impedance to drive the gate of the pass device MP6 of the regulator. This effectively pushes the gate pole out to a higher frequency. The feedback amplifier is designed for very high slew rate and high bandwidth while running at very low quiescent current. The circuit enhances the LDO performance, stability, and slew rate.

Abstract: A circuit arrangement for generating an electronically controlled electrical resistance by apparatus of at least one MOS transistor. A source-drain junction of the MOS transistor is used for the generation of the electrical resistance between a first and a second terminal, in order to optimize the linearity of the electrical resistance, there have been provided means for generating a bulk signal, which apparatus generate from the voltage on that terminal of the circuit arrangement which is coupled to the source electrode of an associated MOS transistor a signal for driving a bulk electrode of the associated MOS transistor, which signal is generated from the voltage on the terminal and an additionally superposed direct voltage of such a polarity that, depending on the doping type of the MOS transistor the formation of a diode between the source and bulk regions of this MOS transistor is avoided.

Abstract: An integrated circuit clock buffer is described which includes a pulser circuit having a delayed feedback to provide a pulsed signal in response to a transition in the external clock signal. The pulser circuit includes a delay element having an output node coupled to the input node of an inverter. The delay element and inverter are coupled between a first and second transistor. The buffer circuit generates non-skewed internal clock signals.

Abstract: An input-separated switching device driving circuit in an equivalent power source for supplying a source current, the input-separated switching device driving circuit including: an input-separated switching device which includes a main switching device for switching a load current portion of the source current based on a first driving signal applied to a first driving signal input, and a sense switching device for switching another portion of the source current based on a second driving signal applied to a second driving signal input in order to check the intensity of the load current.

Abstract: A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor.

Abstract: A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.

Abstract: An inductive load driving circuit, formed in an integrated circuit device, includes first, second, third, and fourth switching transistors, and a guardring. The first switching transistor is connected between a first power supply potential point and a first output terminal. The second switching transistor is connected between the first power supply potential point and a second output terminal. The third switching transistor is connected between the first output terminal and a second power supply potential point. The fourth switching transistor is connected between the second output terminal and the second power supply potential point. One of the third switching transistor and the fourth switching transistor is turned on or off depending on a power supply direction in which power is supplied to an inductive load connected between the first output terminal and the second output terminal.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: A drain current of an FET (4) is controlled to control an output of a buzzer (11), and a gate voltage of the FET (4) is controlled by an operational amplifier (3) for changing a source output of the FET (4) into an inverted input. By such a negative feedback circuit structure, a path for controlling a buzzer output is set to be one system and stability of the buzzer output can be enhanced. A variable power supply (2) for changing an output in accordance with control data of a logic section (1) is set to be a non-inverted input of the operational amplifier (3). Consequently, it is possible to obtain a circuit structure which does not depend on the number of bits of the control data.

Abstract: A switch circuit has an input terminal and an output terminal and when turned on, provides a voltage at its input terminal to its output terminal. A transistor is connected between the input and output terminals. A gate drive circuit is connected to the gate of the transistor and provides a gate drive signal to the gate. The gate drive circuit, in response to a first control signal, causes the gate drive signal to have one of a first voltage derived from an input voltage at the input terminal and a low potential voltage. A back gate drive circuit is connected to a back gate of the transistor and provides a back gate drive signal to the back gate. The back gate drive signal controls a voltage applied to the back gate of the transistor depending on whether the transistor is turned on or off. The switch circuit may be used to selectively supply battery power to a portable electronic device.

Abstract: A method and apparatus are provided for adjusting an offset in an electronic circuit by shifting at least one threshold voltage of a MOS transistor in an electronic circuit. By biasing a transistor into hard saturation, with sufficient supply voltage, charge carriers will be injected into the oxide layer of the MOS transistor over a predetermined time interval. Injection of charge carriers into the oxide layer of a MOS transistor causes the absolute value of the MOS transistor threshold voltage to increase. The injection of charge carriers is used to either intentionally increase or decrease the offset voltage in an electronic circuit due to mismatched components, process variations or to improve overall system accuracy or performance. In an operational amplifier or comparator, systematic offset voltage is measured at the output of the amplifier, and the threshold voltages of the differential input stage transistors are adjusted accordingly.

Abstract: An input circuit is established between an input pad and a first stage input gate; a determining portion and switching portion are established in this input circuit. The determining portion determines the presence of bonding to an input pad according to the potential of the input pad. The switching portion outputs a low level signal to the first stage input gate when the determining portion determines that “there is no bonding” and connects the first stage input gate with the input pad when the determining portion determines that “there is bonding”.

Abstract: A semiconductor power converting apparatus includes a semiconductor element for controlling a current flowing between a collector and an emitter in response to a gate condition, a driving device connected to the gate, for driving the gate in response to a drive signal entered thereinto, a voltage applying device for applying both a forward bias and a reverse bias to the gate so as to set the emitter of the semiconductor element to a neutral potential, and a voltage dividing device for dividing a voltage appearing between the collector and the emitter of the semiconductor element, in which the drive signal is under OFF state, a voltage produced based upon the divided voltage by the voltage dividing device is applied to the gate, and the gate voltage is controlled in response to the voltage appearing between the collector and the emitter of the semiconductor element, thereby reducing the snubbed loss.

Abstract: A switching circuitry and a switching method which reduces the influence of parasitic capacitance and provides improved signal performance at high frequencies. The circuitry may comprise a transistor having a source connected to an input node having an output resistance R2, and a drain is connected to the output node having an input resistance R3. The gate of the transistor is connected to a control node with output resistance R12 generating a control signal which opens or closes the transistor. By arranging that R1>>R2 (and assuming that R1≧R3), high frequency circuitry characteristics are dramatically improved, and the circuit provides high frequency voltage gain approaching unity and phase shift between the output and input voltages approaching zero to reduce signal degradation. Alternative arrangements may employ bipolar, FET, or MOS transistors or transistor pairs. The switching circuitry has numerous applications, e.g.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: A semiconductor switching device has a first semiconductor element, a second semiconductor element, and a comparator. The first semiconductor element has a first main electrode, a second main electrode, and a control electrode. The second semiconductor element has a first main electrode connected to the first main electrode of the first semiconductor element, a control electrode connected to the control electrode of the fist semiconductor element, and a second main electrode connected to a circuit that consists of a resistor and a constant current source that are connected in parallel with each other. The comparator compares potentials of the second main electrodes of the first and second semiconductor elements with each other. If the potential of the second main electrode of the first semiconductor element exceeds the potential of the second main electrode of the second semiconductor element, it is determined that there is a break in the load.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in a output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once. By applying the voltage support in phases, a smoother response to the operation of switching the drive transistor off and on may be realized.

Abstract: A high-side, low-side driver that controls voltage from a voltage source to an inductive or resistive load includes a power transistor with a gate, a source and a drain. The driver is configured in a high-side configuration when the load is connected between the source and ground and the drain is connected to the voltage source and in a low-side configuration when the load is connected between the drain and the voltage source and the source is connected to ground. A gate drive circuit turns the power transistor on and off. The positive clamp circuit is connected to the drain and the voltage source. The positive clamp circuit provides a recirculation path for inductive energy that is stored in the inductive load when a loss of reverse battery condition occurs or when ground is lost.

Abstract: An object of the present invention is to economize in power consumption of a semiconductor integrated circuit. The semiconductor integrated circuit has first and second capacitors electrically connected to a control electrode of a transistor. The first capacitor is used to input a signal therein and the second capacitor is used to change a threshold value relative to the input signal.

Abstract: The present invention is composed of: positive and negative control power sources P and N, first and second semiconductor device groups A and B in which a plurality of semiconductor devices 12 and 13 and also 15 and 16 are series-connected to these positive and negative control power sources P and N, switching signal source 17 that supplies ON/OFF control signals to semiconductor devices 12 and 13 and also 15 and 16 of these first and second semiconductor device groups A and B, and delay circuits 18 and 19 that delay for a specified time the ON/OFF control signals supplied to any one of semiconductor devices 12 and 13 and also 15 and 16 of first or second semiconductor device groups A and B from this switching signal source 17.

Abstract: According to this invention, there is provided a drive apparatus for a power device having high- and low-voltage main electrodes and a control electrode, including a circuit for decreasing a voltage of the control electrode to a voltage of the control electrode which is not higher than a threshold voltage of the power device before a voltage between the high- and low-voltage main electrodes enters an overshoot region in a case where the power device is to be turned off. Therefore, electron injection can be stopped before the voltage between the main electrodes rises, the stability of the current density can be improved, and current concentration, oscillation, and the like can be prevented to improve reliability.

Abstract: First main electrodes of second and third semiconductor elements are connected to the first main electrode of the first semiconductor element, control electrodes of the second and third semiconductor elements are connected to the control electrode of the first semiconductor element, a second main electrode of the second semiconductor element is connected to a first resistor, and a second main electrode of the third semiconductor element is connected to a second resistor. Second main-electrode voltages of the first and second semiconductor elements are compared with each other by a first comparator, a control voltage is supplied a control voltage to the control electrodes of the first and second semiconductor elements according to an output of the first comparator by control means. Second main-electrode voltages of the first and third semiconductor elements are compared with each other by a second comparator.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: A gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals, including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device.

Abstract: A semiconductor power converting apparatus includes a semiconductor element for controlling a current flowing between a collector and an emitter in response to a gate condition, a driving device connected to the gate, for driving the gate in response to a drive signal entered thereinto, a voltage applying device for applying both a forward bias and a reverse bias to the gate so as to set the emitter of the semiconductor element to a neutral potential, and a voltage dividing device for dividing a voltage appearing between the collector and the emitter of the semiconductor element, in which the drive signal is under OFF state, a voltage produced based upon the divided voltage by the voltage dividing device is applied to the gate, and the gate voltage is controlled in response to the voltage appearing between the collector and the emitter of the semiconductor element, thereby reducing the snubbed loss.