Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: An analog interface processing circuit includes a first and second signal processing interface, a processing system connected to the first and second signal processing interfaces, a biasing voltage source switchably coupled to said first signal processing interface via a first switch assembly and switchably coupled to said second signal processing interface via a second switch assembly, and a first control output of said processing system controllably coupled to said first switch assembly and a second control output of said processing system controllably couple to said second switch assembly.

Abstract: Techniques for reducing crowbar current are disclosed. In one embodiment, a circuit for reducing crowbar current comprises an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail. The circuit also comprises a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.

Abstract: A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.

Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: An analog-switch circuit (1) having: a resistor (R1); a resistor (R2); a CMOS analog switch (S1) in which a first end is connected to an input end (Vin) via the resistor (R1), and a second end is connected to an output end (Vout); and a CMOS analog switch (S2), in which a first end is connected to the first end of the analog switch (S1), and a second end is connected to a ground end via the resistor (R2). The CMOS analog switch (S2) is turned on or off in antiphase to the analog switch (S1).

Abstract: A switch control circuit has level shifters connected to a switch circuit to convert voltage levels of control signals, a negative potential generating circuit connected to the level shifter, to generate a negative potential, a negative potential output line supplying the negative potential to the level shifter, and a negative potential output line control circuit configured to control the potential of the negative potential output line. The negative potential output line control circuit has a power-supply setting circuit, an inverter inverting the output signal from the power-supply setting circuit, a first capacitor connected between an output terminal of the inverter and the negative potential output line, and a negative potential initialization circuit.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.

Abstract: I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time.

Abstract: A switch circuit includes: first, second, and third input-output terminals; a first switching element connected between the first and second input-output terminals; a second switching element connected between the third input-output terminal and a grounding point; a third switching element connected between the first and third input-output terminals; a fourth switching element connected between the second input-output terminal and the grounding point; a first control voltage applying terminal connected to control terminals of the first and second switching elements; a second control voltage applying terminal connected to control terminals of the third and fourth switching elements; first and second resistors connected between the control terminals of the first and second switching elements and the first control voltage applying terminal, respectively; and first and second diodes connected in parallel with the first and second resistors, respectively, and having cathodes connected to the first control voltage

Abstract: A semiconductor device includes a first transistor having a p-channel type, a second transistor having an n-channel type, and a third transistor with low off-state current between a high potential power supply line and a low potential power supply line, and a source terminal and a drain terminal of the third transistor are connected so that the third transistor is connected in series with the first transistor and the second transistor between the high potential power supply line and the low potential power supply line, and the third transistor is turned off when both the first transistor and the second transistor are in conducting states.

Abstract: Direct-path current is reduced in a semiconductor device including CMOS circuits. One embodiment of the present invention is a method for driving a semiconductor device that includes a first CMOS circuit between power supply lines, a first transistor between the power supply lines, a second CMOS circuit between the power supply lines, and a second transistor between an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit. The first transistor and the second transistor each have lower off-state current than a transistor included in the first CMOS circuit. In a period during which the voltage of a first signal input to the first CMOS circuit is changed, a second signal is input to the first transistor and the second transistor to turn off the first transistor and the second transistor.

Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.

Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

Abstract: This document discusses, among other things, a switch circuit including a switch having a low-impedance state configured to couple a first node to a second node and a high-impedance state configured to isolate the first node from the second node. The switch circuit can include an arbiter circuit configured to receive a source voltage and an input signal, to provide, at an output, the higher voltage of the source voltage and the input signal, and to isolate the input signal form ground when the input signal has a lower voltage than the source voltage.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: A semiconductor processing device (10) of the present invention includes a processing circuit (1), a digital-analog conversion circuit (2), an output control circuit (3), at least one output port circuit (4), a connection control circuit (5), and an output switch circuit (6). The output port circuit (4) includes an output buffer (41), a first switch element (SW1), and a second switch element (SW2, SW3). When the second switch element is connected to the side of an output amplifier (42), the output port circuit (4) controls the ON resistance of a P channel MOS transistor (41a) and an N channel MOS transistor (41b) based on a signal amplified at the output amplifier (42) to output an analog signal from the output buffer (41).

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: A transmission gate includes first and second transmission path terminals, a series connection of first and second field effect transistors (FETs), and a control circuit. The channels of the first and second FETs are coupled in series between the first transmission path terminal and the second transmission path terminal, such that a channel contact of the first FET is coupled to the second transmission path terminal and a channel contact of the second FET is coupled to the first transmission path terminal.

Abstract: The present invention provides a high-side driver circuit including a power transistor, the first transistor, the second transistor, the second capacitor, the second diode, a start-up circuit. The start-up circuit is coupled between a resistor and the second capacitor to complete a gate driving circuit. And, the aforementioned resistor can either be the gate resistance of the power transistor or an external resistor. The design of start-up circuit enables the functionality of the bootstrap capacitor of being charged to a designate voltage level. Thus, the depletion-mode transistor can be controlled to turn on/off without a floating voltage source or a negative voltage source.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

Abstract: A dual pole dual through switch for switching between at least four states. The switch comprises four transistors such as N-channel Metal Oxide Semiconductor transistors, such that at each state at most one transistor is in “on” state, and the others are in “off” state. Each transistor has its own control circuit, which provides zero or negative voltage to the drain of the transistor, positive voltage to the source of the transistor, and control alternating voltage to the gate of the transistor. The switch can be used on-chip for devices. Such devices may include a base station or a handset of a cordless phone.

Abstract: In at least one operation control TFT (27N, 27P) in a control circuit (27), an impurity of a type that generates an impurity level of a channel region (33c) is included in the channel region (33c) as a threshold adjustment impurity, and the concentration of the threshold adjustment impurity is made higher than the concentration of the threshold adjustment impurity in channel regions (33c) of other TFTs (21, 25, 28) of the same type, thus causing the absolute value of the threshold voltage to be greater than that of the other TFTs (21, 25, 28) of the same type.

Abstract: A gate drive circuit capable of turning on a semiconductor switching element at high speed, which includes: a buffer circuit including a turn-on-drive switching element and a turn-off-drive switching element that are complementarily turned on and off, for driving the semiconductor switching element; a first DC voltage supply including a positive electrode connected to the source or emitter of the turn-on-drive switching element and a negative electrode connected to a reference potential; and a second DC voltage supply including a positive electrode connected to the source or emitter of the turn-off-drive switching element and a negative electrode connected to the reference potential.

Abstract: An exemplary circuit for clearing data stored in a complementary metal-oxide-semiconductor (CMOS) includes a power circuit and a button circuit. The power circuit supplies power for the CMOS. The button circuit is configured to clear data stored in the CMOS, and includes a switch and an electronic switch element. A first terminal of the switch is grounded, and a second terminal of the switch is coupled to a first terminal of the electronic switch element. A second terminal of the electronic switch element is grounded. A third terminal of the electronic switch element is coupled to the CMOS. When the switch is closed, the second terminal of the electronic switch element is connected to the third terminal of the electronic switch element, and the data stored in the CMOS is cleared.

Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

Abstract: A system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage signal.

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract: A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal.

Abstract: An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Abstract: A power switch circuit includes a control circuit, and first and second detecting circuits. The control circuit includes first and second field effect transistors (FETs) and first and second sensing resistors. The first detecting circuit includes two input terminals connected to the first and second ends of the first sensing resistor and an output terminal connected to the first FET. The first detecting circuit controls the first FET to be turned on or turned off according to the voltages of the first and second ends of the first sensing resistor. The second detecting circuit includes two input terminals connected to the first and second ends of the second sensing resistor and an output terminal connected to the second FET. The second detecting circuit controls the second FET to be turned on or turned off according to the voltages of the first and second ends of the second sensing resistor.

Abstract: Conventional current sharing circuits, which can be used in drivers for liquid crystal displays (LCDs), for example, often use bipolar transistors. However, bipolar transistors are not available in many CMOS processes. Thus, a current sharing circuit is provided here that employs CMOS transistors. In particular, the circuit provided here uses a current mirror and pass circuit to assist in providing this current sharing function.

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: A switch can be implemented by a switch circuit, which can include a pair of NMOS transistors connected in series as pass-through transistors to transmit an input signal at an input terminal to produce an output signal at output terminal in response to an active state of a switching signal, and a pair of PMOS transistors connected in series as pass-through transistors to transmit the input signal at the input terminal to produce the output signal at output terminal in response to the active state of the switching signal. The switch circuit can also include a switch network connecting, in response to the active state of the switching signal, sources to bodies of the pairs of NMOS and PMOS transistors, and connecting, in response to an inactive state of the switching signal, the bodies of the pair of NMOS transistors to a first reference voltage, the bodies of the pair of PMOS transistors to a second reference voltage, and the sources of the pairs of NMOS and PMOS transistors to a third reference voltage.

Abstract: A semiconductor chip includes at least one power semiconductor switch configured to activate and deactivate current conduction from a first supply terminal, which is connected to a first supply line that provides an unstabilized first supply voltage, to the at least one output terminal in accordance with a respective control signal. In operation, the unstabilized first supply voltage is monitored and an under-voltage is signaled when the unstabilized first supply voltage falls below a first threshold value. The first supply terminal is short circuited with a third terminal when the an under-voltage is signaled.

Abstract: Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

Abstract: Provided is a transmission gate capable of adapting to various input voltages to attain high S/N characteristics. The transmission gate includes: a PMOS transistor (11) which includes a drain to which an input voltage (Vin) is input, is turned ON when a voltage (Vin?Vs1) is input to a gate thereof, and includes a source from which the input voltage (Vin) is output as an output voltage (Vout); and an NMOS transistor (12) which has a gate length, a gate width, a gate oxide thickness, and an absolute value of a threshold voltage which are the same as those of the PMOS transistor (11), includes a drain to which the input voltage (Vin) is input, is turned ON when a voltage (Vin+Vs1) is input to a gate thereof, and includes a source from which the input voltage (Vin) is output as the output voltage (Vout).