Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry connected between a high voltage source and a low voltage source. The core circuitry may include multiple transistors including a first transistor of a first polarity type and a second transistor of a second polarity type that is different than the first polarity type. The integrated circuit may include voltage regulation circuitry connected between an external positive voltage source and ground. The voltage regulation circuitry may operate to provide the low voltage source to the core circuitry. The low voltage source may be equal to or higher than ground. The voltage regulation circuitry may further operate to body bias the multiple transistors with a single voltage that is applied to a body terminal of the first transistor and the second transistor.

Abstract: A method and system of monitoring a reliability of a semiconductor circuit are provided. A current consumption of a first ring oscillator that is in static state is measured at predetermined intervals. Each measured current consumption value is stored. A baseline current consumption value of the first ring oscillator is determined based on the stored current consumption values. A latest measured current consumption value of the first ring oscillator is compared to the baseline current consumption value. Upon determining that the latest measured current consumption value is above a threshold deviation from the baseline current consumption value, the first ring oscillator is identified to have a dielectric breakdown degradation.

Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.

Abstract: A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second switch while turning ON the first switch. A third driver coupled to a third switch is powered by providing a unidirectional path between the first supply node of a second driver and the first supply node of the third driver and by keeping OFF the first and third switch while turning ON the second switch.

Abstract: A memory system includes an isolated first well of a first polarity and an array of volatile memory cells. Each of the memory cells includes a first set of transistors in the isolated first well, and a second set of transistors. A source bias circuit is coupled to the array of volatile memory cells. At least a portion of the source bias circuit is in the isolated first well and coupled to source electrodes of the first set of transistors of each of the memory cells. A control circuit is configured to enable the source bias circuit.

Abstract: Related-art back bias generation circuits cause a problem where a long time is required for transition between an operating state and a standby state because driving power is lowered to reduce the power consumption in the standby state. A back bias generation circuit outputs a predetermined voltage. The predetermined voltage is the back bias voltage of a substrate in a standby mode. A bias control circuit stores an electrical charge while a circuit block is in an operating mode, supplies the stored electrical charge to the substrate of a MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supplies the output of the back bias generation circuit to the substrate of the MOSFET.

Abstract: A transistor biasing circuit including a first controller configured to receive a sensor signal generated based on the performance of one or more transistors of a digital circuit and to compare the sensor signal with a reference signal and to generate a first biasing voltage control signal; a first actuator configured to generate a first biasing voltage based on the first biasing voltage control signal; a second actuator configured to generate a second biasing voltage based on a second biasing voltage control signal; and a second controller configured to generate the second biasing voltage control signal based on an intermediate voltage level generated based on the first and second biasing voltages.

Abstract: Roughness is eliminated and planarization is achieved by a metal oxide film on a surface of a lower electrode. Consequently, damage on a capacitive film caused by the roughness of the lower electrode is reduced. Furthermore, physical damage on the capacitive film is reduced by forming a first layer of an upper electrode by, for example, CVD. Consequently, the damage on the capacitive film is suppressed, and the reliability of the capacitive film is improved. Furthermore, not by forming the whole upper electrode by the CVD or the like, but by forming a second layer by PCD or the like on the first layer, an increase in resistance of the upper electrode is suppressed as well.

Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.

Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.

Abstract: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.

Abstract: A switch apparatus is provided, including: a main switch connected between first and second terminals, and electrically connecting or disconnecting the first and second terminals according to gate voltage applied to a gate terminal; a voltage output unit having a voltage divider including a first voltage-division resistance on the first terminal side and a second voltage-division resistance on the second terminal side, and outputting voltage corresponding to voltage of the first terminal and voltage of the second terminal if the main switch is caused to enter a connected state; a buffer outputting voltage following output voltage of the voltage output unit in a connected state of the main switch; and a switch control circuit supplying first voltage corresponding to output voltage of the buffer to the gate terminal, and supplying a second voltage corresponding to output voltage of the buffer to a bulk terminal of the main switch.

Abstract: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.

Abstract: A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.

Abstract: [Object] To provide a semiconductor apparatus and a method of controlling a MOS transistor, with which a leak current of the MOS transistor can be suppressed. [Solving Means] A semiconductor apparatus includes a MOS transistor and a voltage application unit that applies, when the MOS transistor is off, a voltage for controlling a threshold value of the MOS transistor in a shallower direction onto a substrate of the MOS transistor.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: An integrated circuit includes a first logic circuit region comprising a first regional clock network for supplying a first regional clock signal to digital logic circuit(s); and a clock gating circuit to derive the first regional clock signal from a clock signal and selectively apply and interrupt the first regional clock signal in accordance with a state select signal. The first logic circuit region comprises a first back bias voltage grid connected to respective bodies of PMOS transistors of the digital logic circuit(s) and a second back bias voltage grid connected to respective bodies of NMOS transistors of the digital logic circuit(s). The integrated circuit further comprises a controllable back bias voltage generator configured to adjust a first back bias voltage of the first back bias voltage grid, and to adjust a back bias voltage of the second back bias voltage grid, in accordance with the state select signal.

Abstract: A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet.

Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.

Abstract: In an embodiment, set forth by way of example and not limitation, an integrated circuit includes charge pump circuitry formed on an integrated circuit (IC) chip, a first protective circuit formed on the integrated circuit chip and coupling the first output node to a first IC port, a second protective circuit formed on the integrated circuit chip and coupling the second output node to a second IC port, and a third protective circuit formed on the integrated circuit chip and coupling the power input node to a power input IC port.

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

Abstract: In one embodiment, a hot swap circuit is disclosed. The hot swap circuit includes a first switch connected to a power input line. The hot swap circuit also includes a first capacitor connected to the first switch that is charged when the first switch is closed. The hot swap circuit further includes a second switch connected to the first switch and the first capacitor. The hot swap circuit additionally includes an input capacitor connected to the second switch and located in parallel with an input line to a power system. When the second switch is closed, the input capacitor is charged.

Abstract: A charge pump circuit may include: input units suitable for receiving a first input pulse signals and outputting second input pulse signals that are out of phase; an internal voltage generation unit suitable for generating an internal voltage by performing a voltage pumping operation in response to an external voltage and the second input pulse signals, and adjusting a well bias voltage at a power-up period and a normal operation period after the power-up period, in response to a switching control signal; and a switching control signal generation unit suitable for generating the switching control signal which is activated differently on the power-up period and the normal operation period.

Abstract: Low-power, high-performance voltage regulator circuit devices are disclosed and described. In one embodiment, such a device can include a first stage circuitry configured to generate a high voltage reference from a low voltage reference, a second stage circuitry coupled to the first stage circuitry, the second stage circuitry configured to receive the high voltage reference and output a voltage regulated signal, and a switch disposed between and coupled to the first stage circuitry and the second stage circuitry, the switch being configured to couple and uncouple the first stage circuitry from the second stage circuitry.

Abstract: A switched capacitor DC-DC converter circuit and a method for outputting voltage using the same are disclosed. The circuit includes a switched capacitor circuit and a body bias control circuit. The on-resistance of the transistor in the switched capacitor circuit is increased by the body bias control circuit, so as to lower the voltage ripple generated from the output voltage.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: A power amplifier include an amplifier including at least one field effect transistor (FET) that operates in an amplifying stage configured to amplify an input signal, and a body controller configured to control a bias voltage of a body terminal of the FET based on a power of the input signal. The body controller performs controlling so that the bias voltage of the body terminal is reduced in response to the power of the input signal being increased. Accordingly, such a power amplifier exhibits improved linearity.

Abstract: According to one embodiment, a switched capacitor power supply circuit includes a switched capacitor power supply circuit unit that supplies a voltage obtained by converting an input voltage with a predetermined conversion ratio as an output voltage by switching a connection configuration between a plurality of capacitors that perform charge and discharge, and a control circuit that switches the connection configuration between the plurality of capacitors according to the output voltage to change the conversion ratio.

Abstract: A semiconductor device includes a first circuit configured to generate a first voltage based on a first current, a second circuit that includes a first transistor of a first conductivity type having a first terminal, a second terminal, and a first gate, the second circuit configured to generate a second voltage based on a voltage difference between the first terminal and the second terminal, and a third circuit configured to compare the first voltage and the second voltage, and generate a third voltage for adjusting a substrate bias of the first transistor, based on the comparison result.

Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Abstract: Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described.

Abstract: A switching circuit includes a first diode coupled between a first terminal and a second terminal, a second diode coupled between the first terminal and a third terminal, and a bias circuit coupled to the first terminal and configured to bias the first diode on and the second diode off in a first switch state and to bias the first diode off and the second diode on in a second switch state, the bias circuit including a voltage converter configured to convert a fixed voltage to an intermediate voltage and a current source coupled in series with the voltage converter.

Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

Abstract: A display driving integrated circuit is provided which drives a plurality of gate lines included in a display panel. The display driving integrated circuit includes: a charge pump configured to change a voltage from an external power source to generate an output voltage; and a gate line driver configured to drive the plurality of gate lines based on the output voltage. The charge pump may operate in one of a low-current mode and a high-current mode based on a size of the display panel.

Abstract: An integrated circuit, such as included as a portion of a sensor node, can include a regulator circuit having an input coupleable to an energy harvesting transducer. The integrated circuit can include a wireless receiver circuit coupled to the regulator circuit and configured to wirelessly receive at least enough operating energy to establish operation of the sensor node without requiring the energy harvesting transducer. The integrated circuit can include a digital processor circuit coupled to the regulator circuit and a power management processor circuit. The digital processor circuit or one or more other circuits can include a subthreshold operational mode established by the power management processor circuit based on the selected energy consumption level. For example, establishing the subthreshold operational mode can include adjusting or selecting a supply voltage so as to establish subthreshold operation of a field effect transistor (FET) in the digital processor circuit or other circuits.

Abstract: The present invention relates to an output-current detection IC chip for diode sensors and a diode sensor device, which reduce the influence by a leak current of a protection circuit. The present invention is equipped with a sensor unit in which anodes of N (N being an integer of 2 or more) diode sensors are connected to each other, a common terminal connected to a connection portion where the anodes are connected to each other, N input terminals connected to cathodes of the diode sensors, N+1 protection circuits connected to the input terminals and the common terminal, an I-V conversion circuit which converts an output current of each diode sensor into a voltage, a chopper circuit which switches the polarity of the output current and inputs the same to the I-V conversion circuit, and a dummy protection circuit connected to the input of the I-V conversion circuit.

Abstract: A power control circuit for a hearing device is devised. The power control circuit has a switched-capacitor power supply, a substrate bias control circuit, a reference circuit, a performance monitor circuit, a first plurality of N-type semiconductors and a second plurality of P-type semiconductors. The performance monitor circuit is adapted to monitor the supply voltage, the first substrate bias control voltage and the second substrate bias control voltage, respectively, and is adapted to provide a measure of performance to the substrate bias control circuit. The substrate bias control circuit is adapted to optimize the current consumption of the circuit by continuously altering the levels of the first substrate bias control voltage and the second substrate bias control voltage based on the performance measurement.

Abstract: A solid-state image pickup device includes: a pixel portion in which a plurality of pixels are arrayed in matrix; and an Analog-Digital converter. The Analog-Digital converter converts pixel signals, which are generated in the pixel portion, from analog signals into digital signals. The Analog-Digital converter includes: a comparator; and a counter. The comparator compares the analog signals, each of which corresponds to each of the plurality of pixels, with a reference signal. The comparator includes: a first differential transistor to which the reference signal is input; a second differential transistor to which the analog signals are input; a first load transistor; a second load transistor; and a current source transistor. A fluctuation of a voltage between a gate and a source of the first differential transistor is suppressed. This fluctuation follows a voltage fluctuation of a node connected commonly to the second differential transistor and the second load transistor.

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract: A semiconductor device includes a substrate, an active layer, a transistor, and a capacitor. The active layer is disposed on the substrate, and the active layer is divided into a first portion and a second portion. The transistor and the capacitor are disposed on the substrate. The transistor includes the second portion, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively and electrically connected to the second portion. The gate electrode is disposed on the second portion. The capacitor includes the first portion, a first electrode, a first insulating layer, and a second electrode. The first electrode is electrically connected to the first portion and the source electrode. The first insulating layer is disposed on the first portion. The second electrode is disposed on the first insulating layer and is electrically connected to the gate electrode.

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The gate electrode is disposed in trenches extending in a first direction parallel to the first main surface. The gate electrode is electrically coupled to a gate terminal. The channel region and the drift zone are disposed along the first direction between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. The conductive layer is electrically connected to the gate terminal.

Abstract: A field effect transistor (FET) with a graphene layer as a channel layer is disclosed. The FET provides two gate electrodes, one of which receives the gate bias, while, the other receives a reference bias. An intermediate electrode made of ohmic metal to the graphene layer is provided between the two gate electrodes. The second gate electrode receiving the reference bias suppresses the hole injection into the channel beneath the first gate electrode.

Abstract: A transistor includes a channel layer in which a plurality of graphene whose edge portions are terminated with modifying groups different from each other are bonded to each other; a gate electrode formed on the channel layer via a gate insulating film; and a source electrode and a drain electrode formed on the channel layer.

Abstract: A circuit for controlling power supply includes a first switch situated between a first power supply and a first node coupled to a circuit block, a second switch situated between a second power supply having a voltage value different than the first power supply and a second node coupled to a back gate of a transistor of the circuit block, a third switch situated between the first node and the second node, and a control unit configured to place the second switch in an “on” state and the third switch in an “off” state during an “on” state of the first switch, and to place the second switch in an “off” state and the third switch in an “on” state during an “off” state of the first switch.

Abstract: An electronic device includes a transistor having a body and a body biasing circuit. The body biasing circuit includes a threshold estimator circuit to estimate a threshold voltage of the transistor and a comparison circuit to compare the threshold voltage of the transistor to a reference threshold voltage and to generate a comparison signal based thereupon. A bias adjust circuit generates a body biasing voltage that biases the body of the transistor as a function of the comparison signal, the body biasing voltage being a voltage that, when applied to the body of the transistor, adjusts the threshold voltage thereof to be equal to the reference threshold voltage.

Abstract: An integrated circuit includes an operational circuit and a test circuit for measuring a leakage current associated with all or part of the operational circuit. The leakage current measurement circuit may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first switching control signal generation circuit configured to generate a first switching control signal which is enabled in synchronization with a time when a first delay period has passed from a time when a power-down mode is entered. The semiconductor device may include a second switching control signal generation circuit configured to generate a second switching control signal which is enabled during a period from a time when a read operation mode or a write operation mode is entered to a time when a second delay period has passed.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a respective gate and body. A resonance circuit connects the body of each of the at least one FET to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value and an approximately open circuit at an operating frequency, wherein the approximately closed circuit allows removal of surface charge from the body to the reference node.