Abstract: The invention relates to a circuit arrangement which includes a subvoltage generating unit and a voltage multiplier for generating at least one voltage Vmult, it being arranged to control the voltage multiplier by switching the voltage multiplier to a direct mode during a start time. The invention also relates to an arrangement for driving a display device, to a display device which includes such an arrangement, to an electronic apparatus which is provided with a display device for the display of image data which includes an arrangement for driving the display unit, and to a method of starting a circuit arrangement 15 which includes a subvoltage generating unit 40, a voltage multiplier 20 and a start control unit 30.

Abstract: To provide a voltage generating circuit for generating a boosted voltage on the basis of a power source voltage or any voltage.

Abstract: A low power charge pump system having a plurality of charge pump cells. Each cell is a three transistor device that operates to transfer voltage from an input node to an output node of the cell when the input voltage is substantially greater than the output voltage and to block when the output voltage is substantially greater than the input voltage. Each cell has a pump capacitor is connected between a clock and its output, the odd-numbered cells having a first clock connected to their pump capacitors and the even-numbered cells having a second clock connected to their pump capacitors. During a first phase of either the first or second clock, the cell operates to transfer a voltage on its input node to its output node and during a second phase, the cell operates to boost its output voltage by a predetermined amount.

Abstract: A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that

Abstract: A switch circuit includes an input terminal, an internal circuit, and first and second MOS transistors. The input terminal receives an input signal. The internal circuit executes a predetermined function. The first MOS transistor is a first conductivity type MOS transistor. The first MOS transistor is coupled between the input terminal and the internal circuit, and has a control gate receiving a control signal, a first electrode coupled to the input terminal and a second electrode. The second MOS transistor is a second conductivity type MOS transistor of a type opposite the first conductivity type MOS transistor. The second MOS transistor is coupled between the input terminal and the internal circuit, and has a control gate receiving a signal having a phase opposite the control signal, a first electrode coupled to the second electrode of the first MOS transistor and a second electrode coupled to the internal circuit.

Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

Abstract: A method of providing multiple voltage outputs includes receiving an input signal from a multifunctional pump. The method also includes sending a first output signal based on the input signal using a first switch and sending a second output signal based on the input signal using a second switch and a transistor.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A complementary source follower circuit has an N-channel type transistor and a P-channel transistor. The threshold voltage of each transistor is independently controlled by a back bias voltage control circuit so that the input voltage and the output voltage relationship can be made linear without the use of an additional circuit such as a level shifting circuit. Also, power consumption can be reduced when the circuit is in standby mode by using the back bias voltage control circuit to achieve non-linearity. A back bias voltage control circuit can also be used to control the threshold voltage of a transistor in series with a resistance load to reduce power usage.

Abstract: The apparatus for generating a driving voltage for a sense amplifier has at least voltage output means, and first and second core voltage step-up means. The voltage output means outputs a voltage for driving the sense amplifier to a node. Each of the first and second core voltage step-up means are connected between a power supply and the node. The first and second core voltage step-up means are turned on in sequence to elevate the voltage level of the node connected with the sense amplifier up to the level of the power supply. This enhances the performance of the sense amplifier as well as the execute detection amplification in a short time period. The first and second core voltage step-up means are turned on in sequence to elevate the core voltage as the driving voltage, reducing the power noise. Each core voltage step-up driver may be installed in each bank to reduce power consumption.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.

Abstract: A voltage selector circuit determines the highest of at least two available input voltages, and connects the highest voltage to an output terminal. The circuit includes a comparator having first and second FETs having their sources connected to first and second input voltages (V1 and V2), and which are biased with first and second bias currents. The first FET is driven on regeneratively when V1>V2, and the second FET is driven on regeneratively when V2>V1. A first switch connects V1 to an output terminal when the first FET is driven on, and a second switch connects V2 to the output terminal when the second FET is driven on. First and second diode-connected FETs are connected below the first and second FETs and carry their respective bias currents, thereby limiting the voltage swings on the FETs' gates and providing control over hysteresis.

Abstract: An output circuit includes: a power supply unit; an output MIS transistor connected to the power supply unit; a reference MIS transistor that is connected to the power supply unit and is invariably in ON state; a current supply unit for generating a reference voltage Vref; an output terminal through which a current is supplied to a load circuit; a comparator; a logic circuit; and a control circuit for carrying out the ON/OFF control of the output MIS transistor. Comparison is made between the reference voltage Vref and output terminal voltage Vout by utilizing the ON-state resistances of the output and reference MIS transistors, thus detecting the magnitude of an output current. If the output current exceeds the target value, the output MIS transistor is turned OFF, thereby protecting it from an excessive current.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: A semiconductor integrated circuit with stabilizing capacity has a voltage drop circuit that drops a power supply voltage to a first voltage Vcc1 and supplies the Vcc1 to a plurality of function blocks; a stabilizing capacity that stabilizes the Vcc1; and a plurality of voltage switching circuits each of which is provided in each of the function blocks and selectively switches between the Vcc1 and a base voltage Vss to produce a second voltage Vcc2 and supplies the Vcc2 to each function block, and each of the function blocks forms a capacity for stabilizing an output of the voltage drop circuit by means of its semiconductor structure by the Vcc1 and the Vcc2 applied thereto.

Abstract: A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.

Abstract: A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.

Abstract: A leakage compensation circuit compensates for current changes that result from bulk leakage currents that occur when a current source transistor is connected to a number of switches. A leakage current flows out of a switch, while a compensation transistor connected to the switch sinks a current substantially equal to the leakage current.

Abstract: A buffer circuit is used to provide hysteresis, which can reduce the negative effects of noise in digital circuits. Reducing the number of transistors in the buffer circuit reduces the amount of space the circuit occupies and reduces power consumption. By connecting a voltage-coupling element between the body of a transistor in a first inverter and an output of a second inverter, the voltage-coupling element can control the hysteresis of the buffer circuit.

Abstract: A voltage supply circuit is capable of improving an operating speed of the circuit while lowering power consumption. An internal power supply voltage that is dropped and an internal ground voltage that is raised, from an external power supply, are generated and then supplied to an internal circuit. Therefore, when the circuit is driven, a swing width of a signal is reduced to reduce a dynamic power. When the internal circuit is driven at a low voltage, the back bias of a transistor is varied to lower the threshold voltage. Thus, the operating speed can be improved. Also, in a standby mode, the threshold voltage is increased to minimize the amount of current flowing at a sub-threshold voltage below the threshold voltage, thus reducing a static power.

Abstract: A semiconductor integrated circuit and power control method use one of a supply voltage of the circuit and a delay time of the circuit to control a substrate bias voltage applied to a substrate of an insulated gate field effect transistor. High speed operation, consuming a small amount of power, is achieved. A CMOS circuit has a widened operating voltage range, with reduced leak currents in a standby mode in a range of high supply voltage, reducing power consumption of the CMOS circuit, and increasing operating speed of the CMOS circuit in the range of low supply voltage.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: Circuits and methods for optimizing operating performance of an integrated circuit device within a maximum allowed current by varying a period of a clock signal based on an amount of current consumed by the integrated circuit device. In one aspect, an integrated circuit device includes a plurality of functional blocks, a power supply line which supplies an internal power supply voltage to the functional blocks, a voltage converter circuit which controls an amount of current supplied to the power supply line by comparing a reference voltage with the internal power supply voltage, and a clock generator circuit which generates a clock signal that is applied to the functional blocks. The clock generator circuit adjusts a period of the clock signal according to the amount of current supplied to the power supply line.

Abstract: An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.

Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

Abstract: A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.

Abstract: A method and apparatus for generating a high voltage in a device includes a boosting means that precharges a first node, a second node and a substrate voltage of a charge transfer transistor. The charge transfer transistor may perform a charge sharing operation between the first node and a high voltage generating terminal based on a voltage at the second node. The first node may be boosted to a first voltage, and the substrate voltage may be increased based on a voltage at the high voltage generating terminal. The second node may be boosted to a second voltage different than the first voltage, and the substrate voltage may be increased based on a voltage at the high voltage generating terminal. The substrate voltage may also be increased based on changes to the first voltage of the first node that occur during the charge sharing operation.

Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.

Abstract: Different reference voltages are employed in different logical electrical circuits. In the conventional arts, a reference voltage circuit is only employed in a specific logical electrical circuit or a reference voltage circuit with fuse can changes a reference voltage by fusing the fuse. Nevertheless, the reference voltage circuit with fuse is still only employed in a specific system of logical circuit regardless of the fuse is fused or unfused. A select reference voltage circuit for a logical electrical system of the present invention can solve the problem. Therefore, the select reference voltage method for a logical electrical system can be employed in different systems having respective different system voltages.

Abstract: A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

Abstract: A drive apparatus supplies electric power to a solenoid of an inductive load from a battery and a capacitor to improve response of the load. The drive apparatus comprises switches for switching between a first state where a negative side of the battery is connected to a positive side of the battery, and a second state where the negative side of the capacitor is connected to the negative side of the battery. When the load is in operation, the voltage applied to the solenoid is raised by the voltage of the battery as the first state, so that the current flowing into the solenoid rises sharply to improve response of the load. When the operation of the load is to be stopped, the electric power to the solenoid is interrupted, and the energy accumulated in the solenoid is recovered by the capacitor as the second state.

Abstract: The invention relates to a charge pump.

Abstract: In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

Abstract: A charge pump power supply includes two or more modes of operation. An input protection circuit is connected between an input of the power supply and a voltage source. The input protection circuit regulates the voltage at the input of the power supply, limits current at the input when switching from a weaker mode to a stronger mode, and prevents current reversal when switching from a stronger mode to a weaker mode. In some modes, the power supply continuously provides current to the load, obviating the need for an output capacitor.

Abstract: The invention concerns a semi-conductor device comprising on a substrate: a first dynamic threshold voltage MOS transistor (10), with a gate (116), and a channel (111) of a first conductivity type, and a current limiter means (20) connected between the gate and the channel of said first transistor. In accordance with the invention, this first transistor is fitted with a first doped zone (160) of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone (124) of a second conductivity type, placed against the first doped zone and electrically connected to the first zone by an ohmic connection. Application to the manufacture of CMOS circuits.

Abstract: A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

Abstract: A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

Abstract: Embodiments of the present invention provide an amplifier circuit and method that can be used to save power or reduce distortion in an electronic system, such as a wireless communication system. In one embodiment, the present invention includes an amplifier circuit comprising a transistor having a gate terminal, drain terminal, body terminal, and a load. An input signal has different signal envelopes during different time periods. A control signal coupled to the body terminal is used to change the voltage on the body terminal when the input receives different envelopes. Accordingly, the amplifier can be biased to use less power when lower envelopes are being received. Electronic systems, such as wireless communication systems, can realize advantageous performance enhancements by utilizing the amplifier and other techniques employed by embodiments of the present invention.

Abstract: A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.

Abstract: In an input/output buffer circuit to which input signal voltage VBUS higher than power source voltage VDD is possibly inputted to an input/output terminal BUS, a gate terminal G3 is controlled by a signal in-phase to a input/output mode switching signal CNT outputted from a buffer circuit 5, and the power source voltage VDD is applied when it is an input mode. When the input signal voltage VBUS is lower than voltage obtained by applying threshold voltage Vthp of PMOS transistor to the power source voltage VDD (VBUS<VDD+Vthp), voltage obtained by subtracting threshold voltage Vthn of NMOS transistor from the power source voltage VDD is applied to a gate terminal G1 (VG1=VDD−Vthn). On condition that Vthn>Vthp, a PMOS transistor P1 gets conductive, whereby the power source voltage VDD is applied to a gate terminal G2 and PMOS transistor P2 is turned off. Thereby, an unnecessary current path is not formed.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract: A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the comparator circuit is used to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. The high or low comparator output signal is transmitted to the switch control circuit, which utilizes a pair of level shifters to control the pair of PMOS switches, which in turn couple one of the first and second voltage sources to the output node.

Abstract: A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.

Abstract: A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.

Abstract: A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

Abstract: A semiconductor device includes a boosting circuit for supplying a power supply voltage during a standby state of the semiconductor device. The boosting circuit includes a charge pump circuit and first and second detection circuits for detecting an output voltage of the charge pump circuit. The second detection circuit is operated by a DC current greater than that of the first detection circuit, and is activated by an output (Vdet1) from the first detection circuit. The charge pump circuit is activated based on at least an output (Vdet2) from the second detection circuit.

Abstract: A threshold voltage compensation method and circuit compensates a bias voltage applied to a transistor gate to account for variations in the transistors threshold voltage. In one embodiment, a logic stack includes three transistors in series between a high voltage source and ground with a higt voltage output between the first and second transistor and a full swing output between the second transistor and the third transistor. A bias voltage is applied to the gate of the second transistor to provide a minimum voltage level for the high voltage output. As the threshold voltage of the second transistor varies, the bias voltage is adjusted to compensate for the threshold voltage level variance and maintain the minimum voltage level for the higt voltage output.

Abstract: In the disclosed semiconductor integrated circuit, a plurality of power supply terminals of the logic circuit block are connected to the actual power supply line via the leak current cut-off circuit. When the logic circuit block is to be activated, the delay control circuit controls the leak current cut-off circuit to electrically connect the power supply terminal to the actual power supply line with a delay of the predetermined time. Therefore, when the logic circuit block is activated, voltage drop of the actual power supply line can be lowered to a small value and erroneous operation of the other logic circuit block in the activated condition due to the power supply noise can be prevented.