Abstract: A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.

Abstract: A system is disclosed. The system includes a first circuit, the first circuit includes a bias device for allowing the first circuit to transition between a first mode and a second mode. The system further includes a second circuit which controls the bias device. The second circuit provides a bias voltage at a sub-threshold voltage level to the bias device when the first device is in one of the first and the second mode. The second circuit provides a bias voltage at a threshold voltage level or higher when the first device is in one of the first and the second mode. Accordingly, the transition time between modes of the first circuit is minimized.

Abstract: A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that drive the gates of the pass transistors. The use of separate circuits to the gate and the wells further reduces leakage. In the condition of power supply voltage and signal levels that are near the thresholds of the FETs involved, one or more Schottky diodes may be used across pn junctions in the FETs that will prevent turning on the pn junctions.

Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: A plurality of circuit blocks are provided in a semiconductor device which collects and corrects impairment quantities of discretionary areas in a circuit group of various types having random couplings. The semiconductor device is provided with a detector, which is arranged in each circuit block and detects an electric signal of an element in the circuit block; a wiring wherein each detector output passes through; a plurality of switches for feeding the wiring with each detector output; and a buffer connected to the wiring and passes through a direct current voltage.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Abstract: Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: Embodiments of the invention comprise methods, apparatuses and systems for a dynamic bias control circuit configured to dynamically bias an amplifier. The dynamic bias control circuitry includes four branches. Each of the four branches includes a transistor operably coupled in series between a current source and a reference voltage. Each branch also includes a storage element having a first terminal and a second terminal and configured for selectively coupling the first terminal to the reference voltage, selectively coupling the first terminal to a node located between the current source and a drain of the transistor, selectively coupling the second terminal to the node, and selectively coupling the second terminal to an output.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: An integrated circuit including a voltage generator for generating a body bias voltage is described. The voltage generator includes a charge source and a voltage regulator coupled to the charge source. Transistors are coupled to the charge source to receive the body bias voltage from the voltage generator.

Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.

Abstract: A body-biased enhanced current mirror circuit is disclosed wherein the body voltage of a current mirror device is adjusted to compensate for the effect of changes in the output voltage on the output current, increasing the output impedance. For each instance of the current mirror, this approach has the advantage of requiring no additional margin in operating voltage and of consuming no more circuit area than prior art current mirror designs. In addition, the body-biased enhanced current mirror circuit provides a stable reference current to output current ratio over a wide operating range. An auxiliary MOSFET current mirror device with the body connected to ground may be added in parallel with the body-biased current mirror device to eliminate a non-monotonicity of the current output.

Abstract: An integrated circuit comprising at least one MOS-type transistor, further comprising a system for detecting the variations of the electrical quantities of the at least one transistor, and a biasing device modifying the bias voltage of the bulk of the at least one transistor according to the variations measured by the detection system.

Abstract: In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.

Abstract: In the current drive section, a wiring for setting a substrate potential is separately provided from a wiring of a power potential VDD so that substrate potentials of P-channel MOS transistors within respective drive cells become the same regardless of the distance from the power pad (power potential VDD) to each drive cell.

Abstract: A low-dropout regulator is provided. The low-dropout regulator includes a p-type depletion transistor as a pass device. The low-dropout regulator further includes switch circuitry and a charge pump that provides, at its output, a voltage greater than VDD. The source of the p-type depletion transistor is coupled to VDD. Under normal operating conditions, the bulk of the p-type depletion transistor is coupled to the source of the p-type depletion transistor. However, if the voltage at the gate of the p-type depletion transistor gets close to VDD, the switch circuitry causes the bulk of the p-type transistor to be coupled to the output of the charge pump instead.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: A power managing apparatus is utilized to control a first supply voltage, a second supply voltage, and a substrate voltage of a digital circuit. The power managing apparatus includes a voltage generating device, for generating a first reference voltage and a second reference voltage; and a voltage switching device, coupled to the voltage generating device, for adjusting the first supply voltage, the second supply voltage, and the substrate voltage. When the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to be the first supply voltage and the substrate voltage; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to be the first supply voltage, and outputs the second reference voltage to be the second supply voltage.

Abstract: A method for extending lifetime reliability of CMOS circuitry includes coupling a first switching device between a logic high supply rail/logic low supply rail, and coupling a virtual supply rail to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device is coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, wherein in a third mode of operation, the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail is equalized.

Abstract: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit.

Abstract: A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

Abstract: A method for extending lifetime reliability of CMOS circuitry includes configuring a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

Abstract: A sense amplifier flip flop including a differential input portion, a differential amplifying portion including a first inverter and a second inverter, and a bias voltage generating portion. The bias voltage generating portion is configured to generate body voltages for transistors of the first inverter and the second inverter so that an offset between electric currents flowing through the differential input portion can be adjusted.

Abstract: A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level.

Abstract: An N-type well region is formed in a P-type semiconductor substrate. In the N-type well region, a P-type well region is formed. The P-type well region is used as a back gate of a transistor. The back gate of the transistor is separated from other elements by the N-type well region. In the P-type well region, a pair of N+ type semiconductor regions as a source region and a drain region of the transistor is formed. On the surface of the semiconductor substrate, a gate electrode of the transistor is formed. A potential of one region among the above-described pair of N+ type semiconductor regions is inputted to a buffer circuit. The same potential as the potential of the N+ type semiconductor region to be outputted from the buffer circuit is supplied to the P-type well region via a switching element.

Abstract: A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device.

Abstract: A semiconductor device including a bias voltage generator formed from a junction field effect transistor (JFET). The JFET includes a control gate terminal and a first and a second source/drain terminal. The first and second source/drain terminals can form a first terminal of a p-n junction and the control gate terminal can form a second terminal of the p-n junction. The first terminal of the p-n junction can be provided with a first potential. The second terminal can be left essentially floating to provide a bias voltage. A bias receiving circuit can receive the bias voltage. The bias receiving circuit can be in close proximity on the semiconductor device to the bias voltage generator.

Abstract: A semiconductor integrated circuit according to the present invention comprises an MOS substrate having a substrate region (MOS) and a source region separated from each other, a dummy MOS circuit substrate-separated from the MOS circuit and having a substrate region (dummy) and a source region (dummy) separated from each other, a substrate voltage generating circuit for generating a substrate voltage to be applied to the substrate region (MOS) and the substrate region (dummy), and a comparing circuit for measuring a current generated in the dummy MOS substrate, wherein an area ratio between the substrate region (dummy) and the source region (dummy) is substantially equal to an area ratio between the substrate region (MOS) and the source region (MOS).

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A plurality of LEDs is driven in parallel, in at least two modes. In a first mode, the LEDs are driven with a first voltage. In subsequent modes, the LEDs are driven with successively higher voltages. The forward voltage drop for each LED is monitored, and the driver switches from the first mode to successive modes based on the largest of the LED forward voltage drops. The current through each LED is controlled by directing a reference current through a first digitally controlled variable resistance circuit, and directing the LED current through a second digitally controlled variable resistance circuit having substantially a known ratio to the first variable resistance circuit and connected in series with the LED. A digital count is altered based on a comparison of the first and second currents, and the first and second variable resistance circuits are simultaneously altered based on the digital count.

Abstract: A method and apparatus compensate for process variations in the fabrication of semiconductor devices. A semiconductor device includes a control circuit that measures a performance parameter of the device, and in response thereto selectively biases one or more well regions of the device to compensate for process variations. For some embodiments, if measurement of the performance parameter indicates that the device does not fall within a specified range of operating parameters, the control circuit biases selected well regions to sufficiently alter the operating characteristics of transistors formed therein so that the device falls within the specified range of operating parameters.

Abstract: An embodiment of a bias switching circuit may include a first transfer switch that transmits a bias voltage to a first output node in response to a first switching signal, a second transfer switch that transmits a first power voltage to the first output node in response to a second switching signal, a third transfer switch that transmits the bias voltage to a second output node in response to the second switching signal, a fourth transfer switch that transmits the first power voltage to the second output node in response to the first switching signal. The circuit may further include a first transistor that transmits a second power voltage to the first output node in response to a third switching signal, and a second transistor that transmits the second power voltage to the second output node in response to a fourth switching signal.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A pseudo differential circuit is a circuit system taking the advantages of both a CMOS circuit and a differential circuit. However, when process variability and the like are taken into account, a cross point of positive and negative outputs is not constant, thereby increasing a variation in duty of an output waveform. A semiconductor circuit according to the present invention includes: a first transistor being of a first conductivity type, coupled between a first power supply and an output terminal, and applied with an input signal; a second transistor being of a second conductivity type and coupled between a second power supply and the output terminal; a third transistor being of the second conductivity type and coupled between the first power supply and the output terminal; and a fourth transistor being of the first conductivity type and coupled between the second power supply and the output terminal.

Abstract: A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the semiconductor integrated circuit device further comprising a first transistor of a second conductivity type and a second transistor of the second conductivity type, the transistors being connected in series between the second power supply line and a second substrate well provided on the semiconductor substrate.

Abstract: A high voltage generation circuit includes a pump clock generation unit configured to generate a pump clock signal in response to a pumping enable signal, a charge pump configured to generate a high voltage on an output in response to the pump clock signal, and a switching unit to selectively couple the output of the charge pump to an output node in response to the pumping enable signal.

Abstract: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A charge pump circuit employs an oscillator powered by a variable positive supply voltage, storage and switching circuitry controlled by an oscillator signal from the oscillator, and a regulator that maintains a negative supply voltage generated by the storage and switching circuitry at a target value through control of the variable positive supply voltage. The charge pump can be used in a power stage employing normally on switching transistors (such as silicon carbide junction FETs or SiC JFETs) that require a negative voltage to be turned completely off. Such power stages are in turn useful in applications including military aerospace applications having harsh electromagnetic interference (EMI) conditions, where they may be controlled by optical control signals conveyed by optical fibers from a more benign operating environment within the body of an aircraft.

Abstract: A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Abstract: With an ultrasound pulser suitable for application to a medical ultrasound system, and so forth, a high voltage power supply of a transducer drive circuitry, on both high potential and low potential sides, is rendered variable in a range of 0 V on the order of ±200 V, thereby implementing a semiconductor integrated circuit wherein a plurality of the ultrasound pulsers corresponding to a plurality of channels, respectively, are integrally formed on a small area.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: Disclosed is a semiconductor silicon wafer having an electric power supply affixed to the backside of the wafer. By fabricating the electric power supply onto the backside of the wafer that has been left unused, the semiconductor chip can have a self-supplied power, realizing the self-powered semiconductor chip with an increased efficiency. Further, since the electric power supply is installed on the wafer, not the semiconductor chip, the fabrication procedure becomes very simple, and the battery can be mounted on any type of chip.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: A new approach for managing turn-on of power islands uses a precharge phase to begin the process of bringing up the island's internal supply voltage, while minimizing transients and associated power-control-logic instability.

Abstract: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit.