Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

Abstract: The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch transistor has a first terminal coupled to a first supply voltage (102), a second terminal coupled to an internal voltage rail (108), a gate coupled to an activation signal source (110), and a body coupled to a bias signal source (114). A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source when that transistor is shut off. A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on.

Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

Abstract: A booster circuit includes a first booster unit having a first output terminal from which a boosted voltage is output. The first output terminal is connected to an external output terminal. A second booster unit has a second output terminal from which a boosted voltage is output. The second output terminal is connected to the external output terminal. A control circuit outputs a first control signal used to control the operation of the first booster unit and a second control signal used to control the operation of the second booster unit. Further, the control circuit controls the first and second control signals so that a transition between the operative state and the non-operative state of the first booster unit and a transition between the operative state and the non-operative state of the second booster unit will be made at different timings according to output voltage of the external output terminal.

Abstract: A pump circuit includes first and second transistors connected between an input terminal and an output terminal, and a capacitor which is connected at its one end to the connection node of the first and second transistors. The pump circuit is responsive to control signals applied to the gate electrodes of the first and second transistors and another end of the capacitor to output from the output terminal a second voltage which is approximately equal to a first voltage applied to the input terminal. A back-gate voltage generating circuit which produces a third voltage which is less than the lower one of the first and second voltages. The third voltage is applied to at least the back gate of the second transistor which outputs the second voltage.

Abstract: A system and method for providing a voltage. The system includes a first transistor with a first gate, a first terminal, and a second terminal, a second transistor with a second gate, a third terminal, and a fourth terminal, and a third transistor with a third gate, a fifth terminal, and a sixth terminal. Additionally, the system includes a fourth transistor with a fourth gate, a seventh terminal, and an eighth terminal, a fifth transistor with a fifth gate, a ninth terminal, and a tenth terminal, and a sixth transistor with a sixth gate, an eleventh terminal, and a twelfth terminal. The tenth terminal and the eleventh terminal are directly connected at a third node, which is directly connected to a first substrate for the third transistor, a second substrate for the fourth transistor, a third substrate for the fifth transistor, and a fourth substrate for the sixth transistor.

Abstract: To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.

Abstract: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may be unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.

Abstract: A charge pump circuit includes a test mode control unit for generating a plurality of control signals according to a test mode enable signal and an input signal and fixing one of the plurality of the control signals depending upon whether a fuse has been cut or not, a ring oscillator for outputting an output frequency of which varies according to an output of the test mode control unit, and a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator.

Abstract: An ORing element for use in a power supply and/or power system. The ORing element may include a field effect transistor (FET), a first bi-polar transistor and a second bi-polar transistor. The FET may be electrically connected between an input and an output. The first bipolar transistor may have an emitter electrically connected to the source of the FET and a collector electrically connected to a gate of the FET. The second bi-polar transistor may be diode connected, with its emitter electrically connected to its base. The emitter of the second bi-polar transistor may also be electrically connected to the base of the first bi-polar transistor. The collector of the second bi-polar transistor may be electrically connected to the drain of the FET.

Abstract: The present invention relates to a power managing apparatus utilized for controlling a first supply voltage, a second supply voltage, and a substrate voltage of a digital circuit. The power managing apparatus includes a voltage generating device, for generating a first reference voltage and a second reference voltage; and a voltage switching device, coupled to the voltage generating device, for adjusting the first supply voltage, the second supply voltage, and the substrate voltage. When the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to the first supply voltage and the substrate voltage; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to the first supply voltage, and outputs the second reference voltage to the second supply voltage.

Abstract: A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality of LABs. Sleep control logic of the PLD issues a sleep control signal for placing at least a portion of the plurality of LABs in a sleep mode. Bias control logic of the PLD is in communication with the sleep control logic. The bias control logic is triggered by the sleep control signal to issue a first bias control signal and a second bias control signal. The first and second bias control signals are transmitted to corresponding transistors of the LABS. The first and second bias control signals apply a reverse bias to corresponding transistor wells to increase threshold voltages for the respective transistors.

Abstract: Circuits, methods, and apparatus that provide output drivers that consume relatively little integrated circuit area and provide fast output switching. An exemplary embodiment provides an output driver including pull-up and pull-down devices, each device driven by a pre-driver stage. The pre-driver for the pull-down device is supplied from an auxiliary power supply, which has a higher voltage than the supply seen by the pull-up device. The pre-driver for the pull-down is biased by a voltage that tracks the higher of the auxiliary and output supplies. In some embodiments, the output driver may be part of an input/output cell. In that case, the well for the pull-up device is biased by a voltage that tracks the highest of the output supply and input received voltage, while the pull-up predriver circuit bias is the higher between the auxiliary and output supplies and the input received voltage.

Abstract: The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.

Abstract: A reference voltage generating circuit for outputting a reference voltage having a level varying depending on the operation mode of a semiconductor device is disclosed.

Abstract: A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

Abstract: An integrated circuit apparatus according to one embodiment of the invention has an NMOS transistor and a source voltage controller which controls the source voltage of the NMOS transistor according to operation mode. The source voltage controller changes the source voltage according to temperature. Since this integrated circuit apparatus changes the source voltage of the MOSFET based on temperature, it is controlled to have desired leakage current regardless of temperature change.

Abstract: A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.

Abstract: A voltage generating circuit that drives multiple output terminals in alternating positive and negative cycles has two resistor ladders, one resistor ladder generating voltages for the positive cycles, the other resistor ladder generating voltages for the negative cycles. Single-ended amplifiers are connected directly to the resistor ladders, and a switching circuit connects each output terminal to a selectable one of the amplifiers. The output terminals may be precharged to opposite potentials at the beginning of positive and negative cycles, and the resistor ladders may include switching elements that initially set all generated voltages to these potentials so that the amplifiers start each cycle with equal input and output levels, reducing overshoot and undershoot. This voltage generating circuit saves space and power in driving, for example, a display panel in a mobile telephone.

Abstract: An integrated circuit (IC) device includes a first voltage supply for powering first circuitry within the device, a second voltage supply for powering second circuitry within the device, a suspend circuit having an output to generate a power-down signal, and a voltage regulator circuit coupled to a power node. The voltage regulator circuit includes a first transistor coupled between the first voltage supply and the power node and having a gate responsive to a regulation signal, a second transistor coupled between the second voltage supply and the power node and having a gate responsive to the power-down signal, and a well bias circuit having an input coupled to receive the power-down signal, a first output coupled to a well region of the first transistor, and a second output coupled to a well region of the second transistor.

Abstract: Systems and methods for integrated circuits comprising multiple body bias domains. In accordance with a first embodiment of the present invention, an integrated circuit is constructed comprising active semiconductor devices in first and second body bias domains. A first body biasing voltage is coupled to the first body bias domain, and a second body biasing voltage is coupled to the second body bias domain. The first and the second body biasing voltages are adjusted to achieve a desirable relative performance between the active semiconductor devices in the first and the second body bias domains.

Abstract: The leakage current output by a MOS transistor is minimized by varying a back bias voltage across a range of voltages, and detecting the back bias voltage within the range that minimizes the leakage current output by the MOS transistor. The detected back bias voltage is then applied to the MOS transistor.

Abstract: This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.

Abstract: Method and apparatus for adjusting an impedance of a substrate of a Metal-Oxide-Semiconductor (MOS) transistor by providing a bias voltage and connecting a frequency-selective circuit between the substrate and the bias voltage. The frequency-selective circuit is also provided with at least one reactive element, such as an inductive element or a capacitive element, to obtain a certain frequency-response of the frequency-selective circuit and thus adjusts the substrate impedance of the MOS transistor. The method and apparatus are compatible with standard CMOS technology and applicable to RF switches, including T/R switches for processing high-frequency analog signals.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

Abstract: A high voltage switching circuit of a NAND type flash memory device that includes a clock level shifter for increasing an amplitude of a clock signal, a pass voltage generator for outputting a pass voltage by pumping a power source voltage in response to a clock signal with an increased amplitude, and a high voltage pass transistor for transferring a high voltage according to the pass voltage.

Abstract: A method includes controlling the connection of a charge pump output to a load capacitor as a function of activation control signals to an oscillator controlling the charge pump. A charge pump system includes a charge pump, an oscillator, a switching element and an enable signal generator. The switching element connects and disconnects the charge pump from a load capacitor. The enable signal generator is connected to the oscillator and to the switching element and enables and disables the oscillator and the switching element as a function of the output of the charge pump.

Abstract: Biasing a transistor connected to a voltage converter, the method includes: (i) providing at least one bias voltage to at least one well of at least one transistor of a test circuitry; (ii) measuring at least one parameter of a test circuitry representative of at least one characteristic of the transistor and of at least one characteristic of the voltage converter; (iii) altering at least one bias voltage and repeating the stages of providing and measuring until a predefined control criteria is fulfilled; and (iv) providing a voltage bias to a well of the transistor in response to the measurements.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: A semiconductor IC capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing stable operation.

Abstract: The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

Abstract: A power supply voltage switch circuit for selecting a power supply voltage of an integrated circuit according to a first control signal. The power supply voltage switch circuit contains a high voltage selecting module for generating an output voltage according to the higher of a first and a second voltages; a level shifting module electrically connected to the high voltage selecting module to receive the output voltage as power supply, for performing level shifting to a first control signal according to the output voltage; and a selecting switch module electrically connected to the level shifting module for selectively outputting the first or the second voltage as the power supply voltage of the integrated circuit according to the level-shifted first control signal.

Abstract: A plurality of MOS type circuits is provided, and are connected in a multistage manner. A first transistor is inserted between a power source voltage VDD and a power supply node of each of MOS type circuits at an odd numbered stage. A second transistor is inserted between the power source voltage VDD and a power supply node of each of MOS type circuits at an even numbered stage. When the plurality of MOS type circuits are established in a standby state, a control circuit first controls to make a second transistor conductive, and then make a first transistor conductive when the plurality of MOS type circuits, each of which is established in a standby state, are recovered from the standby state to an active state.

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Abstract: A system and method is provided for providing power managed common mode logic (CML) transmitters for use with main and auxiliary power sources. Power switch circuitry comprising two PMOS transistors switches the CML transmitter output circuit between a main power source node (VDD) and an auxiliary power source node (TXRAIL). A bias circuit biases the two PMOS transistors to place the main power source voltage on the auxiliary power source node (TXRAIL) when the value of the main power source voltage is nonzero. The bias circuit also biases the two PMOS transistors to remain off when the value of the main power source voltage on the main power source node (VDD) is zero.

Abstract: To restrain variations in the power supply potential caused among a plurality of integrated circuits as well as the voltage drop of the power supply potential that has reached each block. A semiconductor integrated circuit device is provided with integrated circuits as blocks 2–4, power supply wires 11–13 for supplying power supply potential VDD or ground potential GND from feeder terminals 5–10 to the blocks 2–4, a switch circuit 14 for connecting the power supply wire 11 and the power supply wire 12, and a switch circuit 15 for connecting the power supply wire 11 and the power supply wire 13. When the switch circuit 15 is turned on, for example, the power supply wire 11 and the power supply wire 13 of the block 2 and the block 4 are connected whereby to supply the power supply potential from the two power supply wires, so that power supply potential variation is restrained.

Abstract: An oscillating buffer is coupled to an oscillating source, in parallel, for providing a predetermined waveform at a predetermined frequency for a core circuit with a plurality of MOS transistors operating at a core voltage. In one embodiment, the oscillating buffer includes an inverter, coupled between the core voltage and ground, for amplifying an input signal from the oscillating source. The inverter has one or more MOS transistors with gate oxides of a thickness substantially the same as that of the MOS transistors of the core circuit.

Abstract: A control circuit with a high voltage sense device. In one embodiment, an apparatus includes a first transistor disposed in a substrate having a first, a second and a third terminal. The first terminal of the first transistor is to be coupled to an external voltage and the second and third terminals of the first transistor are to be coupled to a ground reference voltage. The apparatus also includes a second transistor disposed in the substrate having a first, a second and a tap terminal. The first terminal of the second transistor is coupled to the first terminal of the first transistor, the second terminal of the second transistor is coupled to the second and third terminals of the first transistor and the tap terminal of the second transistor is coupled to provide a tap voltage that is substantially proportional to a voltage between the first and second terminals of the second transistor up to a pinch-off voltage of the second transistor.

Abstract: A power-on bias circuit including a first inverter having an input terminal and an output terminal, the input terminal functions as an input terminal of the power-up bias circuit; a second inverter having an input terminal and an output terminal, the output terminal of the second inverter functions as the output terminal for the power-on bias circuit; and a Schmitt Trigger circuit having an input terminal and an output terminal, wherein the input terminal of the Schmitt Trigger circuit is connected to the output terminal of the first inverter, the output terminal of the Schmitt Trigger circuit is connected to the input terminal of the second inverter, the first inverter, the second inverter and the Schmitt Trigger circuit are each in electrical communication with a voltage input terminal and ground.

Abstract: Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch comprises: if a voltage of a first power supply rises before a voltage of a second power supply, initially biasing the backgate with a voltage based on the first power supply; and if the voltage of the first power supply rises after the voltage of the second power supply, biasing the backgate with a voltage based on the second power supply.

Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: A memory includes a power-up circuit configured to increase a first voltage to a first value with a second voltage tied to ground, reduce the first voltage from the first value to a second value with the second voltage floating to reduce the second voltage through a parasitic coupling capacitance, and pump the second voltage to reduce the second voltage to a third value with the first voltage less than the second value.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: In a ring oscillator constituting an oscillating circuit, resistor circuits are used as delay circuits to be connected to respective inverters. That is, the inverters and the resistors are connected in series so that the resistor is provided between the adjacent inverters. With the arrangement, it is possible to provide an oscillating circuit which is less dependent on any of power supply voltages, temperatures, and manufacturing variations, while maintaining a characteristic in which the oscillating frequency decreases as an output voltage of a booster circuit increases.