Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Abstract: In a power supply circuit having input and output terminals, an error amplifier has first and second paths independent of each other to output a control voltage, a first MOS transistor is interposed between the input terminal and an intermediate node, and a step-up section steps up a voltage supplied from the intermediate node and outputs the stepped-up voltage to the output terminal. The step-up section includes a capacitor, a second MOS transistor, a third MOS transistor, and a drive circuit. The first end of the capacitor is connected to the intermediate node. The second MOS transistor is interposed between the input terminal and a second end of the capacitor. The third MOS transistor is interposed between the second end of the capacitor and a ground. The drive circuit drives the second and third MOS transistors in a complementary manner based on a clock signal.

Abstract: An oscillator supplies a clock signal having a frequency determined in part according to a received current. A transmit side charge pump is coupled to the clock signal and boosts a voltage supplied to the charge pump to generate a boosted voltage. A driver circuit drives a transmit signal having a frequency based on the clock signal and a voltage based on the boosted voltage to a capacitive isolation communication path. A receive side charge pump is coupled to the isolation capacitors of the isolation communication path and boosts a voltage of the received signal on the receive side of the isolation communication path and supplies a gate signal with the boosted voltage to a gate of at least one transistor.

Abstract: A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

Abstract: A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.

Abstract: A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels.

Abstract: Multiple measurements may be obtained via a single pin of an integrated circuit (IC) to set multiple control parameters of a light emitting diode (LED) controller within the IC. For example, a first input signal may be applied from the IC to two or more components via a single IC pin. A first output signal may be obtained from the two or more components via the single IC pin. A second input signal may be applied from the IC to the two or more components via the single IC pin, and a second output signal may be obtained from the two or more components via the single IC pin. A first parameter and a second parameter of the two or more components may be calculated based, at least in part, on the first output signal and the second output signal obtained via the single IC pin.

Abstract: Charge pump systems and methods for the operation thereof can be configured for delivering charge to a primary circuit node. A sequential charging pattern of at least a subset of a series-connected plurality of charge-pump stages connected between a supply voltage node and the primary circuit node can be selectively initiated. For example, the sequential charging pattern can be initiated one time for every N cycles of a given clock signal, wherein N is a selectively adjustable integer value greater than or equal to 1.

Abstract: A demodulator for near field communication may include: a scale down circuit configured to receive first and second modulated signals from first and second power electrodes, and configured to provide a scale down signal to a first node by scaling down magnitudes of the first and second modulated signals; a current source coupled between the first node and a ground voltage, and configured to generate a constant current flowing from the first node to the ground voltage; a charge store circuit coupled between the first node and ground voltage, and configured to perform charge and discharge operations alternately, based on the scale down signal and constant current, to output an envelope signal, which corresponds to an envelope of the scale down signal; and/or an edge detector configured to generate input data, which correspond to the first and second modulated signals, based on a transition of the envelope signal.

Abstract: A charge pump circuit for generating a negative voltage has a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop has a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

Abstract: A method of driving a display panel includes providing a boosting voltage line on the display panel with a boosting voltage, compensating the boosting voltage based on a feedback boosting voltage received from the display panel, and providing the boosting voltage line on the display panel with the compensated boosting voltage. The display panel includes a first sub pixel. The first sub pixel includes a first switching element and a first boosting switching element, the first switching element is connected to a first liquid crystal (LC) capacitor, a gate line, an m-th data line and a first electrode of the first LC capacitor, and the first boosting switching element is connected to the boosted voltage line, and ‘m’ is a natural number.

Abstract: An apparatus for converting voltage includes terminals coupled to external circuits at corresponding voltages and a switching network having driving circuits and semiconductor switches that interconnect capacitors in successive states to one another and to the terminals. The switches interconnect some capacitors to one another through a series of switches when an activation pattern causes them to be activated. Each driving circuit has power connections, a control input, and a drive output coupled to and controlling at least one switch. A drive output of one of them couples to and drives each switch. Some of the driving circuits are powered via corresponding power connections from at least one of the capacitors such that a voltage across the corresponding power connections is less than a highest of the corresponding voltages. The terminals and the switching network are constituents of a switched capacitor converter.

Abstract: The present disclosure provides a method of reusing electrical energy for a charge pump. The method comprises operating in a reusing phase after a boosting phase is completed; retrieving energy of parasitic capacitance in the reusing phase; and reusing the energy of the parasitic capacitance for an internal circuit.

Abstract: A negative reference voltage generating circuit includes a switched capacitor circuit having a capacitor connected to a first and a second nodes, a first and a second switches connected to the first node, a third and a fourth switches connected to the second node; and a control circuit, generating a first to a fourth control signals to control the first to the fourth switches respectively. The control circuit applies a preset positive reference voltage to the first node to charge the capacitor during a first period, and outputs a negative voltage from the second node based on the voltage charged to the capacitor during a second period different from the first period. By repeating the first and the second periods, an inverting negative voltage of the positive reference voltage that is outputted from the second node is used as a negative reference voltage.

Abstract: A charge pump circuit for generating a negative voltage has: a clock generator arranged to output at least one clock signal; a switched capacitor voltage inverter circuit including capacitive elements wherein the switched capacitor voltage inverter circuit receives the at least one clock signal and generates a negative voltage therefrom. The charge pump circuit further has a regulation control loop providing a feedback path from an output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, and an output arranged to output a generated negative voltage. The feedback path has an operational amplifier configured to generate a maximum charging supply voltage from a fed back level-shifted negative voltage and apply the maximum charging supply voltage to the input supply of the switched capacitor voltage inverter to charge at least one of the capacitive elements during a loop start up.

Abstract: A pumping circuit includes a charge pump configured to generate a pumping voltage based on a first voltage in response to an oscillation signal, and an oscillator configured to provide a period-controlled oscillation signal based on the first voltage and a second voltage.

Abstract: A power-up circuit of a semiconductor apparatus includes a detection block configured to detect a first target level of an external voltage and activate a power-up signal; and a bias block configured to divide the external voltage according to a division ratio that is variable in response to the power-up signal, and output a bias voltage.

Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.

Abstract: A charge pump system includes a plurality of pump units, a control circuit, and a detection circuit. The plurality of pump units are used for generating a pump output voltage. The control circuit is coupled to the plurality of pump units and is used for controlling each pump unit of the plurality of pump units. The detection circuit is coupled to the control circuit and the plurality of pump units and is used for detecting the pump output voltage. When the pump output voltage is greater than a predetermined value, the detection circuit generates and latches a control signal to enable the control circuit. After the control circuit is enabled, when the pump output voltage is detected to be smaller than the predetermined value, the detection circuit generates a first pump enable signal to the control circuit for enabling a first pump unit of the plurality of pump units.

Abstract: A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level.

Abstract: A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage. During the normal working period, the pump capacitor and the output capacitor are controlled by the proper switch that is configured into the connection relationship that the charge pump can normally work in order to make the charge pump work normally. As a result of the pre-charge operation, embodiments disclosed herein can reduce the time of the output capacitor for reaching a steady state value.

Abstract: A silicon-on-insulator (SOI) based positive/negative voltage generation circuit includes: an inverter including an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor.

Abstract: A charge pump cell, comprising: an input node; an output node; Q channels, where Q is an integer greater than one, and where at least two of the channels comprise: a capacitor; a unidirectional current flow device; an output diode; and a channel drive signal node; and wherein a first current flow node of the unidirectional current flow device is connected to a first node of the capacitor at a channel node, a second node of the capacitor is connected to the channel drive signal node, a second current flow node of the unidirectional current flow device is connected to the input node, and the output diode is connected between the channel node and the output node.

Abstract: A semiconductor device includes an external voltage detection unit suitable for detecting a voltage level of an external voltage to output an external voltage detection signal based on the detected result, a reference voltage generation unit suitable for generating a reference voltage based on the external voltage, an internal voltage generation unit enabled in response to the external voltage detection signal, suitable for selectively generating a voltage corresponding to the reference voltage as an internal voltage, and an internal voltage control unit suitable for selectively providing a voltage having a target level corresponding to the internal voltage as the internal voltage in response to the external voltage detection signal.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A signal balance system, a light control system, and a signal balance method thereof are disclosed. The signal balance system includes a signal sensing module and a processing module. The signal sensing module is used for detecting an external signal source to generate a sensing signal. The processing module is used for generating an adjusting signal based on the sensing signal, wherein the processing module determines whether the sensing signal exceeds a first threshold; if yes, the processing module decreases the sensing signal to generate the adjusting signal so as to control a controlled device.

Abstract: Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include generating a clock signal in a particular die of a plurality of dies, counting pulses of the clock signal in a wrap-around counter in each die of the plurality of dies, and pausing an access operation for the particular die of the plurality of dies at a designated point until a value of the wrap-around counter matches an assigned counter value of the particular die.

Abstract: A DC-DC converter comprises a capacitor arrangement and a switching arrangement for controlling coupling of the capacitor arrangement to a converter input during a loading phase and to a converter output during a storing phase. The converter cycles between charge pumping stages and charge holding phases, giving rise to a converter switching frequency. A variable output load is controlled thereby to maintain a constant converter switching frequency.

Abstract: A method of controlling a charge pump circuit can include: (i) detecting a difference between an output voltage and an input voltage in real time; (ii) generating an error amplifying signal by comparing the difference between the output voltage and the input voltage against a predetermined difference; and (iii) generating a control voltage signal for controlling the charge pump circuit according to the error amplifying signal, where a frequency of the control voltage signal positively changes along with the difference between the output voltage and said input voltage when the difference between the output voltage and the input voltage is greater than the predetermined difference.

Abstract: Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution.

Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

Abstract: The present invention generally relates to a DVC having a charge-pump coupled to a MEMS device. The charge-pump is designed to control the output voltage delivered to the electrodes, such as the pull-in electrode or the pull-off electrode, that move the switching element within the MEMS device between locations spaced far from and disposed closely to the RF electrode.

Abstract: Efficiency of a charge pump circuit is increased. The charge pump circuit includes serially connected fundamental circuits each including a diode-connected transistor and a capacitor. At least one transistor is provided with a back gate, and the back gate is connected to any node in the charge pump circuit. For example, the charge pump circuit is of a step-up type; in which case, if the transistor is an n-channel transistor, a back gate of the transistor in the last stage is connected to an output node of the charge pump circuit. Back gates of the transistors in the other stages are connected to an input node of the charge pump circuit. In this way, the voltage holding capability of the fundamental circuit in the last stage is increased, and the conversion efficiency can be increased because an increase in the threshold of the transistors in the other stages is prevented.

Abstract: A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a peak-to-peak amplitude that is variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.

Abstract: A switching direct current (DC)-to-DC converter includes a charge pump circuit with a flying capacitor (104) and a switching circuit (106). The switching circuit (106) has an ON resistance (Ron) and is configured and arranged to boost an input voltage (Vin) by operating in each of a charging mode (loading) during which charge is provided from the flying capacitor (104) to an output voltage (Vout) and a discharging mode (storing) during which charge is not provided from the flying capacitor (104) to the output voltage (Vout). A determination circuit (102) is configured and arranged to determine a ratio between a discharge rate (308) and a charge rate (310). The discharge rate (308) and the charge rate (310) both correspond to a rate of change for the output voltage of the switching DC-to-DC converter. An ON resistance circuit (102) module is configured and arranged to adjust the ON resistance (Ron) of the charging mode (loading) and to change the determined ratio to a target ratio.

Abstract: A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell.

Abstract: A charge pump includes first through fifth transistors and a capacitor. The first through fourth transistors are connected in cascade and form a control circuit. The second transistor has a gate connected to its drain and hence, acts as a diode. The charge pump receives a clock signal and a supply voltage and generates an output voltage where the level of the output voltage is controlled by varying a size of the second transistor.

Abstract: A voltage converting device includes first to third voltage converters, each including a capacitor, a pair of charge switches for charging the capacitor, a pair of first output switches for outputting a first output voltage through the capacitor, and a pair of second output switches for outputting a second output voltage through the capacitor. Via timing control of the switches, outputs of the first and second output voltages are substantially continuous and are prevented from floating.

Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.

Abstract: Charge pump system and memory are provided. The system includes: a first enabling control unit, adapted to delay at least one start-up signal of the system to obtain and output an oscillating enabling signal after receiving the at least one start-up signal and a voltage boosting enabling signal; a second enabling control unit, adapted to delay the oscillating enabling signal to obtain and output a charge pump enabling signal after receiving the oscillating enabling signal and the voltage boosting enabling signal; a clock oscillating unit, adapted to generate a clock signal after receiving the oscillating enabling signal; and at least one charge pump cell, adapted to output a boosting voltage after receiving the charge pump enabling signal and the clock signal, obtain the voltage boosting enabling signal based on the boosting voltage, and output the voltage boosting enabling signal. Power consumption of the system in a start-up process is reduced.

Abstract: A load-sensing voltage charge pump system may include a plurality of reference voltage inputs including a target voltage input. The system may also include a plurality of voltage charge pump segments equal in number to the plurality of reference voltage inputs. A voltage charge pump segment may include: a regulator that receives a reference voltage, and a voltage charge pump that outputs a current to a load at a sensed voltage. The regulator may enable each of the voltage charge pump segments, when the sensed voltage is less than or equal to the one of the reference voltages and the target voltage. The system may include a boosted line connected in parallel to an output of each of the voltage charge pump segments. The boosted line may receive the current at the sensed voltage from each of the voltage charge pump segments that is enabled.

Abstract: Voltage generation circuits are provided. The voltage generation circuit includes a reference voltage generator suitable for generating a reference voltage signal having a constant level without a correspondence to a temperature variation. A comparator suitable for comparing a first drivability controlled by a level of the reference voltage signal with a second drivability controlled by a level of a comparison voltage signal to generate a comparison signal. A voltage controller may be configured to generate the comparison voltage signal whose level continuously increases until the comparison signal is enabled.

Abstract: A control circuit and method for an audio amplifier detect a signal for driving a speaker to control the switching frequency and the operation mode of a charge pump in the audio amplifier, to improve power efficiency of the audio amplifier. Preferably, a digital interface is further used to test the magnitude of the output signal of the audio amplifier, to reduce the costs of analog test. The charge pump has fewer switches and thus saves costs and die area of an integrated circuit. The control method needs only two phase control for the charge pump to generate a positive voltage and a negative voltage, and thus simplifies the operation of the circuit.

Abstract: The present invention provides a power supply comprising a driver and a charge pump. The driver is configured to provide a driving signal to a load. The charge pump comprises a first capacitor coupled to the load in parallel, at least one flying capacitor, a second capacitor and a switch array comprising a plurality of switches. The switch array is coupled to the first capacitor, the second capacitor and the at least one flying capacitor. The switch array receives the voltage across the first capacitor and controls the charge and discharge of the at least one flying capacitor, so as to make the voltage across the second capacitor be larger than the voltage across the first capacitor.

Abstract: A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line voltages to be performed with a stable word line voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner.

Abstract: An electrical circuit for providing electrical power for use in powering electronic devices is described herein. The electrical circuit includes a primary power circuit and a secondary power circuit. The primary power circuit receives an alternating current (AC) input power signal from an electrical power source and generates an intermediate direct current (DC) power signal. The intermediate DC power signal is generated at a first voltage level that is less than a voltage level of the AC input power signal. The secondary power circuit receives the intermediate DC power signal from the primary power circuit and delivers an output DC power signal to an electronic device. The output DC power signal is delivered at an output voltage level that is less than the first voltage level of the intermediate DC power signal.

Abstract: A charge pump circuit includes a delay circuit, a transistor, and a capacitor. The charge pump receives an input signal and outputs an output signal. The delay circuit receives a first signal based on the input signal and outputs a first delayed signal. The transistor includes a gate, a first channel node, and a second channel node. The first channel node receives the first signal. The second channel node is connected to the output and to a first plate of the capacitor. A second plate of the capacitor receives a second signal based on the first delayed signal. The charge pump circuit is adapted to operate such that the voltage range of the output signal is greater than the voltage range of the input signal.

Abstract: The invention discloses a green power converter which omits the pulse width modulation (PWM) technique in the traditional power converter, does not have high-frequency power device, does not generate EMI interference, simultaneously adopts the symmetry basic primitive (SBP) technique, the amplitude high modulate (AHM) technique and the dynamic rectification (DR) technique, and only needs to perform traditional power conversion on a small part of the input power so as to acquire the whole output power, namely that a large part of the output power neither need traditional power conversion nor need to pass through a magnetic core transformer. The input AC voltage neither needs to be rectified and filtered nor has large inductance and large capacitance, thus the power factor is 1, and the total harmonic distortion (THD) is 0. A transformer secondary side adopts dynamic rectification, can acquire a DC circuit, and can also acquire an AC voltage.

Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Abstract: A charge pump circuit includes a first plurality of capacitors, and a first precharge circuit. The first plurality of capacitors are connected in parallel to each other. The first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied. The first precharge circuit precharges a predetermined number of capacitors in the first plurality of capacitors at the power voltage. The predetermined number is greater than one.