Abstract: A memory controller of inventive concepts may include an active regulator configured to operate in an active mode and be inactive in a sleep mode, an active logic configured to receive a drive voltage, a power gating switch configured to connect the active regulator to the active logic after a transient state of the active mode, the transient state being an initial time period of the active mode, and a charging circuit configured to charge the active logic during the transient state.

Abstract: A voltage conversion circuit includes: a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first and second converted signals in a matching period of time in which voltages of the first converted signal and the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time.

Abstract: A pumping circuit includes a cross-coupled charge pump circuit including first and second capacitors configured to pump an input voltage in response to a first clock signal and to an inverted first clock signal and a plurality of transistors configured to one of transfer the input voltage to the first and second capacitors and to transfer a pumping voltage to an output node, and a switching voltage supply circuit configured to supply switching voltages to gates of the plurality of transistors to enable the transfer of the input voltage and the pumping voltage.

Abstract: There is provided a reference voltage generating apparatus including: a reference voltage source, a voltage retaining circuit, a switch and a controller. The reference voltage source generates a reference voltage. The voltage retaining circuit includes a first element circuit and a second element circuit, and the voltage retaining circuit outputs a voltage of a connection node between a first terminal of the first element circuit and a second terminal of the second element circuit. The switch is connected between the connection node and the reference voltage source. The controller controls the reference voltage source and the switch. The first element circuit includes at least a resistance component and the first element circuit is supplied with a first voltage at a third terminal and the second element circuit includes a resistance component and a capacity component and the second element circuit is supplied with a second voltage at a fourth terminal.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: Embodiments relate to a direct voltage sensor and a charge pump system for a computer system. A charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Abstract: The invention relates to a charge pump circuit comprising an input node for inputting a voltage to be boosted; an output node for outputting a boosted voltage; a plurality of pumping stages connected in series between the input node and the output node, each pump stage comprising at least one charge transfer transistor, wherein the at least one charge transfer transistor is a double-gate transistor comprising a first gate for turning the transistor on or off according to a first control signal applied to the first gate and a second gate for modifying the threshold voltage of the transistor according to a second control signal applied to the second gate, wherein the first and second control signals have the same phase.

Abstract: The final cell or cells in a cascade or ladder of voltage elevator cells may be exposed to significant overvoltages from electrostatic discharge originating in off-chip loads. In such conditions, the final cell or cells may be damaged or destroyed by such overvoltages. Protective circuitry may be added to one or more of the final voltage elevator cells to reduce or eliminate such damage or destruction by distributing the overvoltage among two or more cells. Such protective circuitry may include a capacitor coupled in parallel with the input and output node of one or more of the final voltage elevator cells. The protective circuitry may also include a resistor coupled in series between the final voltage elevator cell and the load.

Abstract: A charge pump regulator includes a charge pump circuit, a voltage divider, a mode determining circuit, a frequency divider, and a selecting circuit. The charge pump circuit receives an oscillation signal and generates an output signal. The voltage divider receives the output signal and generates a first and a second divided voltages. The mode determining circuit determines whether the charge pump regulator is in a pumping mode or a detecting mode, and issues a first control signal. When the mode determining circuit is in the pumping mode, a pumping enable signal is activated and the clock signal is converted into the oscillation signal by the selecting circuit. When the mode determining circuit is in the detecting mode, a detecting enable signal is activated and the frequency divider generates a detecting signal according to the first control signal.

Abstract: A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.

Abstract: Switched capacitor circuits and charge transfer methods include a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one buffer amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one buffer amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase.

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract: The invention is a radiation hardened charge-pump system and method of using polysilicon diodes and metal-to-metal capacitors in a standard CMOS process technology that provides boosted positive or negative voltages higher than power supply voltage levels, that reduces or eliminates field leakage, bipolar snap-back, SEL problems, and the SEGR problem. The charge-pump system is arranged as multiple parallel redundant pumps to harden the circuit so that if there is a single-event transient, or an unknown polysilicon-diode failure in a new technology, the remaining pumps will continue to operate. A diode placed at the end of each redundant pump section allows charge to be placed onto the high voltage node without removing charge due to failure of one of the sections. With the use of auxiliary circuits, such as a voltage doubler, this hardened charge pump can be used reliably at low power supply voltage levels.

Abstract: A spread-spectrum switching regulator for eliminating modulation ripple includes high gain amplifier that is responsive to reference voltage and feedback voltage of feedback loop to generate differential voltage, the feedback voltage being one of output voltage of the spread-spectrum switching regulator and a fraction of the output voltage; compensation circuit, coupled to the high gain amplifier, that maintains stability of the feedback loop to generate error level voltage in response to differential voltage; ramp generator that generates ramp waveform with slope adaptable to switching frequency to maintain duty cycle at constant value; pulse width modulator, coupled to compensation circuit and ramp generator, that compares error level voltage and ramp waveform to generate pulsed waveform; driver circuit, coupled to pulse width modulator, that drives the pulsed waveform to alternately switch a pair of transistors; and LC network, coupled to the pair of transistors, to average pulsed waveform to the output vo

Abstract: A semiconductor memory device includes a plurality of word lines each of which are connected to a plurality of memory cells, a row control unit suitable for sequentially activating and precharging a word line corresponding to a target address and a predetermined (N) number of adjacent word lines during a target activation mode, and a mode exit control unit suitable for counting the number of activation operations by the row control unit during the target activation mode to determine whether or not to exit from the target activation mode.

Abstract: A method and apparatus for current sensing and measurement employs two cascaded MOSFET current mirrors, wherein the mirrored current leaving the first current mirror is fed to the input of the second current mirror. Each current mirror contains a high current MOSFET and a low current MOSFET, connected source-to-source and gate-to-gate. The MOSFETs are matched so that drain-to-source current flowing in the high current MOSFET is proportional to the drain-to-source current flowing in the low current MOSFET. The ratio of high current to low current for each current mirror is M, where M is 100 or less. Voltage biasing networks are employed to maintain constant drain-to-source voltages for both MOSFETs in each current mirror.

Abstract: According to various embodiments, a circuit includes a charge pump and a feedback circuit. The charge pump includes a first input, a second input configured to receive an offset signal, and an output terminal configured to provide a charge pump signal based on the first and second inputs. The feedback circuit includes a first input coupled to the output of the charge pump, a second input configured to be coupled to a reference signal, an enable input configured to enable and disable the feedback circuit, and a feedback output coupled to the first input of the charge pump.

Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Abstract: Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory. The accuracy and level of resolution can be further increased through use of sigma delta noise shaping.

Abstract: An apparatus for controlling a charge pump includes a current sensor arranged to output a current sense signal that is linearly proportional to an output current of the charge pump, and an oscillator that provides a clock signal for the charge pump. The oscillator receives the current sense signal and uses it to vary an oscillation frequency of the clock signal. An amplitude of the clock signal also may be varied in response to the current sense signal.

Abstract: An object is to provide a photosensor utilizing an oxide semiconductor in which a refreshing operation is unnecessary, a semiconductor device provided with the photosensor, and a light measurement method utilizing the photosensor. It is found that a constant gate current can be obtained by applying a gate voltage in a pulsed manner to a transistor including a channel formed using an oxide semiconductor, and this is applied to a photosensor. Since a refreshing operation of the photosensor is unnecessary, it is possible to measure the illuminance of light with small power consumption through a high-speed and easy measurement procedure. A transistor utilizing an oxide semiconductor having a relatively high mobility, a small S value, and a small off-state current can form a photosensor; therefore, a multifunction semiconductor device can be obtained through a small number of steps.

Abstract: An embodiment of a digital-to-analog converter circuit includes a resistor network connected to an output node, a switch network having a first plurality of switches connecting the resistor network to a first circuit node and a second plurality of switches connecting the resistor network to a second circuit node, a voltage reference to supply a reference voltage to the first circuit node, and a current generator connected to the first circuit node and the second circuit node, to generate a compensation current, draw the compensation current from the first circuit node, and supply the compensation current to the second circuit node. The current generator can generate the compensation current as a function of a current or a voltage of a component of the voltage reference or as a function of an analog output voltage produced at the output node.

Abstract: The present document relates to charge pump voltage doublers for use in integrated circuits. A charge pump circuit configured to generate an output voltage Vout at an output of the circuit from an input voltage Vin at an input of the circuit is described. The circuit further comprises a boosting capacitor coupled at a first side to the output node of the first P-type switch and coupled at a second side to a capacitor control signal. Furthermore, the circuit comprises control circuitry configured to provide a capacitor control-signal-which alternates between a low level and a high level, and configured to generate first and second control signals based on the capacitor control signal for alternating the first and second P-type switches between on-states and off-states, respectively, such that electrical energy is transferred from the input to the output of the circuit using the boosting capacitor.

Abstract: Negative voltage generators that do not require level shifters or AC coupling capacitors are disclosed. In an exemplary design, a negative voltage generator includes first, second, third and fourth switches, a capacitor, and a control circuit. The first switch is coupled between an input node and a first node. The second switch is coupled between the first node and circuit ground. The third switch is coupled between a second node and circuit ground. The fourth switch is coupled between the second node and an output node. The input node receives a positive voltage, and the output node provides a negative voltage. The capacitor is coupled between the first and second nodes. The control circuit (e.g., an inverter) generates a control signal having positive and negative voltage levels for the third switch using a negative voltage level at the second node.

Abstract: A voltage regulator for use within an envelope tracking power supply system is described. The voltage regulator comprises a voltage regulation module. The voltage regulation module comprises at least one energy storage element, the at least one energy storage element comprising a first terminal operably coupled to a first node of the voltage regulation module, and a second terminal operably coupled to a second node of the voltage regulation module. The voltage regulation module further comprises an input arranged to receive a reference voltage supply signal, the input being selectively couplable to the first node and selectively couplable to the second node, an output selectively couplable to the first node and selectively couplable to the second node, and a ground plane selectively couplable to the second node.

Abstract: A capacitive touch panel controller has a memory and multiple driving signal output units. At least one transistor of each driving signal output unit and multiple transistors of the memory are fabricated by an identical semiconductor fabrication process so that the gate oxide layers of the transistors of the driving signal output unit and the memory are identical in thickness. As the transistor of each driving signal output unit and those of the memory are fabricated by a same high-voltage semiconductor fabrication process, the transistor of each driving signal output unit can be fabricated to provide a capacitive touch panel controller having high-voltage driving capability without using any high-voltage fabrication process and increasing the production cost. Due to the high-voltage driving, the SNR and anti-interference capability can be increased.

Abstract: An object of the present invention is to efficiently heat a refrigerant retained in a compressor. An inverter control unit generates six drive signals corresponding to the respective switching elements of the inverter, and outputs the generated drive signals to the corresponding switching elements of the inverter to cause the inverter to generate a high-frequency AC voltage. Particularly, the inverter control unit generates a drive signal having a switching pattern A for turning on all the three switching elements on a positive voltage side or a negative voltage side of the inverter, and subsequent thereto, generates a drive signal having a switching pattern B for turning on two switching elements of the three switching elements and turning off one switching element thereof.

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

Abstract: A conversion control circuit for controlling the operation of a power transistor is disclosed. The conversion control circuit includes a voltage-regulating switch and a control unit. One end of the voltage-regulating switch connects to an external voltage input terminal while another end connects to a voltage-regulating capacitor. The conversion control circuit converts an input voltage inputted from the external voltage input terminal into a power voltage. The power voltage is for supplying operating power to the conversion control circuit. The control unit receives a feedback voltage signal to generate a voltage-regulating pulse signal and a turn-on pulse signal, which are used for controlling the operations of the voltage-regulating switch and the power transistor, respectively and for defining a charging period for charging the voltage-regulating capacitor. A converter including the described conversion control circuit is also disclosed.

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract: A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation.

Abstract: Various embodiments of the present invention relate to a voltage generator, and more particularly, to systems, devices and methods of configuring a charge pump system by incorporating an auxiliary charge pump to generate an intermediate voltage that is used to boost up a primary charge pump according to a level of an input supply voltage. The intermediate voltage has a higher level than that of the input supply voltage, and is provided to boost up the primary charge pump when the input supply voltage is determined to be lower than a threshold voltage. Such a charge pump based voltage generator is compatible to a wide input supply range, capable of sustaining a large output load and effectively reduces the chip estate.

Abstract: A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.

Abstract: The output voltage of a LP HV charge pump is compared with a voltage reference using a comparator having hysteresis. When the output voltage exceeds the reference voltage, an input clock to the charge pump is turned off, causing the output voltage to fall due to leakage current in the non-volatile memory. After a time delay due to the hysteresis of the comparator, the input clock is turned on, causing the output voltage to rise again until the voltage reference is again exceeded at which time the input clock is again turned off again. The process repeats, resulting in a reduction of average current consumption by the LP HV charge pump.

Abstract: Operation of a charge pump is controlled to optimize power conversion efficiency by using an adiabatic mode with some operating characteristics and a non-adiabatic mode with other characteristics. The control is implemented by controlling a configurable circuit at the output of the charge pump.

Abstract: An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.

Abstract: The present disclosure provides a method of reusing electrical energy for a charge pump. The method comprises operating in a reusing phase after a boosting phase is completed; retrieving energy of parasitic capacitance in the reusing phase; and reusing the energy of the parasitic capacitance for an internal circuit.

Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.

Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for a capacitor of a stage of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level then subsequently to the auxiliary pump's level.

Abstract: In one aspect, a charge pump output of a charge pump is coupled to a capacitor of a voltage shifter. The output of the voltage shifter causes pump control logic to enable the charge pump. In another aspect, a transistor in saturation has a drain terminal coupled to a charge pump output and a source terminal coupled to an output mode providing a word line read voltage.

Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: Various technologies described herein pertain to automatically adjusting the strength of a voltage booster of an image sensor. A self-scaled voltage booster includes a regulator, a controller, and two or more charge pumps that can be selectively enabled and disabled by the controller. The controller generates controller signals for the charge pumps based on a duty cycle of a regulator signal generated by the regulator. Moreover, the controller can maintain the controller signals without modification for at least a predetermined minimum period of time after a prior modification of at least one of the controller signals. Further, the controller can include a duty cycle and delay module (or a plurality of duty cycle and delay modules) that detects the duty cycle of the regulator signal and maintains the controller signals without modification for at least the predetermined minimum period of time.

Abstract: Aspects are directed to low dropout regulation. In accordance with one or more embodiments, an apparatus includes a charge pump that generates an output using a reference voltage, a low dropout (LDO) regulator circuit, current-limit and a voltage-limit circuit. The LDO circuit includes an amplifier powered by the charge pump and that provides an LDO voltage output. The voltage-limit circuit includes a transistor coupled between a voltage supply line and the LDO regulator circuit and a gate driven by the charge pump. The voltage-limit circuit limits voltage coupled between the voltage supply line and the LDO regulator circuit based upon the output of the charge pump, such as by coupling the voltage at the voltage supply line via source/drain connection of the transistor under low-voltage conditions, and providing a limited voltage to the LDO regulator circuit under high voltage conditions on the voltage supply line.

Abstract: A voltage generation circuit includes an oscillator configured to output a first period signal and a second period signal in response to a detection signal; a period signal select unit configured to receive the first and second period signals and output one of the first and second period signals as an additional period signal in response to a control signal; and a charge pump unit configured to charge-pump an input voltage in response to the first period signal and the additional period signal and generate a power supply voltage.

Abstract: A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control circuit to generate a control signal for each of the charge pumps. The control signal causes each of the charge pumps to be enabled, partially enabled, or disabled, and controls at least one of the charge pumps independently of the other charge pumps.

Abstract: A charge pump circuit includes a charge pump, a regulator circuit, and a load current, wherein the charge pump circuit further includes: a filter circuit connected to an output terminal of the charge pump for filtering an output voltage of the charge pump; and a ripple control circuit connected both to the output terminal of the charge pump and to the filter circuit for reducing the output voltage of the charge pump upon an increase thereof, thereby attenuating ripples contained in the output voltage of the charge pump. The charge pump circuit is capable of enabling a relatively stable output voltage for the charge pump, thus benefiting a downstream integrated circuit.

Abstract: A charge pump circuit includes a plurality of serially coupled stages and a plurality of clock drivers. A voltage output of a first of the stages is connected to a voltage input of a second of the stages. A voltage output of the second of the stages is boosted relative to a voltage input of the second of the stages. Each of the stages includes complementary charge pumps. Each of the charge pumps includes a pumping capacitor that stores charge in the stage. Each of the clock drivers drives a clock signal to the pumping capacitor of at least one of the stages. A voltage of the clock signal provided to the second of the stages is derived from the voltage input of the second of the stages.

Abstract: The present document relates to charge pump voltage doublers for use in integrated circuits. A charge pump circuit configured to generate an output voltage Vout at an output of the circuit from an input voltage Vin at an input of the circuit is described. The circuit further comprises a boosting capacitor coupled at a first side to the output node of the first P-type switch and coupled at a second side to a capacitor control signal. Furthermore, the circuit comprises control circuitry configured to provide a capacitor control-signal-which alternates between a low level and a high level, and configured to generate first and second control signals based on the capacitor control signal for alternating the first and second P-type switches between on-states and off-states, respectively, such that electrical energy is transferred from the input to the output of the circuit using the boosting capacitor.

Abstract: There is provided a semiconductor device in which an influence of a power source noise is suppressed and the number of pins and the area of the semiconductor device are reduced. A power source line for a first internal circuit and a power source line for a second internal circuit are coupled to a common pin terminal. A ground line for the first internal circuit and a ground line for the second internal circuit are coupled to another common pin terminal. A power source noise generated on the power source line for the first internal circuit during an operation of the first internal circuit is absorbed by a P-channel MOS transistor and a capacitor. A power source noise generated on the ground line is absorbed by an N-channel MOS transistor and the capacitor.

Abstract: A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result.