Abstract: Disclosed is a device and method for providing a bounded bias voltage with improved Process Voltage Temperature (PVT) adjustment. An embodiment may include a bias_n generation circuit that adjusts a bias_n voltage for PVT as a function of two bias_n NMOS transistors/diodes and a bias_p generation circuit that adjusts a bias_p voltage for PVT as a function of two bias_p PMOS transistors/diodes. An embodiment may further include a PVT adjusted bounded bias voltage circuit comprised of a NMOS transistor with the bias_n voltage at the gate and a PMOS transistor with the bias_p voltage at the gate such that a common connection between the NMOS and PMOS transistors generates a bounded bias voltage adjusted for PVT as a function of two body biased voltages (bias_n/bias_p). The bounded bias voltage may be used to provide a low supply voltage to a low voltage device using an available high voltage supply.

Abstract: An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage. The input buffer further includes a bias circuit configured to generate the variable voltage responsive to a state of the input signal.

Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.

Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

Abstract: It is described a high efficiency rectification stage using dynamic threshold MOSFET. The idea is to use the input signal to reduce the threshold voltage when the transistor has to be on, and to increase the threshold when the transistor has to be off. This allows reducing both the resistive losses and the leakage current. A matching network allows the generation of a second higher voltage signal to drive the control gates and the bulk, i.e. the wells, of the transistors. Further, a self-tuned front-end is provided to extend the bandwidth of the high-Q charge pump.

Abstract: A semiconductor integrated circuit includes a current mirror having a predetermined input-output ratio and including a first transistor configured to receive an input current and a second transistor configured to output an output current, and an output transistor configured to generate a reference voltage according to the output current of the current mirror. The value of the output current is greater than the value of the input current, and the total area of one or more collector regions of the first transistor is substantially the same as the total area of one or more collector regions of the second transistor.

Abstract: A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: A voltage generating system and a memory device using the same are disclosed. The voltage generating system includes an internal voltage regulator, configured to supply a current to pull an internal supply voltage to a regulated level and maintain at the regulated level; and a substrate-bias controlled selector, configured to receive a regulator power-up mode signal, a regulating mode signal and a substrate-bias voltage of a substrate, and control the internal voltage regulator such that when the substrate-bias voltage is smaller than a predetermined voltage, the internal voltage regulator powers up and operates normally by respectively taking the regulator power-up mode signal and the regulating mode signal into consideration, and when the substrate-bias voltage is larger than or equal to the predetermined voltage, the internal voltage regulator is disabled. The predetermined voltage is smaller than or equal to a forward voltage of a p-n junction formed with the substrate.

Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.

Abstract: A voltage booster system of a charge pump type includes a regulator for outputting a constant voltage and a charge pump circuit for boosting a voltage of an output terminal of the regulator. The regulator includes a differential amplifier unit for inputting a reference voltage and a feedback voltage according to the voltage of the output terminal, and an output stage portion including an PN connection element having one end portion connected to an application terminal of a power source voltage and another end portion connected to the output terminal. The PN connection element is configured to be controlled according to an output signal of the differential amplifier unit. The charge pump circuit includes a first capacitor to which the voltage of the output terminal is applied to be charged; a second capacitor; a third capacitor; a first switching section; and a second switching section.

Abstract: One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.

Abstract: An integrated circuit in which a voltage divider circuit is integrated comprises a first resistor, second resistor, control portion, switch, and switching portion. The first resistor and second resistor form a resistive voltage divider element for dividing a voltage obtained by rectifying an alternating-current voltage, or a direct-current voltage, supplied to a control portion. The switch is provided in series with the resistive voltage divider element, and passes or cuts off current passing through the resistive voltage divider element. The switching portion switches the switch so as to pass current during driving of the control portion, and cut off current during standby of the control portion.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element. The capacitance disconnecting circuit includes a non-volatile memory cell with a threshold voltage changed based on a change of a leakage current which flows from the capacitance element, and blocks off the leakage current based on a rise of the threshold voltage of the non-volatile memory cell when the leakage current exceeds a predetermined value.

Abstract: A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current.

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract: A bias voltage generation circuit includes a first current source connected to a first power source; a first transistor which is diode connected and is connected to the first current source; a second transistor connected between the first transistor and a second power source; a second current source connected to the first power source; a third transistor connected to the second current source; a fourth transistor connected between the third transistor and the second power source; a first output point connected to the first transistor and the third transistor and outputs a first bias voltage; a second output point connected to the fourth transistor and the second current source and outputs a second bias voltage; and a bias voltage adjusting circuit which adjusts the first bias voltage in accordance with a control input.

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

Abstract: Some embodiments of the present disclosure relate to regulators for charge pumps. Such regulators selectively activate a charge pump based not only on the voltage output of the charge pump, but also on an series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations.

Abstract: Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Abstract: A semiconductor memory apparatus that generates a voltage by performing a pumping operation in response to an oscillator signal includes a driving voltage detecting unit configured to control the cycle of the oscillator signal in accordance with the level of a driving voltage that is used to perform the pumping operation.

Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

Abstract: The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased.

Abstract: A transconductance-capacitance (Gm-C) filter of arbitrary order is provided that is biased by a bias circuit such that the Gm-C filter is robust to variations in process corner and temperature as well as input supply noise. The bias circuit includes a biased transistor that has a width-to-length ratio that is a factor X times larger than a corresponding transistor in the Gm-C filter. The biased transistor couples to ground through a switched capacitor circuit.

Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.

Abstract: A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.

Abstract: A direct current (DC) to DC converter, including: input ports for receiving an input DC voltage; output ports for outputting an output DC voltage; a first matrix of capacitors and switches; a second matrix of capacitors and switches; and a control circuit, coupled to the switches of the first and second matrices, configure d to repetitively: (i) configure the first matrix to a charge configuration and couple the first matrix to the input ports while configuring the second matrix to a discharge configuration and coupling the second matrix to the output ports; (ii) maintain the charge and discharge configurations for a first period of time; (iii) configure the second matrix to the charge configuration and couple the second matrix to the input ports while configuring the first matrix to the discharge configuration and couple the first matrix to the output ports; and (iv) maintain the charge and discharge configurations for a second period of time; (a) wherein the charge configuration and the discharge configurat

Abstract: Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.

Abstract: A high-voltage integrated circuit device can include, in a surface layer of a p semiconductor substrate, an n region which is a high-side floating-potential region, an n? region which becomes a high-voltage junction terminating region, and an n? region which is an L-VDD potential region. A low-side circuit portion can be disposed in an n? region. Below a pickup electrode disposed in the high-voltage junction terminating region, a universal contact region in Ohmic contact with the pickup electrode can be disposed. The universal contact region has a p+ region and an n+ region that can be disposed in alternating contact along a surface of the p semiconductor substrate. By disposing the universal contact region in this way, the quantity of carriers flowing into the low-side circuit portion can be reduced when a negative surge voltage is input. Consequently, erroneous operation due to latchup of a logic portion can be minimized.

Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

Abstract: A body-bias voltage source having an output monitor, charge pump, and shunt. a shunt circuit having on/off control is coupled to the output monitor and to the output of the charge pump. Upon sensing that the output voltage of the charge pump is above a desired value, the output monitor may disable the charge pump circuit and may enable the shunt circuit to reduce the voltage at the output of the charge pump. When the voltage output of the charge pump is below the desired value, the output monitor may disable the shunt circuit and may enable the charge pump circuit. A shunt circuit having proportional control may be substituted for the shunt circuit with on/off control.

Abstract: Even in the case where negative current flows in a semiconductor device, the potential of a semiconductor substrate is prevented from becoming lower than the potential of a deep semiconductor layer which is a component of a circuit element, and a parasitic element is prevented from operating, which accordingly prevents malfunction of the semiconductor device. The semiconductor device includes the n-type semiconductor substrate, a power element, the circuit element, and an external circuit. The external circuit includes a power supply, a resistive element having one end connected to the power supply, and a diode having its anode electrode connected to the other end of the resistive element and its cathode electrode connected to the ground. To the other end of the resistive element, a semiconductor layer is connected.

Abstract: The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage.

Abstract: Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load.

Abstract: A semiconductor device includes a precharge circuit configured to precharge a voltage output node, a boosting circuit configured to boost a voltage at the voltage output node by a predetermined level after the voltage output node is precharged, and a voltage supply circuit configured to supply a pumping voltage to increase the voltage at the voltage output node to a target level.

Abstract: A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A current sensor is disclosed comprising a differential amplifier including a first node, a second node, and an output. The current sensor further comprises a first resistor having a first end coupled to the first node and a second end for coupling to a transducer, and a second resistor having a first end coupled to the second node and a second end. When the second end of the second resistor is unconnected and the differential amplifier is driven with a supply voltage, the first node is biased by a first leakage current and the second node is biased by a second leakage current such that the output represents a current flowing through the transducer.

Abstract: We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.

Abstract: According to one embodiment, an output signal circuit for use in a receiver is provided. The output signal circuit is provided with first and second transistors of an insulated gate field effect type, and a backgate bias generator. A source of the first transistor is capable of receiving an input signal. A source of the second transistor is capable of generating an output signal. A backgate bias generator produces a backgate bias voltage which is applied to backgate of the first and second transistors commonly.

Abstract: An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.

Abstract: According to one embodiment, a power supply stabilizing circuit includes at least one bias voltage generation circuit and at least one voltage supply circuit. The at least one bias voltage generation circuit is configured to compare a reference voltage and a signal corresponding to a bias voltage which is generated from an unstable voltage, thereby generating the bias voltage. The at least one voltage supply circuit is disposed near a functional circuit, is connected to the functional circuit by a wiring line, and is configured to stabilize the unstable voltage, based on the bias voltage which is supplied from the at least one bias voltage generation circuit, and to supply a stabilized voltage to the functional circuit.

Abstract: An apparatus includes a charge pump array including multiple charge pump cells. The charge pump array is configurable into a first arrangement of the charge pump cells coupled in series or a second arrangement of the charge pump cells coupled in parallel. The apparatus can include reconfiguration circuitry configured to select the first arrangement of the charge pump cells or the second arrangement of the charge pump cells. The charge pump array is configured to alter a voltage level of a signal based, at least in part, on the selected arrangement of the charge pump cells.

Abstract: An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.

Abstract: A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

Abstract: Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed.