Abstract: An arrangement includes a first electronic device and a power supply unit adapted to provide the first electronic device with electric operating energy from a mains voltage. The first electronic device includes an evaluation unit adapted to switch the first electronic device from an operating state to at least one energy saving state and vice-versa, and a standard interface for connecting the first electronic device to a second electronic device.

Abstract: A diagnostic imaging device includes a signal processing circuit (22) processes signals from a detector array (16) which detects radiation from an imaging region (20). The hit signals are indicative of a corresponding detector (18) being hit by a radiation photon. The signal processing circuit (22) includes a plurality of input channels (321, 322, 323, 324), each input channel receiving hit signals from a corresponding detector element (18) such that each input channel (321, 322, 323, 324) corresponds to a location at which each hit signal is received. A plurality of integrators (42) integrate signals from the input channels (32) to determine an energy value associated with each radiation hit. A plurality of analog-to-digital converters (441, 442, 443, 444) convert the integrated energy value into a digital energy value. A plurality of time to digital converters (40) receive the hit signals and generate a digital time stamp.

Abstract: In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.

Abstract: According to one embodiment, a semiconductor device includes an internal circuit which is driven by a power supply voltage and is set in one of a first state and a second state in which an amount of current consumed by the internal circuit is greater than in the first state, and a wait control module. The wait control module detects that a state of the internal circuit has transitioned from the first state to the second state, and executes a wait control process of outputting an operation start instruction signal to the internal circuit after passing of a predetermined wait time from the detection of the transition of the state of the internal circuit from the first start to the second state.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.

Abstract: A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.

Abstract: A signal delaying system is provided, including a delay locked loop circuit and a voltage providing circuit. The delay locked loop circuit delays an input signal to generate a delayed signal. The voltage providing circuit provides a control voltage to the delay locked loop circuit for determining a delay time of the delay locked loop circuit when the delay locked loop circuit operates in a first mode; and providing a stand-by voltage to the delay locked loop circuit when the delay locked loop circuit operates in a second mode, wherein the voltage providing circuit further adjusts the stand-by voltage to make the stand-by voltage substantially equal to the control voltage.

Abstract: A semiconductor integrated-circuit device rectifies a received carrier wave, generates a first power-supply voltage based on the rectified output, and selects, as a power-supply voltage required for operation, one of the first power-supply voltage and a supplied second power-supply voltage. The first power-supply voltage is selected as the power-supply voltage required for operation when the second power-supply voltage is lower than a threshold value. The second power-supply voltage is selected as the power-supply voltage required for operation when the second power-supply voltage is equal to or higher than the threshold value and an instruction to operate in accordance with a predetermined function is given.

Abstract: In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.

Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.

Abstract: Power management integrated circuit and related devices. A clock generator generates a periodic signal. Based on the periodic signal and a feedback signal, a pulse width modulator generates a control signal, based on which a driver drives a power switch. A power terminal is connected to an external capacitor. A linear regulator connected to the power terminal generates and supplies an internal power source. Powered by the internal power source, a bandgap generator provides a bandgap reference voltage. A standby control terminal receives a standby signal. When the standby signal is asserted, the clock generator, the pulse with modulator and the driver are at a disabled state, and the linear regulator and the bandgap generator at an enabled state.

Abstract: Each of computing units on a semiconductor integrated circuit includes a first signal output unit that outputs a first status signal indicating a state of a input/output control unit with regard to an access to a storage unit, a second signal output unit that outputs a second status signal indicating a state of a process control unit with regard to an access to a processing unit, and a power control unit that control ON and OFF of power of the storage unit and the processing unit based on states of the first status signal and the second status signal.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: A network status indicating circuit includes a logic circuit, a switch circuit, and an indicating unit. The logic circuit includes nine input ends, a NOT gate, and two OR gates. The switch circuit includes two input ends and two output ends. The indicating unit includes two LEDs. The logic circuit is connected to the indicating unit to indicate the status of a network IC.

Abstract: Disclosed herein is a semiconductor integrated circuit including a stoppable circuit unit configured to be alternately switched between a stopped state and an operating state; a first voltage line configured to apply a first voltage to the stoppable circuit unit when the stoppable circuit unit is in the operating state; a second voltage line configured to apply the first voltage to the stoppable circuit unit when the stoppable circuit unit is in a transient state of switching from the stopped state to the operating state; and a third voltage line configured to apply a second voltage to the stoppable circuit unit.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

Abstract: A semiconductor integrated circuit includes a first power supply whose potential is controlled under control operation from an external control circuit, a second power supply whose potential is controlled under control operation from the external control circuit, and whose potential can be set independently of the first power supply, a first power-supply system comprising a circuit driven by the first power supply, a second power-supply system comprising a circuit driven by the second power supply, and a connecting circuit that performs connecting operation between a first high-potential line of the first power-supply system and a second high-potential line of the second power-supply system in response to a potential-matching signal indicating that the first power-supply system and the second power-supply system are operated by the same potential from the external control circuit.

Abstract: A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.

Abstract: A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

Abstract: An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage node to apply the internal voltage to the internal voltage node in response to a voltage level of the first node, and/or a leakage current interrupting portion to apply an external voltage to the first node to deactivate the internal voltage driving portion and to interrupt the external voltage applied to the driving node to interrupt a leakage current.

Abstract: A particularly high level of performance in a sensorless, electronically commutated multiphase electric motor can be achieved, wherein for one full cycle at least, one motor phase is controlled in an asymmetrical manner relative to a further motor phase by controlling a commutation angle of one motor phase by reduction relative to a corresponding commutation angle of the other motor phase. Alternatively or in addition, according to the aforementioned method, at least one motor phase is asymmetrically controlled by reduction by self-reference for a full cycle, a commutation angle being controlled by reduction relative to a preceding or subsequent commutation angle or the size of the intermediate angles between two commutation angles being varied, the reduced commutation angle always being preceded or followed by a measurement angle within which the relevant motor phase is switched at zero current for detecting the rotor position by measuring the counter-electromotive force.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A semiconductor integrated circuit apparatus includes a first circuit block including a critical path and second and third circuit blocks not including the critical path. A threshold voltage of a semiconductor element of a circuit in the first circuit block is equal to or lower than a threshold voltage of a semiconductor element of a circuit in the second circuit block and a supply voltage supplied to the first circuit block is equal to or higher than a supply voltage supplied to the second circuit block, wherein the critical path in the first circuit block is eliminated. A threshold voltage of a semiconductor element of a circuit in the third circuit block is equal to or lower than the threshold voltage of the semiconductor element of the circuit in the second circuit block, and a supply voltage supplied to the third circuit block is equal to or lower than the supply voltage supplied to the second circuit block, wherein power consumption of the third circuit block is reduced.

Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: A voltage providing circuit includes: a first voltage providing circuit, for generating a first voltage; a switch device, for receiving a first voltage; a second voltage providing circuit, for providing a second voltage; a control circuit, for controlling the switch device and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch device for allowing a target device to receive the second voltage, and in a second mode, the control circuit turns on the switch device and stops the second voltage providing circuit from providing the second voltage such that the target device can receive the first voltage; and an adjusting circuit, for providing a reference voltage to the first voltage providing circuit according to the first voltage and the second voltage for changing the first voltage, thereby making the first voltage substantially equal to the second voltage.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

Abstract: A bias generation circuit is between a power voltage node and ground voltage node at a far end from power voltage and ground voltage terminals. Reference voltage nodes are connected to an amplifier circuit block from the far end. The amplifier block is closer to the power supply source, and the bias generation circuit is distant therefrom. Even if the power supply voltage drops due to current constantly flowing in the amplification block and bias generation circuit, the bias generation circuit generates reference voltages at the reference voltage nodes based on the voltage-dropped power supply. Therefore, the voltage in the constant current source MOS transistor of the amplifier block becomes lowest at the amplifier circuit closest to the bias generation circuit. The response speeds of other amplifier circuits do not drop if the circuit is designed based on the amplifier closest to the bias generation circuit.

Abstract: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.

Abstract: A method, system, module, apparatus, use, and computer program product are shown for determining a supply voltage level for operating an integrated circuit. To allow exact voltage level calibration, a high load condition is provided to the integrated circuit, a first voltage level of the integrated circuit is adjusted to provide a stable operation of the integrated circuit in the high load condition, a temperature of the integrated circuit in the high load condition is measured, the measured temperature in the high load condition is stored along with the adjusted first voltage level in the high load condition.

Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.

Abstract: In related arts, a body voltage needs to be controlled by separately detecting external environment such as temperature. In the related art, variation such as a process parameter for each individual product has not been considered. A semiconductor integrated circuit according to the present invention includes a comparator comparing a leak current of a first conductive type transistor with a leak current of a second conductive type transistor to output a comparing result, and a conduction control signal generator outputting a signal determining a conduction state of the first conductive type transistor and a conduction state of the second conductive type transistor in a power saving control target circuit in a power saving mode based on the comparing result.

Abstract: A voltage regulator arrangement having a first voltage regulator, whose input connection is connected to the supply potential connection and whose output connection is connected to a first supply potential connection of a circuit arrangement, with the first voltage regulator supplying the circuit arrangement with a supply voltage in a rest state. A second voltage regulator is also provided, whose input connection is connected to the supply potential connection, and whose output connection is connected to a second supply potential connection of the circuit arrangement, with the second voltage regulator supplying the circuit arrangement with a supply voltage during its normal operation.

Abstract: The present invention provides an integrated virtual voltage circuit for use with a sub-circuit. In one embodiment, the integrated virtual voltage circuit includes a MOS transistor switch coupled to a supply voltage and configured to employ a drain to provide an operating voltage for the sub-circuit during switch activation. Additionally, the integrated virtual voltage circuit also includes a connection unit coupled to the MOS transistor switch and configured to provide a standby voltage for the sub-circuit during deactivation of the MOS transistor switch wherein the standby voltage is based on a static coupling of the drain to a body region of the MOS transistor switch. In an alternative embodiment, the connection unit is further configured to connect a voltage reference between the supply voltage and the drain of the MOS transistor switch to determine the standby voltage.

Abstract: An electronic device includes a rechargeable battery, an electrical circuit, a battery safety circuit, and a power down mode circuit. The electrical circuit is configured to generate a power mode control signal. The power down mode circuit receives the power mode control signal. If the power mode control signal has a first value, the power down mode circuit is configured to force a voltage at a first port of the battery safety circuit to a voltage value that is less than an under voltage lock out (UVLO) threshold value of the battery safety circuit to transition the electronic device from a normal operating mode to a low current power down mode. The electronic device may further include a wake up mode circuit.

Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: A standby regulator circuit includes a standby bias circuit and a standby operational amplifier. The standby regulator circuit provides a standby regulated control voltage to a multiplexer. A regular operational amplifier provides a regulated control voltage to the multiplexer. During regular operation, the multiplexer selects the regular operational amplifier and selects the standby regulator circuit in a low-power mode. The multiplexer couples to a native pass transistor gate having a threshold voltage about equal to 0 V. The native pass transistor provides a regulated output voltage with relatively low-level input control voltages. In low-power mode, a power-down signal, provided to the multiplexer, smoothly transitions regulated control voltage from the regular operational amplifier to regulated control voltage sourcing from the standby operational amplifier.

Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

Abstract: A circuit unit is provided. The circuit unit has an intermittent operation circuit. The intermittent operation circuit is set in an operation state and in a stand-by state periodically. An operation mode control unit generates a test mode control signal to designate either an operation test mode or an intermittent operation test mode of the intermittent operation circuit. The operation test mode corresponds to one of a continuous operation or a predetermined time period operation of the intermittent operation circuit. An operation timing generation unit receives the test mode control signal. The operation timing generation unit produces an operation control signal based on the test mode control signal. The operation control signal is outputted to the intermittent operation circuit to operate or wait the intermittent operation circuit.

Abstract: A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivated during the suspend mode. Deactivation of one or more power supplies during a normal mode of operation is also facilitated, whereby current paths created by the deactivated power supplies are also eliminated. Voltage bias circuitry is added to certain voltage regulators within the IC, so as to maintain those voltage regulators inactive due to a drop in voltage magnitude that is sensed when one or more power supplies are disabled. In addition, a well bias circuit is employed to maintain the substrate bias potential of certain devices within the voltage regulators and associated amplifiers to a fixed potential depending upon the operational mode of the IC.