Abstract: The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.

Abstract: An A/D converter provides one or more operational amplifiers as components. The A/D converter includes a current controlling unit that is activated before an actual operation of the A/D converter to control a current of at least one of the operational amplifiers based on a settling characteristic of the operational amplifier.

Abstract: An analog baseband, a computer readable medium, and a method for powering on and off a set of regulators in the analog baseband, where each regulator is configured to provide a predefined voltage. The method includes storing in a register of the analog baseband at least n bits, where n is an integer larger than 2, assigning in the analog baseband, to each regulator, a number of m bits of the n bits, where m times a number of the regulators is smaller than or equal to n, programming in the analog baseband the at least n bits in a sequence of m bits that describes a time when each regulator is powered on or off and an order in which each regulator is powered on or off upon reception of a sleep signal, receiving in the analog baseband the sleep signal that indicates whether the set of regulators are powered on or off, and instructing, based on sequence of m bits stored in the registers of the analog baseband, the set of regulators to power on or off based on the received sleep signal.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: A multi-system module having a functional substrate includes a substrate comprising therein at least one control circuit units, and a plurality of main circuit units provided on one side surface of the substrate. The main circuit units are electrically connected to the control circuit unit, whereby the control circuit unit is used to manage the operation of the main circuit units. Via the above module structure, the substrate can improve the function of controlling multiple systems.

Abstract: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.

Abstract: Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated.

Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

Abstract: A low-voltage power switch includes a gate-controlled circuit and a switch. The gate-controlled circuit generates a control voltage lower than the voltage of ground according to a control signal. The switch includes a first end, a second end, and a control end. The first end of the switch is coupled to a power supply of a low voltage, the control end of the switch is coupled to the gate-controlled circuit for receiving the gate-controlled signal, and the second end of the switch couples the first end of the switch when the switch receives the gate-controlled signal for outputting the power supply of the low voltage.

Abstract: An external accessory that can be attached to and detached from an electronic apparatus equipped with a power source unit includes: a first power receiving unit that receives power from the power source unit of the electronic apparatus; a second power receiving unit that receives power from the power source unit of the electronic apparatus; a decision-making unit that makes a decision as to whether or not the first power receiving unit is receiving power; a function execution unit that executes a predetermined function by using power received at one of the first power receiving unit and the second power receiving unit; and a control unit that engages the function execution unit in operation continuously when an affirmative decision is made by the decision-making unit, and engages the function execution unit in operation intermittently when a negative decision is made by the decision-making unit.

Abstract: The present invention provides a power saving circuit for PWM circuit. The power saving circuit is utilized to control at least one internal circuit. The power saving circuit comprises a switching circuit which generates a switching signal. The power saving circuit controls the internal circuit in response to the switching. The power saving circuit disables the internal circuit for power saving when the switching signal is disabled.

Abstract: A reference generating apparatus and a sampling apparatus thereof are provided. The coding module is configured to code and decode a first reference signal to retrieve a second reference signal with less power than generating the first reference signal. The second reference signal is identical to the first reference signal in amplitude.

Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: A method of controlling power consumption in an electronic device may include selecting between an on mode of the electronic device in which first circuitry of the electronic device is configured to perform a first operation, an off/standby mode in which second circuitry of the electronic device is configured to perform a second operation, and a sleep/vacation mode in which the second circuitry is controlled to at least one of reduce a frequency of and suspend performance of the second operation. An electronic device may include: first circuitry configured to perform a first operation when the electronic device is in an on mode; second circuitry configured to perform a second operation when in an off/standby mode; and a circuitry controller configured to control the second circuitry to at least one of reduce a frequency of and suspend performance of the second operation when in a sleep/vacation mode.

Abstract: A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.

Abstract: Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header.

Abstract: A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

Abstract: A semiconductor integrated circuit device comprises: a circuit block, a first MOS transistor, a first power line, a second power line, a third power line, and a drive circuit. The first MOS transistor is connected between the first and second power lines. The circuit block is connected between the second and third power lines. The drive circuit controls a voltage supplied to a gate of the first MOS transistor. The first MOS transistor is off in a standby state and on in an operation state. During a shift from the standby state to the operation state and a shift from the operation state to the standby state, the drive circuit changes the voltage supplied to the gate of the first MOS transistor at a first rate, and then, changes the voltage supplied to the gate of the first MOS transistor at a second rate faster than the first rate.

Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.

Abstract: A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.

Abstract: A system is disclosed for reducing power drain of a component when the component is in a powered down state. The system comprises a power input configured to receive power, a power output to the component, monitor logic configured to monitor a level of power moving between the input and output, and control logic configured to control power transfer between the input and output. The control logic may be in communication with the monitor logic and configured to selectively restrict power flow between the input and output when the monitor logic senses that power flow between the input and output falls below a threshold level. A method comprises checking a power level between the input and output, and if the power level exceeds a threshold, then permitting substantially unrestricted power flow. If the power level is less than the threshold, then restricting the power level between the input and output.

Abstract: An apparatus for selectively enabling power including a power supply, and a device having a controller and an input activated by a user. The controller is selectively powered by the power supply. While the device is in a sleep state, a sensing circuit senses activation of the input by the user and enables the power supply to provide power to the controller in response to the sensed activation of the input by the user. A latch circuit causes the power supply to continue to provide power to the controller. The controller is responsive to the sensed activation of the input by the user for enabling the latch circuit and for disabling the latch circuit, thereby reentering the device into a sleep state.

Abstract: A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a tristateable device, said tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being rece

Abstract: An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101, 102) from an active mode to a standby mode.

Abstract: Provided are an internal voltage initializing circuit for use in a semiconductor memory and a driving method thereof, which are capable of preventing a back bias voltage from abnormally increasing due to a pumping operation of a VPP pump according to a change in a level of a power-up signal. The internal voltage initializing circuit includes: a high voltage initializing unit for selectively connecting a power supply voltage terminal an a high voltage terminal in response to a power-up signal; and a back bias voltage initializing unit for selectively connecting a ground terminal and a back bias voltage terminal in response to a signal produced by delaying the power-up signal by a predetermined time.

Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.

Abstract: Disclosed herein is a semiconductor integrated circuit including, a circuit section, a first voltage line, a second voltage line, a third voltage line, a switch section, and a control section.

Abstract: A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom.

Abstract: A power gating structure controls a connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes. The power gating structure includes a first path and a second path. In an active mode, the first path electrically couples the power supply terminal with the virtual power supply node in response to a first control signal. In a data retention mode, the second path electrically couples the power supply terminal with the virtual power supply node in response to the first control signal and a second control signal with a predetermined voltage level difference. In a power-down mode, both the first path and the second path electrically isolate the power supply terminal from the virtual power supply node in response to the first control signal and the second control signal.

Abstract: An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.

Abstract: A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value.

Abstract: A power supply circuit includes a voltage output controller configured for outputting voltages, a standby controller configured for directing the voltage output controller to provide voltage to a load, and a microprocessor configured for controlling the standby controller according to a mode of the load. The voltage output controller is applied with a direct current voltage. When the load enters active mode from a powered off mode, the standby controller sends a control signal to the voltage output controller to output direct current voltage to the load and the microprocessor. When the load enters standby mode from the active mode, the microprocessor directs the standby controller to prevent the voltage output controller from outputting direct current voltage to the load and the microprocessor.

Abstract: A semiconductor integrated-circuit device rectifies a received carrier wave, generates a first power-supply voltage based on the rectified output, and selects, as a power-supply voltage required for operation, one of the first power-supply voltage and a supplied second power-supply voltage. The first power-supply voltage is selected as the power-supply voltage required for operation when the second power-supply voltage is lower than a threshold value. The second power-supply voltage is selected as the power-supply voltage required for operation when the second power-supply voltage is equal to or higher than the threshold value and an instruction to operate in accordance with a predetermined function is given.

Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry is suitable for powering core logic on a programmable logic device. The voltage regulator circuitry receives an external power supply voltage and reduces the external power supply voltage to a core power supply voltage if needed. If the external power supply voltage is at the same level needed to power the core logic, the voltage regulator circuitry passes the power supply voltage to the core logic. The voltage regulator circuitry monitors the core power supply voltage using a feedback path. Overshoot and undershoot fluctuations are minimized. The external power supply voltage may be supplied to a first bus. The core power supply voltage may be distributed on a second bus. A ring of transistors may be used to convey power from the first bus to the second bus. Control circuitry may control the ring of transistors based on programmable setpoint voltages.

Abstract: An apparatus for optimizing power consumption of an electrical circuit component in an operating- and evaluating-circuit of a two-conductor field device, wherein a control unit is provided, which switches the electrical circuit component with a clock signal. An energy supply unit is provided for supplying the circuit component with energy, and wherein at least one energy-storing component is connected to at least one output, at least one input and/or a supply input of the electrical circuit component. The apparatus provides for a field device, a suitable electronics for enabling improvement of the energy budget of the evaluating- and operating-circuit, especially its circuit component.

Abstract: A sleep mode control circuit and method are provided to pull high the error signal of a DC/DC switching power supply system to a target level when the switching power supply system is in a sleep mode, such that the switching power supply system can be more rapidly waked up from the sleep mode to its normal mode once the loading of the switching power supply system increases. A threshold is given for the output signal of the comparator that is used to determine the duty for the switching power supply system, and the error signal in the sleep mode is thus maintained slightly lower than the minimum voltage for the error signal in the normal mode.

Abstract: A supply voltage switching circuit for a computer includes a chipset, a first transistor and a second transistor. The chipset includes a first MOSFET and a second MOSFET. A 5V system voltage and a 5V standby voltage are respectively inputted to sources of the first MOSFET and the second MOSFET. Gates of the first MOSFET and the second MOSFET are respectively coupled to collectors of the first transistor and the second transistor. Emitters of the first transistor and the second transistor are coupled to a first terminal for receiving a control signal. A 1.8V standby voltage is separately inputted to bases of the first transistor and the second transistor. A 12V system voltage and the 5V standby voltage are respectively inputted to collectors of the first transistor and the second transistor. A second terminal is connected between the drain of the first MOSFET and the drain of the second MOSFET.

Abstract: A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.