Abstract: Systems and method for detecting potentially harmful harmonic and direct current signals at a transformer are disclosed. One such system includes a plurality of detection components electrically connected to electrical signal lines leading from one or more connection points on a power grid, and a plurality of threshold detectors, each threshold detector configured to compare an incoming signal from a detection component to a predetermined signal having a threshold. The system also includes a controller receiving an output from each of the plurality of threshold detectors and configured to drive at least one external component in response to receiving an indication from at least one of the plurality of threshold detectors of a detected signal above a threshold.

Abstract: The multi-pulse frequency shifted technique uses mutually orthogonal short duration pulses o transmit and receive information in a UWB multiuser communication system. The multiuser system uses the same pulse shape with different frequencies for the reference and data for each user. Different users have a different pulse shape (mutually orthogonal to each other) and different transmit and reference frequencies. At the receiver, the reference pulse is frequency shifted to match the data pulse and a correlation scheme followed by a hard decision block detects the data.

Abstract: A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has a plurality of non-adaptive and adaptive filter taps with weighted coefficients and a input and output normalizing circuit that obtain sample values from a received signal input to or output from the adaptive filter to increase gain recovery based on type of modulation of encoded communication data, on state of demodulator (preamble search, preamble detected, data state) or other signal acquisition information. A demodulator and decoder receive the filtered output signal and demodulate and decode the signal to obtain the communications data.

Abstract: A system includes a first powered apparatus having a first analog signal with a fundamental frequency; and a second apparatus providing load diagnostics or power quality assessment of the first apparatus from a second digital signal. The second apparatus includes an input of the first analog signal, an output of the second digital signal, a processor, an adaptive filter executed by the processor, a digital-to-analog converter, and an analog-to-digital converter. The adaptive filter routine outputs a third digital signal as a function of the second digital signal and plural adaptive weights. The digital-to-analog converter inputs the third digital signal and outputs a fourth analog signal representative of an estimate of a fundamental frequency component of the first analog signal. The analog-to-digital converter inputs a difference between the first and fourth analog signals, and outputs the second digital signal representative of the first analog signal with the fundamental frequency component removed.

Abstract: A charge domain filter circuit includes a first signal output portion, a second signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. The second signal output portion outputs a second signal that is sampled at the same time interval as the first signal and at a different time. The adder portion adds the first signal and the second signal together and outputs the result. The second signal output portion is capable of selecting the time to sample the second signal from among a plurality of times.

Abstract: A signal filter includes a node, a first terminal, a second terminal, and energy storage circuitry coupled to the node and the first and second terminals. The node receives an input signal and a reference signal selectively. The first terminal provides an output signal determined by the input signal and the reference signal. The second terminal receives a feedback signal indicative of the output signal. The energy storage circuitry generates the output signal at the first terminal according to the input signal and the reference signal. The energy storage circuitry also receives the input signal via the node and the feedback signal via the second terminal in alternating fashion. A dominant pole of the signal filter is controlled by the frequency at which the input signal and the feedback signal alternate.

Abstract: Technologies are described herein for mitigating the effects of single event effects or upsets on digital semiconductor device data paths and clocks utilizing an adaptive temporal filter. The adaptive temporal filter includes a master delay line and a slave delay line to generate two output clock signals that remain unaffected by variations in process, voltage and temperature (PVT) conditions. The adaptive temporal filter supplies the three independent clock signals having a programmable phase relationship, to a triple voting register structure for storing and outputting an uncorrupted data value using a majority voter.

Abstract: The present invention is related to a digital circuit for use in a mixed-signal circuit.

Abstract: A method and apparatus for cancelling interference in received signals are disclosed. A receiver includes a knowledge-based interference cancellation unit, a blind interference cancellation unit and a trade-off management unit. The knowledge-based interference cancellation unit cancels interference in the received signals based on pre-known knowledge and the blind interference cancellation unit cancels interference in the received signals without the pre-known knowledge. The trade-off management unit determines a trade-off between knowledge-based interference cancellation and blind interference cancellation, whereby at least one of the knowledge-based interference cancellation and the blind interference cancellation is selectively preformed based on the trade-off. The interference cancellation may be performed by implementing at least one of a successive interference cancellation (SIC), a principal component analysis (PCA) and an independent component analysis (ICA).

Abstract: Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.

Abstract: An apparatus for processing signals, in particular physiological measuring signals, wherein the apparatus is provided with different channels with signal inputs (1) for receiving input signals, which input signals each comprise a specific signal component and a signal component common to all input signals, wherein each channel is provided with an impedance transforming input amplifier (3), wherein the apparatus is configured for supplying to the non-inverting input of each input amplifier (3) a respective input signal and, to the inverting input an analogue reference signal common to all channels, wherein the apparatus is provided with a digital signal processor (10) and one more or analogue-digital converters (5) for supplying the signals provided by the input amplifiers (3) to the digital signal processor (10), wherein the signal processor (10) is designed for converting the signals received from the one or more analogue digital converters (5) into one or more output signals.

Abstract: Exemplary embodiments of the present disclosure provide a method and controller for damping multimode electromagnetic oscillations in electric power systems which interconnect a plurality of generators and consumers. The controller for damping such oscillations includes a phasor measurement unit (PMU) and a power oscillation damper (POD) controller. Each oscillating mode signal is damped and then superposed to derive a control signal. A feedback controller is used to feedback the control signal to a power flow control device in the power system.

Abstract: Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract: Provided is a signal processing method which reduces a plurality of echoes by receiving a plurality of reception signals and subtracting a pseudo echo generated by a plurality of adaptive filters which input the reception signals from a plurality of echoes generated by the reception signals. At least one of the reception signals is delayed to generate a delayed reception signal. The reception signal and the delayed reception signal are inputted to the adaptive filters to generate a pseudo echo. The frequency of inputting the reception signal and the delayed reception signal to the adaptive filters is controlled in accordance with the sensitivity of a localization change of the reception signals.

Abstract: A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom.

Abstract: A sensor, a sensing method of the sensor, and a filter of the sensor are provided. The sensor includes a sensing data output unit configured to output sensing data that varies depending on touch or proximity of an object, and a determiner configured to compare a threshold value with the sensing data to recognize touch or proximity, vary a first strength value indicating the sensing data in a state of no touch or no proximity and a second strength value indicating the sensing data in a state of touch or proximity, vary the threshold value using the first and second strength values, and output an output signal indicating touch or proximity.

Abstract: Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal.

Abstract: An acoustic characteristic control apparatus supplies music signal, for example, to input terminal connected to a band-pass filter and a peaking filter. In a zero-cross detection circuit, a pulse signal corresponding to a period while a signal is positive is formed. A pulse-width measuring circuit output a signal corresponding to a pulse width. Next, the output of the pulse-width measuring circuit is inputted to one comparator and another comparator. The one comparator discriminates a time when the pulse width is equal to or larger than a first setting value, and the another comparator discriminates a time when the pulse width is equal to or smaller than a second setting value. The comparator is connected to the up terminal and the down terminal of an up/down counter. The output of the up/down counter is connected to the peaking filter through the subtractor, and acoustic characteristics of the peaking filter is controlled according to the count value of the up/down counter.

Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.

Abstract: A power circuit and method thereof are provided. The power circuit includes an output circuit having an alternating current-coupling element and that supplies an output signal of the output circuit to an amplifier as a driving voltage. The power circuit includes an envelope signal-extracting unit extracting an envelope signal from a carrier wave, a simulation signal-waveform generating unit generating a simulation signal including a fluctuation component occurring when the envelope signal is transmitted to the output circuit, a fluctuation component-extracting unit extracting the fluctuation component included in the simulation signal, and an inverted component-generating unit generating an inverted component obtained by performing phase inversion for the fluctuation component, where the fluctuation component occurring in the output circuit is canceled out through the inverted component.

Abstract: A filtering module filters out high frequency signals, primarily noise, from an input data stream. The filtering module includes an input module, a phase detecting module, and a threshold module. The input module performs either a charging or a discharging across a capacitor on a basis of an RC time constant. The phase detecting module is coupled to the input module to keep identical phase at a first node and an output node. The threshold module is coupled to the phase detecting module for providing an output signal based on a threshold voltage and the charging or the discharging across the capacitor.

Abstract: A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.

Abstract: A noise reduction circuit includes first and second reset signal generation circuits that generate first and second reset signals that are activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high level or a low level is maintained, and first and second counter circuits that count an inverted signal of the clock signal, and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit that includes a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock, wherein the selector circuit selects and outputs any of: a signal fixed at a high level or a low level, and an output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output.

Abstract: A semiconductor device interconnecting unit configured to input/output a high-frequency signal having a millimeter wave band to/from a semiconductor device is provided. The semiconductor or device interconnecting unit includes a part of a band pass filter configured to pass therethrough the high-frequency signal having a millimeter wave band by using an LC resonance circuit, and a remainder of the band pass filter, wherein the part and the remainder are separated from each other. The part is provided inside the semiconductor device, and the remainder is provided outside the semiconductor device. The part and the remainder include capacitors having variable capacitors added thereto, respectively. A pass band for the high-frequency signal having a millimeter wave band is changed by changing capacitance values of the variable capacitors.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract: The present invention discloses a power converter with low standby power consumption, used to convert an AC input power to an output DC power, comprising: an EMI filter, coupled to the AC input power to filter the EMI; a TRIAC, coupled to the EMI filter to access the AC input power; and a TRIAC driver, used for driving the gate of the TRIAC switch according to an on-off control signal from a loading device, to control the conduction of the TRIAC switch.

Abstract: A transceiver mitigates signal leakage into a receive path from a transmit path. A subtraction circuit determines a difference between a receive signal and a compensation signal to produce a compensated receive signal prior to demodulation by a demodulator. An equalizer both amplitude adjusts and phase adjusts orthogonal baseband transmit signals based on the difference from the subtraction circuit to produce the compensation signal. A digital tuning circuit determines at least one amplitude adjust coefficient to be used by the equalizer. The equalizer can have a polarity switch or a variable attenuator or a variable delay.

Abstract: The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular. This signal reproducing device (1) includes: N FETs (61 to 6N) each receiving a common input signal (VIN) at a gate terminal and having a bias voltage (VDD) applied to a drain terminal; and an adder circuit (4) connected to source terminals of the FETs (61 to 6N), for combining currents between the drain terminals and the source terminals of the FETs (61 to 6N) and outputting the resulting current, wherein the FETs (61 to 6N) and the bias voltage (VDD) are set so that a voltage at the gate terminal having the common input signal (VIN) applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the FETs (61 to 6N).

Abstract: The present invention discloses a method for the removal of power line interference (PLI) to the signal parts of which are abrupt. First, to the non-abrupt part of the original input signal, we pass it to the notch filter, and get the output as the system output. Then, to the abrupt part, we subtract previous output from the original input signal; and add a straight line, connecting the starting and end of previous output, to the result of the subtraction to get the input of the notch filter. After processing of the notch filter, we add previous output to current output of the notch filter; and subtract the straight line as before from the sum to get the output of this step. We repeat this processing several times. During the detection of electrocardiogram (ECG), 50/60 Hz power line interference conceals the subtle changes in the original ECG, which affects the diagnosis.

Abstract: The Simple Noise Control Method is a method used to eliminate all noise from a pulsed signal. By subjecting the pulsed signal to a band pass filter and duration filter based on simple, low cost and widely available timers, counters and logic gates or equivalents, any noise in the pulsed signal which have different frequencies or durations than the signal can be removed with very high certainty.

Abstract: One embodiment of the present invention comprises a mass flow controller. The mass flow controller may comprise a pair of thermal sensing elements, a bridge circuit adapted to receive at least one first signal from the pair of thermal sensing elements and a differential amplifier adapted to (i) receive at least one bridge signal from the bridge circuit, and (ii) emit an output signal generally proportional to a flow rate of fluid passing through the mass flow controller. The mass flow controller is also comprised in one embodiment of a filter portion of a control module having one or more first filters comprising substantially permanent parameters adapted to provide a more accurate output signal for a baseline fluid upon a change in the flow rate and one or more second filters comprising variable parameters, with each of the one or more second filters being adapted to provide a more accurate output signal for non-baseline fluids upon a change in the flow rate.

Abstract: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

Abstract: According to an embodiment of the present invention, an insulating communication circuit includes a first insulating circuit 62#11 having first and second circuits, a second insulating circuit 62#12 having third and fourth circuits, and a communication interface that is connected to a first ground and transmits a signal to the first circuit based on a communication signal and a clock signal from an external control device.

Abstract: There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.

Abstract: The invention relates to a method for processing of a signal (s), wherein desired data (d(f(N))) are received via a desired channel (N) of a plurality of frequency channels (N?2, N?1, N, N+1, N+2) and unwanted data (d(f(N?2)), d(f(N?1)), d(f(N+1)), d(f(N+2))) can be received on a neighboring channel (N?2, N?1, N+1, N+2) and wherein the signal (s) is sampled with a sampling frequency (fa) to avoid aliasing of the desired channel (N) in order to create digital data (do), wherein the sampling frequency (fa=2f(N?1, N, N+1)) is set high enough for aliasing-free sampling of the desired channel (N) and at least one of the neighboring channels (N?1, N+1).

Abstract: A semiconductor device includes: a noise detecting circuit; an input signal delaying circuit; and a mask circuit. The noise detecting circuit detects noise superimposed on an input signal and outputs a mask signal during a predetermined time period. The input signal delaying circuit delays the input signal and outputs a delay signal thereof. The mask circuit outputs an output signal in which the delay signal is masked based on the mask signal.

Abstract: A filter circuit enhances a deficient Q-value in a filter stage and buffers the filter stage from subsequent filter stages using a common active device. A filter circuit includes a first buffered filtering stage including a first Q-deficient filter stage to receive an input signal and a first Q-enhancement buffer stage. The first Q-enhancement buffer stage is coupled to the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage. A filtering method includes filtering an input signal in a first Q-deficient filter stage and enhancing a deficient Q-value of the first Q-deficient filter stage with an active device. The method further includes buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.

Abstract: An active snubber operates, in part, to compel switching components, such as switch-mode power supplies and converters, to attain desired values rapidly, albeit temporarily, during which time there is sufficient time for a power supply's internal regulation system to sustain these values independently. The invention can dampen ringing, accelerate response time, and correct erroneous responses of the output of the switching converter. In one embodiment, the active snubber, which is operably connected to the output of a switching component that has a switching or ringing frequency, f1, and that is modulated by a signal generator at a frequency, f2, is characterized by an operable connection to the output of a buffer connected to the signal generator. The buffer provides a reference voltage that is equal to the switching component output voltage at the modulation frequency at f2.

Abstract: A device for filtering a signal delivered as output from a sensor installed in a motor vehicle includes a comparator (A) offering as output a first logic signal (SA) representative of the positive and negative transitions of the output signal (SM) from the sensor, a clock (G) delivering a signal (SG) serving as time base for the whole device, elements (E, D, F) making it possible to fix a filtering time (TFilt) of the output signal (SM) from the sensor, a suppression block (B) receiving as input the first logic signal (SA) and delivering as output a second logic signal (Sb) whose duration of holding (tn) in a logic state depends on the filtering time (TFilt), and a control block (C) managing the set of the signals of the device, and having as input signals the first and second logic signals (SA, Sb).

Abstract: A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.

Abstract: An input signal processing system is described. It comprises a first transconductance device having a first input, second input, and an output, wherein the first input is coupled to receive the input signal; a first resistor coupled to a first input of the first transconductance device, wherein the first resistor converts the input current signal to an input voltage signal; a first voltage-current converter coupled to the output, the second input, the resistor, and a low voltage supply, wherein the first voltage-current converter is operative for converting the input voltage signal to a input current signal; and a low pass filter having an input coupled to the voltage converter for filtering noise from the input current signal.

Abstract: An embodiment is directed to a zero IF down converter circuit. The circuit comprises a voltage-to-current converter, a mixer, and a suppression circuit. The voltage-to-current converter converts an RF voltage signal to an RF current signal. The mixer changes the frequency of the current signal to a lower frequency current signal. The suppression circuit removes a lower frequency distortion component from the RF current signal before sending the RF current signal to the mixer.