Abstract: A signal analysis control system is provided with a signal analyzing section for analyzing signals inputted to a transmission section and generating analysis information, and a signal control section for controlling signals inputted to a receiving section by using the analysis information.

Abstract: A deglitch circuit including signal transmission units is provided. The signal transmission units are connected in serial to form a signal transmission unit string, and a first signal transmission unit of the signal transmission unit string receives a digital signal. Each signal transmission unit includes a first switch, a first delay circuit and a second switch. First and second terminals of the first switch are coupled to a previous signal transmission unit of the signal transmission unit string and an input terminal of the first delay circuit, respectively. The second switch is coupled between an output terminal of the first delay circuit and a first voltage. When the digital signal has a first logic state, the first switch is turned off, and the second switch is turned on. When the digital signal has a second logic state, the first switch is turned on, and the second switch is turned off.

Abstract: Systems and methods for filtering analog signals corresponding to sensed parameters are provided. In this regard, a representative method includes: sampling the analog signal to acquire a sequential series of data points; determining a first cumulative change in value with respect to a first of the data points relative to at least two subsequent data points in the series, the subsequent data points including a second of the data points; determining a second cumulative change in value with respect to the second of the data points relative to at least two data points adjacent to the second of the data points in the series, the at least two adjacent data points including an immediately preceding and an immediately succeeding one of the data points relative to the second of the data points; comparing the first cumulative change and the second cumulative change to respective data thresholds; and outputting a filtered analog signal based, at least in part, on results of the comparing.

Abstract: A device (110) includes a sensing element (26) having drive nodes (34, 36) and sense nodes (42, 44). Parasitic capacitance (22) is present between drive node (34) and sense node (42). Likewise, parasitic capacitance (24) is present between drive node (36) and sense node (44). When a drive signal (56) is applied between drive nodes (34, 36), a parasitic current (70) between drive and sense nodes (34, 42) and a parasitic current (72) between drive and sense nodes (36,44) is created due to the parasitic capacitances (22, 24). A capacitive network (112) is coupled between the drive node (36) and the sense node (42) to create a correction current (134) through capacitive network (112) that cancels parasitic current (70). Likewise, a capacitive network (114) is coupled between the drive node (34) and the sense node (44) to create a correction current (138) through capacitive network (112) that cancels parasitic current (72).

Abstract: A method of suppressing noise in a circuit is disclosed. The method comprises providing a supply voltage to a first terminal of the circuit; providing a ground voltage to a second terminal of the circuit; providing a clock signal to the circuit; and actively decoupling noise from at least one of the first terminal and the second terminal of the circuit by actively decoupling noise synchronously with the clock signal. A circuit for suppressing noise in a circuit is also disclosed.

Abstract: The present invention includes: a main voltage detection unit for detecting a voltage applied between main electrodes of an electrical power switching element; a control current source for injecting a current into a gate electrode of the electrical power switching element in accordance with the voltage detected by the main voltage detection unit; a main current detection unit for detecting a main current flowing between the main electrodes of the electrical power switching element; and an adjustment unit for adjusting a current of the control power source in accordance with the main current detected by the main current detection unit.

Abstract: A method for reducing low frequency noise of a transistor operable at cryogenic temperatures includes a first step in which the transistor is illuminated with a light in a state that the transistor is activated and flowed current by supplying a power at a predetermined temperature, and a second step in which the transistor is operated at the predetermined temperature after the illumination of the light.

Abstract: A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.

Abstract: Methods and apparatus (100) for composing, generating and transmitting information-bearing optical signals are provided. An information-bearing electrical signal is composed (108) having desirable spectral properties, preferably configured to ensure that undesired interference between electrical spectral components generated in a square-law direct detection process (120) at a corresponding optical receiver (104) is substantially avoided. Predistortion (110) is advantageously applied to transmitted signals, in order to account for a nonlinear relationship arising in a modulation process (114) between electrical signal amplitude and corresponding optical field amplitude. Orthogonal frequency division multiplexing (OFDM) techniques may be applied to composed signals having the desired characteristics, and additionally may facilitate the application of frequency domain equalisation (128) in order to mitigate transmission impairments, including dispersion.

Abstract: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

Abstract: A mechanism is provided for a one card to filter false signals due to a another card being hot-plugged. A discriminator circuit in the card receives a low-state signal via an input and, responsive to receiving the low-state signal, the discriminator circuit compares the low-state signal to a static signal. Responsive to the low-state signal being greater than the static signal, the discriminator circuit outputs a high-voltage signal. The high-voltage signal output by the discriminator circuit indicates that the low-state signal is a false low signal. Responsive to the low-state signal being less than or equal to the static signal, the discriminator circuit outputs a low-voltage signal. The low-voltage signal output by the discriminator circuit indicates that the low-state signal is a valid low signal.

Abstract: A noise suppression device includes: conversion means which converts an input signal into a frequency region signal for each predetermined first frame; frame generation means which generates a second frame which is different from the first frame; representative frequency region signal generation means which generates a representative frequency region signal from the frequency region signal of the first frame contained in the second frame; and noise suppression degree calculation means which obtains a noise suppression degree of the second frame according to the representative frequency region signal.

Abstract: A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal.

Abstract: Spurious noise that occurs in the vicinity of a carrier can be removed even when a high-resolution cycle is set, thereby realizing low jitters in a high-precision variable clock signal. Cycle data that is set by a pattern generator in a waveform generation apparatus (a semiconductor test apparatus) is corrected in such a manner that spurious noise that occurs in a carrier of a high-precision variable clock is produced at a position far from the carrier in terms of frequency. As a result, the spurious noise can be assuredly removed by a phase-locked loop circuit, thereby realizing low jitters in the high-precision variable clock signal.

Abstract: A method of capturing user control inputs for an electronic device comprises sampling an input measurement signal at a capacitive input sensor of the electronic device to capture user control inputs for operating the electronic device. Electromagnetic interference affecting the sampling or the input measurement signal is electronically neutralized.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Abstract: A sampling filter of such circuitry as not requiring a high frequency REF signal even if the number of decimation is decreased. In the sampling filter, the rotate capacitor in each switched capacitor circuit including Cr (7a-7d) arranged in four parallel arrays operates in four phases of integration, discharge, reset and feedback different from each other at the same timing. Consequently, a control signal for driving the switched capacitor circuit is used commonly. As a result, the circuit scale of a DCU (104) is reduced and the frequency of the REF signal can be lowered to the frequency of an LO signal even in operation without decimation.

Abstract: A semiconductor integrated circuit device provided with an input terminal supplied with a reference frequency signal from outside of the device, a bandpass filter circuit coupled to the input terminal and outputting an internal reference frequency signal and a PLL circuit coupled to the bandpass filter circuit to receive the internal reference frequency signal. The input terminal is supplied with the reference frequency signal generated by a quartz oscillator or the like mounted on the exterior of the semiconductor integrated circuit device. In response to the signal supplied to the input terminal, the bandpass filter circuit restricts components in a bandwidth except for the frequency of the reference frequency signal, and thus supplies the reference signal to the PLL circuit. The PLL circuit operates by using the reference frequency signal as the reference signal.

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Abstract: A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal.

Abstract: An electromagnetic-wave suppression structure in a multilayer PCB or package structure is supplied with a power to be used therein by a power distribution network including a power plane and a ground plane. The multilayer PCB and package includes: an electromagnetic-wave suppression structure including an electromagnetic band-gap; and the electromagnetic-wave suppression structure is formed at a specific portion(s) of the power plane and/or the ground plane to suppress noises.

Abstract: An arrangement for reducing interference between circuit blocks having differences in the amount of input power and phase differences includes isolation wires located between the circuit blocks and connected to a ground.

Abstract: In a semiconductor device, a monitoring circuit monitors and detects a quantity of noise in the semiconductor device. A control circuit has capacitances and controls connections to the capacitances such a decoupling capacitance value provided between a first power supply and a second power supply is dynamically adjusted based on the detected noise quantity.

Abstract: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

Abstract: A semiconductor device includes a layered region (104) formed in a semiconductor substrate (101) of a first conductivity type, and an electrode pad (106) formed on the semiconductor substrate with an interlayer insulating film (105) interposed therebetween and placed above the layered region. The layered region includes a first impurity diffusion region (102), a second impurity diffusion region (103) formed on the first impurity diffusion region, and a third impurity diffusion region (102x) formed on the first impurity diffusion region and surrounding a periphery of the second impurity diffusion region. a conductivity type of the first impurity diffusion region and a conductivity type of the third impurity diffusion region are a second conductivity type, and a conductivity type of the second impurity diffusion region is the first conductivity type.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a detector configured to detect an abnormal condition of the IC device and to generate a detection result as an attack signal, and a noise filter configured to filter out the attack signal as noise and to generate a filtered attack signal. The noise filter is configured to filter out the attack signal as noise when the attack signal is not maintained at a first logic level for a reference period and to generate the filtered attack signal when the attack signal is maintained at the first logic level for the reference period.

Abstract: A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation.

Abstract: The Present Invention relates to methods and systems particularly useful in electrical products used to monitor and detect very weak signals. These products include, for example, night vision binoculars and remote listening devices. More specifically, the methods and systems of the Present Invention provide a signal conditioning technique that attenuates electrical noise generated within the product while at the same time preserving the integrity of the input signal. This provides a high signal-to-noise ratio within the product electronics and a dramatically clear final image. The Present Invention includes a method and system for chopping or splitting an input signal into two components, tagging each of the split signal components with opposite polarities, and a second reverse chopping step that combines the split and tagged input signal components into a restored input signal.

Abstract: A sampling mixer includes TAs (transconductance amplifiers), an in-phase mixer section connected to the TA and the TA, an opposite-phase mixer section connected in parallel with the in-phase mixer section, and a signal generator for generating a control signal for the in-phase mixer section and the opposite-phase mixer section respectively. The IIR filter using signals that underwent a current conversion by using the different transconductances is constructed, so that the filter characteristic can be designed by a weighting of the transconductance in addition to a capacitance ratio. As a result, the wide-band filter characteristic and the band-pass filter characteristic can be obtained, and deterioration of the receiving sensitivity can be suppressed by designing the filter characteristic suitable for the radio communication system.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A filler circuit cell is disclosed. The filler circuit cell includes a decoupled capacitor, a tie low circuit and a tie high circuit. The decoupled capacitor includes a first NMOS transistor and a first PMOS transistor, in which the source/drain of the first NMOS transistor is connected to a second voltage source and the source/drain of the first PMOS transistor is connected to a first voltage source. The tie low circuit includes a second NMOS transistor and a second PMOS transistor and the tie high circuit includes a third NMOS transistor and a third PMOS transistor.

Abstract: Multiple techniques are disclosed for hardening a self-clocking circuit against glitches. Glitch filters are placed in some portions of a digital design. In some embodiments the glitch filter is dynamically tunable. In one embodiment the inputs are locked out by the outputs. Methods for evaluating code symbols are presented, as is a circuit for differential signaling.

Abstract: An iterative method for generating a series of output signal values from a series of input signal values is described. Iterations of the method comprise the steps of obtaining a current input signal value for the current iteration, comparing the current input signal value with an output signal value determined in a previous iteration, updating a counter value determined in the previous iteration based on the result of the comparison between the current input signal value and the previous output signal value such that the updated counter value replaces the counter value determined in the previous iteration, determining a slew value based on the counter value; and adding the slew value to the previously determined output signal value to generate a new current output signal value. Thus different slew values may be added to the previous output signal to obtain a new output signal. The counter value is updated so that its value reflects recent trends in the input signals. E.g.

Abstract: Systems and methods for filtering analog signals corresponding to sensed parameters are provided. In this regard, a representative method includes: sampling the analog signal to acquire a sequential series of data points; determining a first cumulative change in value with respect to a first of the data points relative to at least two subsequent data points in the series, the subsequent data points including a second of the data points; determining a second cumulative change in value with respect to the second of the data points relative to at least two data points adjacent to the second of the data points in the series, the at least two adjacent data points including an immediately preceding and an immediately succeeding one of the data points relative to the second of the data points; comparing the first cumulative change and the second cumulative change to respective data thresholds; and outputting a filtered analog signal based, at least in part, on results of the comparing.

Abstract: Embodiments of the present invention provide a system that controls noise in a power system that includes a power rail and a ground rail. The system includes a MOS transistor coupled in series with a decoupling capacitor between the power rail and the ground rail and an inductive packaging connection coupled to the power rail in parallel with the MOS transistor and the decoupling capacitor. The combination of MOS transistor, decoupling capacitor, and inductive packaging connection form a resonant circuit. During operation, the system determines if there is noise in a Vdd signal on the power rail. Based on the noise present in the Vdd signal, the system adjusts the impedance of the MOS transistor to reduce the noise in a frequency range near a frequency of interest (?interest) of the resonant circuit without causing an unnecessary increase in switching noise at other frequencies.

Abstract: An automatic gain control circuit and method for stably maintaining received power in a mobile Internet system is disclosed. An efficient automatic gain control circuit structure is provided which uses no separate analog circuit elements in a process of detecting the level of a received signal. Therefore, it is possible to reduce a complexity of hardware, the size of the automatic gain control circuit and a manufacturing cost. Further, an automatic gain control (AGC) unit, which is made in a Fluctuating Gunn-Peterson Approximation (FGPA) type, performs an automatic gain control simply by referring to a lookup table based on the level of a received signal. Therefore, the present automatic gain control circuit can not only be more simply designed or modified than a conventional automatic gain control circuit, but also stabilize the level of the received signal simply without periodically checking the level of the received signal for the automatic gain control.

Abstract: Low flicker noise mixer and buffer. This design employs some native metal oxide semiconductor field-effect transistors (MOSFETs) (e.g., having no threshold voltage) within a passive mixer whose gates are driven using clock signals. These native MOSFETs maybe biased at one half of the power supply voltage to provide a lower noise figure. A cooperatively operating buffer employs appropriately places MOSFETs and resistors to ensure the desired gain. Relatively larger valued resistors can be employed to provide for higher voltage gain, and this can sometimes be accompanied with using a higher than typical power supply voltage. Source followers serve as output buffers and also ensure the required output DC voltage level as well. It is also noted that this design can be implemented using n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) of p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs).

Abstract: A filter system and filtering method includes a subtractor which receives an analog input signal and a reference voltage as a first input, and an analog feedback signal, supplied through a feedback loop, as a second input, and outputs a difference between the analog input signal and the analog feedback signal, and a low pass filter which outputs a digital signal by comparing the output signal of the subtractor and a reference voltage, then integrates duty cycle of the digital signal and calculates a following error amount, and then converts a low pass filtered signal based on the calculated following error amount to an analog signal in order to provide the analog signal to the analog feedback signal, i.e. the second input of the subtractor.

Abstract: A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-dividing function. The proposed frequency divider circuit comprises an injection-locked oscillator (ILO) circuit module and a pair of buffer-stage circuits, wherein the ILO circuit module further includes a signal-injection circuit, a cross-coupled switching circuit, and a variable-capacitance tuning circuit. The proposed circuit architecture is characterized by the circuit arrangement of a direct-injection architecture and an inductive-coupling feedback architecture by coupling the inductive elements of the buffer-stage circuits to the inductive elements of the variable-capacitance tuning circuit in the ILO circuit module.

Abstract: A device and a method for reducing input noise providing at least a microcontroller. The microcontroller comprises: at least a noise reduction device, at least an analog switch and at least a signal output unit. The noise reduction device connected to the ground or a voltage is turned on to charge or discharge a stray capacitor existing on a turned off analog switch so that the amount of charge stored in the stray capacitor is zero or a specific value. Thereby, the noise in a touch switch is reduced and the cost of layout on the PCB is saved.

Abstract: Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions.

Abstract: There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.

Abstract: A wireless communication device is disclosed wherein isolation buffers couple to respective active circuits or stages of the device to convey test information regarding such active circuits to a test data line from which status information may be collected. The communication device operates in two modes, namely a normal operational mode wherein the isolation buffers effectively short spurious emissions from the active circuits to a ground, and a test mode wherein the isolation buffers may convey test information from a selected active circuit to the test data line. The isolation buffers prevent spurious emissions from escaping the active circuits to which they are coupled and prevent spurious emissions from traveling from active circuit to active circuit over the test data line throughout the wireless device.

Abstract: A method for an adjustable leading edge blanking device in a power supply device includes generating a detection signal according to a leading edge and a trailing edge of a spike signal, generating a blanking signal according to the detection signal, for blanking the spike signal between the leading edge and the trailing edge, and controlling output states of the power supply device according to the blanking signal.

Abstract: A signal receiver includes a sampling device for sampling a received signal carrying a stream of symbols to form a first set of actual samples. The signal receiver also includes interpolation means for interpolating between the samples of the first set to form a second set of interpolated samples. The signal receiver also includes symbol recovery means configured to process the first and second sets of samples so as to form an estimate of the symbols of the signal. The processing includes performing a temporal whitening step on signals derived from first and second sets of samples. The signal receiver also includes signal combining means using a matched filter and averaging technique.

Abstract: A transconductor to convert an input voltage to an output current, includes: a primary transconductance stage to provide the output current from the input voltage and a driving current; an adaptive transconductance stage coupled in series with the primary transconductance stage to generate the driving current from the input voltage; and a bias circuit coupled to provide a primary bias voltage to the primary transconductance stage and an adaptive bias voltage to the adaptive transconductance stage.

Abstract: Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.

Abstract: The invention provides a system for providing tunable balanced loss compensation in an electronic filter. Tunable balanced loss compensation is provided by using cross-connected balanced transconductors and self-connected balanced transconductors. The cross-connected balanced transconductors and the self-connected transconductors compensate the unbalanced loss across the electronic filter. The self-connected balanced transconductors compensate the balanced loss across the electronic filter. Further, the cross-connected and the self-connected balanced transconductors are tunable by adjusting the values of their transconductances, thereby providing tunable balanced loss compensation.