Switched Capacitor Filter Patents (Class 327/554)
  • Patent number: 11030951
    Abstract: A light-emitting display includes a display panel, a first circuit, and a second circuit. The display panel comprises a pixel. The first circuit supplies a data voltage to a data line for the pixel. The second circuit performs a sensing operation for sensing a sensing line for the pixel and outputs a voltage required for the sensing operation, and outputs a noise removing voltage for cancelling out noise formed on the sensing line during the sensing operation.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 8, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Changwoo Lee, Jaeik Yoo, Osung Do
  • Patent number: 10938443
    Abstract: A communication system includes a modulator configured to generate a modulated signal responsive to at least a data signal, and a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter configured to generate a filtered first signal based on a first signal, and a gain adjusting circuit coupled to the filter. The first signal is based on the first carrier signal and modulated signal. The filter has a gain controlled by a set of control signals. The gain adjusting circuit is configured to adjust the gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, William Wu Shen, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho
  • Patent number: 10749503
    Abstract: A discrete time filter network with an input signal connection and an output signal connection and comprising a capacitor bank with a plurality of history capacitors, and at least one sampling capacitor which operates at a predetermined cycling rate to couple to at least one history capacitor at a time, which history capacitor is selected from the capacitor bank so as to share electrical charge between such selected history capacitor and the sampling capacitor, wherein there is a plurality of sampling capacitors that are provided in the capacitor bank, and the discrete time filter network is provided with at least one switch network comprising a plurality of clock driven switches for making selected cyclical connections between the sampling capacitors and the history capacitors in the capacitor bank at the predetermined cycling rate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 18, 2020
    Assignee: QUALINX B.V.
    Inventors: Iman Madadi, Massoud Tohidian, Seyed Amir Reza Ahmadi Mehr
  • Patent number: 10720919
    Abstract: Apparatus and methods for reducing charge injection mismatch are provided herein. In certain implementations, an electronic circuit includes one or more switch banks. Each switch bank can include a selection circuit and a plurality of switches that can be controlled using one or more clock signals. The selection circuit can select a first portion of the switches for operation in a first switch group and a second portion of the switches for operation in a second switch group. During a calibration, the electronic circuit's charge injection mismatch can be directly or indirectly observed for different switch configurations of the switch banks. The electronic circuit can be programmed to operate with the selected switch configurations of the switch banks to provide the electronic circuit with small charge injection mismatch.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: July 21, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Jie Zhou, Arthur J. Kalb
  • Patent number: 10715114
    Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 14, 2020
    Assignee: uPI Semiconductor Corp.
    Inventors: Chao-Chung Huang, Kuo-Jen Kuo, Yi-Xian Jan
  • Patent number: 10644675
    Abstract: A stacked switched resistance device has been developed. The stacked switched resistance device includes a plurality of segments connected in series. Each segment includes a resistor including an inherent parasitic capacitance, and a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal. An effective resistance of the stacked switched resistance device exceeds another effective resistance of at least one resistor with an equivalent inherent resistance that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 5, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Saikrishna Ganta, Man-Chia Chen, Chinwuba Ezekwe
  • Patent number: 10554255
    Abstract: A communication system includes a demodulator configured to demodulate an amplified modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal. The first signal is based on the first carrier signal and the amplified modulated signal. The filter has a gain adjusted based on a set of control signals. The gain adjusting circuit is coupled to the filter, and configured to generate the set of control signals based on at least a voltage of the filtered first signal or a voltage of a second signal. The gain adjusting circuit includes a first peak detector configured to output a peak value of the voltage of the second signal. The voltage of the second signal includes a voltage of the first signal or a voltage of a reference signal.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, William Wu Shen, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho
  • Patent number: 10439572
    Abstract: An “all-digital” operational amplifier architecture, that does not have the constraint of maintaining devices in their saturation region, can leverage the high speed achievable by deeply scaled technology to replace traditional linear current referenced continuous-time operational amplifier circuits with CMOS-like dynamic circuits that require no referencing structure, have no static power consumption, and are compatible with ultra-low supply voltages. Techniques are described to replace analog continuous-time linear operational amplifier input and output stages by a discrete-time comparator circuit, e.g., CMOS-style, and a switched capacitor charge pump circuit, respectively.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 8, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Frederick Carnegie Thompson, Riccardo Tonietto
  • Patent number: 10395070
    Abstract: A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Eleazar Walter Kenyon
  • Patent number: 10389340
    Abstract: A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: August 20, 2019
    Assignee: HITACHI, LTD.
    Inventor: Tatsuo Nakagawa
  • Patent number: 10205400
    Abstract: SSC energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network may operate at a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range. Improvements in SSC energy buffer circuits include, in various implementations, the use of ground reference gate drive, the elimination of a separate precharge circuit through control of at least a portion of the switches of the SSC energy buffer circuit, and/or optimized ratio of capacitance values of two or more capacitors in an SSC energy buffer circuit.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 12, 2019
    Assignees: The Regents of the University of Colorado, a body corporated, Massachusetts Institute of Technology
    Inventors: Khurram K. Afridi, Yu Ni, Minjie Chen, Curtis Serrano, Benjamin Montgomery, David Perreault, Saad Pervaiz
  • Patent number: 10153751
    Abstract: A switched capacitor low-pass filter. The filter includes a plurality of switched capacitors, and a plurality of resistors. The resistors increase the slope of the roll-off of the filter, reduce DC gain variations across corners, and minimize the frequency variation across corners. In some embodiments, the clock signal used to control the switched capacitor filters has a duty cycle differing from 50%, to improve the frequency response of the filter.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nancy Rasti
  • Patent number: 10090209
    Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Amit A. Dikshit, Tamilmani Ethirajan, Shrinivas J. Pandharpure, Vaidyanathan T. Subramanian, Josef S. Watts
  • Patent number: 9973081
    Abstract: A switched-capacitor voltage divider is provided that functions to divide an input voltage only while a low-duty-cycle clock pulse signal is asserted. All the switches in the switched-capacitor voltage divider are idle during an off time for the low-duty-cycle clock pulse signal.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: May 15, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Wenjing Yin, Xuhao Huang, Sungmin Ock
  • Patent number: 9847772
    Abstract: Certain aspects of the present disclosure provide N-path filters with wider passbands and steeper rejection than conventional N-path filters with only a single pole in each filter path. These N-path filters also have a flatter passband with decreased passband droop. One example N-path filter generally includes a plurality of branches selectively connected with a common node, each branch of the N-path filter comprising a switch connected in series with an impedance comprising a common drain amplifier circuit. In certain aspects, the amplifier circuit may include a degeneration circuit for stability and/or a poly-phase feedback circuit to reduce in-band peaking.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: December 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Milad Darvishi, Hajir Hedayati, Faramarz Sabouri
  • Patent number: 9800217
    Abstract: Technologies are described to DC-couple an integrated amplifier system to a source that provides a signal with an unknown DC component, for example to DC-couple an integrated audio codec to an analog microphone. In one aspect, methods include receiving, by an amplifier, a signal having an unknown DC component, and issuing an amplified signal; low pass filtering, with respect to a cutoff frequency, by a feedback circuit coupled between an output of the amplifier and an input of the amplifier, the amplified signal issued at the output of the amplifier to generate a filtered signal having frequencies lower than the cutoff frequency; and injecting, by the feedback circuit, the filtered signal into the input of the amplifier to cancel the unknown DC component below the cutoff frequency.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 24, 2017
    Assignee: Marvell International Ltd.
    Inventors: Gabriele Gandolfi, Vittorio Colonna, Francesco Rezzi
  • Patent number: 9704763
    Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Amit A. Dikshit, Tamilmani Ethirajan, Shrinivas J. Pandharpure, Vaidyanathan T. Subramanian, Josef S. Watts
  • Patent number: 9698759
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: July 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 9535441
    Abstract: A power supply efficiently suppresses transient voltages by storing the maximum charge expected in the transient and releasing it during the transient event at a rate in an equal but opposite amount to the transient, preventing the battery voltage from collapsing. The described power supply provides improved efficiency compared to conventional architectures for transient suppression, thus increasing the length of time between battery charges and creating a better user experience.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 3, 2017
    Assignee: QUANTANCE, INC.
    Inventors: Vikas Vinayak, Serge Francois Drogi
  • Patent number: 9397651
    Abstract: A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: July 19, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Janet M. Brunsilius, Stephen R. Kosic, Corey D. Petersen
  • Patent number: 9385672
    Abstract: A common-mode feedback module is disclosed for controlling feedback in an amplifier, such as a multi-stage amplifier. The common-mode feedback module may include a feedback input stage, a cascode stage, and a feedback output stage. The common-mode feedback module may provide feedback, such as negative feedback to the amplifier to extend a bandwidth of a frequency response and/or increase stability.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Rahul Karmaker
  • Patent number: 9356565
    Abstract: Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 31, 2016
    Assignee: Omni Design Technologies Inc.
    Inventor: Hae-Seung Lee
  • Patent number: 9160308
    Abstract: A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 13, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Eric Nestler
  • Patent number: 9154344
    Abstract: A charge-domain filter (CDF) apparatus and an operation method thereof are provided. The CDF apparatus includes an input-signal combination network (ISCN), a switch-capacitor network (SCN) module, an output-signal combination network (OSCN), and a bandwidth compensation network (BCN). The input terminal of the ISCN receives an input signal. The SCN module is connected between the ISCN and the OSCN. The OSCN outputs an output signal of the CDF apparatus. The BCN senses the signal of the SCN module, senses the signal of the OSCN, or senses the signal of each of the SCN module and the OSCN, and correspondingly generates a forward signal or a feedback signal for the ISCN or the OSCN according to the sensing result to perform bandwidth compensation.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: October 6, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Ming-Feng Huang
  • Patent number: 9116164
    Abstract: A pseudo-differential accelerometer resistant to EMI is disclosed that includes a device with a sensor core connected to an integrated circuit including a chopper, differential amplifier, and dummy core. The chopper swaps input to output connections during different states. The dummy core is coupled to a dummy chopper input. Three bond wires coupling the sensor output to a sensor chopper input, a first chopper output to a first sensor input, and a second chopper output to a second sensor input can connect the sensor and integrated circuit. The device can include a dummy pad and dummy bond wire connecting the dummy pad to the dummy chopper input. This configuration requires four bond wires connecting the sensor and integrated circuit. A neutralization core can be connected to the sensor chopper input. The chopper can change states to smear noise across a wide range, or away from a band of interest.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 25, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ganesh Balachandran, Vladimir Petkov
  • Patent number: 9093982
    Abstract: A sampling circuit is provided that includes a first sampling circuit that shifts a frequency, at which a gain of a frequency characteristic is maximized, to a lower frequency side, and a second sampling circuit that shifts the frequency, at which the gain of the frequency characteristic is maximized, to a higher frequency side. The sampling circuit also includes an output section provided in an output side of the first sampling circuit and an output side of the second sampling circuit, and outputs a sum or a difference between an output from the first sampling circuit and an output from the second sampling circuit.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: July 28, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Yohei Morishita, Noriaki Saito
  • Patent number: 9069995
    Abstract: Fixed capacitive circuits are described which perform arithmetical summation operations over sets of scaled analog values, where the constant parameters of the summations and scaling multiplications are formed as ratios of circuit element values. The passive nature of the design can enable efficient integrated circuit implementation.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: June 30, 2015
    Assignee: KANDOU LABS, S.A.
    Inventor: Harm Cronie
  • Patent number: 9024684
    Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Song, Nan Chen
  • Patent number: 9024700
    Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF? terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 5, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 9013233
    Abstract: In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: April 21, 2015
    Assignee: Si-Ware Systems
    Inventors: Ahmed Elmallah, Ahmed Elshennawy, Ahmed Shaban, Botros George, Mostafa Elmala, Ayman Ismail, Mostafa Sakr, Ahmed Mokhtar, Ayman Elsayed
  • Patent number: 9000839
    Abstract: An integrated continuous-time active-RC filter comprises a set of opamp integrators with Operational Transconductance Amplifiers (OTAs), and at least one assistant transconductor connected between an input and an output of each of the integrators of the set; wherein the assistant transconductor comprises a plurality of sets of MOSFETS connected in parallel to each other wherein each set of MOSFETS is formed by a pair of MOSFETs connected in series, with one MOSFET of the pair operating in the triode region and the other MOSFET of the pair operating in the saturation region; and wherein the assistant transconductor is configured to inject an assistant current into the output of each of the integrators in the set to enhance the linearity and speed of the opamp integrators of the set.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 7, 2015
    Assignees: The Secretary, Department of Information and Technology, Indian Institute of Technology, Madras
    Inventors: Shanthi Pavan Yendluri, Siva Viswanathan Thyagarajan
  • Patent number: 9000969
    Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Rofougaran
  • Patent number: 8981978
    Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shiro Dosho, Kazuo Matsukawa, Yosuke Mitani
  • Publication number: 20150048881
    Abstract: A noise-removing circuit includes a first capacitor to charge a first voltage supplied to a first node during a first period in which a first switching control signal is supplied, a second capacitor to charge a second voltage supplied to a third node during the first period, a third capacitor to charge the first voltage during a second period in which a second switching control signal is supplied, and to charge the second voltage charged in the second capacitor as a third voltage during a third period in which a third switching control signal is supplied, a fourth capacitor to charge the second voltage during the second period, and to charge the first voltage charged in the first capacitor as a fourth voltage during the third period, and a differential amplifier to output a voltage difference between the third voltage and the fourth voltage.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 19, 2015
    Inventors: Oh-Jo Kwon, Boo-Dong Kwak, Choong-Sun Shin, Hee-Sun Ahn
  • Patent number: 8952748
    Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 10, 2015
    Assignee: FutureWei Technologies, Inc.
    Inventors: Homero Guimaraes, Matthew Richard Miller
  • Patent number: 8937506
    Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements or devices providing for adjustable impedances is described. An input signal is sampled in round robin fashion by a plurality of sample and hold devices. The outputs of the sample and hold devices are connected to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter. The impedance devices in each set are connected to the sample and hold devices in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the sampling circuits contains a new sample of the input signal. Switches connect the sets of impedance devices to an output, only one switch being closed at a time to provide the output signal.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 20, 2015
    Assignee: ESS Technology, Inc.
    Inventor: A. Martin Mallinson
  • Patent number: 8901994
    Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 2, 2014
    Assignee: Intel Coproration
    Inventor: Yongping Fan
  • Publication number: 20140320215
    Abstract: An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Robert Bogdan Staszewski, Masoud Babaie, Zhuobiao He
  • Patent number: 8866532
    Abstract: In accordance with an embodiment, a passive integrator includes a charge storage element coupled between first and second transistors, wherein the first transistor has a current carrying electrode coupled for receiving a signal and a current carrying electrode coupled to the charge storage element. The second transistor has a current carrying electrode coupled to the charge storage element and a second current carrying electrode coupled to another charge storage element.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: October 21, 2014
    Inventor: Yannick De Wit
  • Patent number: 8860492
    Abstract: A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: October 14, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Che Yang
  • Patent number: 8841962
    Abstract: Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Linear Technology Corporation
    Inventor: Gerd Trampitsch
  • Patent number: 8836417
    Abstract: A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Industrial Technology Research Institute
    Inventor: Ming-Feng Huang
  • Patent number: 8836416
    Abstract: Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Jianxun Fan, Robert C. Glenn
  • Patent number: 8836378
    Abstract: Provided is a direct sampling circuit in which signal mixing between systems is avoided, even when signal systems in which time sharing is integrated are used together by time sharing. History capacitors (153, 155) are connected at a preceding step to a switched capacitor filter (160) for each system, buffer capacitors (173, 175) are connected at a subsequent step to the switched capacitor filter (160) for each system, and the history capacitors and buffer capacitors, which are connected to a rotation capacitor of the switched capacitor filter (160), are switched for each time-sharing system that is input.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 16, 2014
    Assignee: Panasonic Corporation
    Inventor: Tadashi Morita
  • Patent number: 8810323
    Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: August 19, 2014
    Inventor: Mohammad Ardehali
  • Patent number: 8779848
    Abstract: A memcapacitor device includes a memcapacitive matrix interposed between a first electrode and a second electrode. The memcapacitive matrix includes deep level dopants having a first decay time constant and shallow level dopants having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance of the memcapacitor device depends upon an initial voltage applied across the memcapacitive matrix and a time dependent change in capacitance of the memcapacitor device depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D. Pickett, Julien Borghetti, Jianhua Yang
  • Publication number: 20140176233
    Abstract: A low power, high accuracy calibration circuit for filter calibration is provided. The calibration circuit includes a chargeable voltage storage element. A first measurement and adjustment circuit determines a charge time required for the voltage of the chargeable voltage storage element to substantially match a reference voltage. The circuit adjusts the voltage storage element to make the charge time approximately equal to a predetermined filter time constant value, the adjustment circuit updating the reference voltage to make the charge time substantially equal to the predetermined filter time constant value and iteratively updating the reference voltage to refine the charge time. A second circuit is configured to have substantially the predetermined filter time constant value based on the adjustment configuration determined by the adjustment of the voltage storage element and the reference voltage of the first circuit.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventor: Hong Kong Applied Science and Technology Research Institute Company Limited
  • Patent number: 8754699
    Abstract: A filter is implemented as cascaded stages, and in at least one stage all resistances are implemented as double-sampled switched-capacitor circuits. In a variation, at least one resistance is implemented as a double-sampled switched-capacitor T-network. In a variation, in an integrator stage, a resistance is implemented as a transconductance, and the cutoff frequency of the integrator stage scales with a switching frequency of a DC-DC voltage converter.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Gaurav Bawa, William Todd Harrison
  • Patent number: 8742964
    Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 3, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jonathan Adam Kleks, Ion Opris, Justin Seng
  • Patent number: 8736361
    Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: May 27, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Gustavo Castro