Abstract: A switch device for source drivers of liquid crystal displays includes a first switch module; a first switch; a second switch; a second switch module; a third switch module; a fourth switch module; a third switch; and a fourth switch; wherein when a first driving signal with a voltage level between a first voltage level and a second voltage level through the second switch module is sent to a second output terminal and a second driving signal with a voltage level between a third voltage level and a fourth voltage level through the third switch module is sent to a first output terminal, the first switch is turned on such that a first node is connected to a first voltage source with the first voltage level and the fourth switch is turned on such that a second node is connected to a fourth voltage source with the fourth voltage level.

Abstract: To implement a filter circuit with low noise and a low cutoff frequency in a smaller area, a filter circuit has a first circuit which receives an input signal supplied to an input terminal, amplifies the signal, and outputs the amplified signal to an output terminal, a first differential amplification circuit for receiving the output signal of the first circuit through a first capacitance element, a first resistance element for forming a negative feedback path between the input and output of the first differential amplification circuit, and a second resistance element for forming a negative feedback path between the output of the first differential amplification circuit and the input of the first circuit.

Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract: A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors during multiple non-overlapping time periods. The charge from one set of sampling capacitors is averaged and transferred to the filter output during one non-overlapping time and the charge from another set of sampling capacitors is averaged and transferred to the filter output during a second non-overlapping time period.

Abstract: A down-conversion filter is provided, using first and second input terminals to receive signals that are differentially outputted by a preceding circuit, and using an output terminal to output a down-converted and filtered signal. An output capacitor is coupled to the output terminal. A first switched-capacitor network is arranged between the first input terminal and the output terminal. A second switched-capacitor network is arranged between the second input terminal and the output terminal. Each switched-capacitor network has capacitors, charging switches and charge-summing switches. The charging switches are designed to alternatively couple the capacitors to the first (or second) input terminal. The charge-summing switches are designed to couple the capacitors to the output terminal.

Abstract: There is provided a filter device having a function of adjusting the center frequency of a filter. The filter device includes: a filter core unit (102) provided with an adder (109) for outputting an added signal of an input signal and a feedback signal (signal Vf), an AGC circuit for generating an amplification signal in which the added signal is amplified, and a phase shifter (111) for generating the signal Vf by shifting a phase of the amplification signal; an amplitude comparing circuit (101) for comparing the reference amplitude and the amplitude of the signal Vf; a gain control voltage generator (108) for controlling the amplification factor of the AGC circuit (110) based upon the comparison result; a frequency comparing circuit (103) for comparing the reference frequency and the frequency of the signal Vf; a phase shifter control voltage generator (117) for controlling the shift amount of the phase in the phase shifter (111) based upon the comparison result.

Abstract: Methods and related systems are described for determining the casing attenuation factor for various frequencies from measurements of the impedance of the transmitting or receiving coil of wire of. The compensation is based on two relationships. The first relationship is between one or more measured impedance parameters and the product of casing conductivity, casing thickness and electromagnetic frequency. The second relationship is between the casing correction factor and the product of casing conductivity, casing thickness and electromagnetic frequency.

Abstract: A transconductance-capacitance (Gm-C) filter of arbitrary order is provided that is biased by a bias circuit such that the Gm-C filter is robust to variations in process corner and temperature as well as input supply noise. The bias circuit includes a biased transistor that has a width-to-length ratio that is a factor X times larger than a corresponding transistor in the Gm-C filter. The biased transistor couples to ground through a switched capacitor circuit.

Abstract: There is provided a filter circuit that includes: a flying capacitor which maintains polarity when switching from an input terminal to an output terminal, and the polarity of which is reversed when switching from the output terminal to the input terminal; a first capacitor that is provided in parallel with the flying capacitor, at the input terminal of the flying capacitor; and a second capacitor that is provided in parallel with the flying capacitor, at the output terminal of the flying capacitor. The flying capacitor is switched from the input terminal to the output terminal with a delay of a predetermined time after the switching from the output terminal to the input terminal, and the flying capacitor is switched from the output terminal to the input terminal with a delay of a predetermined time after the switching from the input terminal to the output terminal.

Abstract: A charge domain filter (CDF) apparatus having a bandwidth compensation circuit is provided. The bandwidth compensation circuit includes a configurable power-reference cell (CPC) and/or a programmable-delay cell (PDC). The CPC receives and adjusts an output of the CDF to obtain a sensing power, and outputs the sensing power to the CDF. The PDC receives and delay an output of the CDF, and outputs a delay result to the CDF. The bandwidth compensation circuit having a flexible structure, so as to implement X-axis (frequency) compensation and/or Y-axis (power or gain) compensation of a frequency response diagram according to a design requirement.

Abstract: In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.

Abstract: A relaxation oscillator for generating a first and a second oscillation signals, comprising: a reference-voltage providing circuit for providing a high and a low reference voltages; switches for directing the high and low reference voltages to inputs of a transconductance amplifier and a non-inverting input of a comparator; the transconductance amplifier for generating an output current with a value determined by its transconductance value, controlled by an input tuning voltage, and multiplied by its inputs' voltage difference; a capacitor connecting between the transconductance amplifier output and ground; and the comparator for generating a first and a second digital signals; wherein the first and second digital signals are digital control signals to the switches, and the first and second oscillation signal of the relaxation oscillator respectively; wherein the oscillation frequency of the relaxation oscillator is independent of the reference voltages, achieving accurate frequency turning, and simplifying t

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: A switched capacitor circuit includes a capacitor and switches located on an input side and an output side of the capacitor. The switched capacitor circuit also includes an operational amplifier of a later stage which receives an output of the capacitor, wherein a current value of a current supplied to the operational amplifier is switched according to at least one open/closed state of at least one of the switches.

Abstract: A signal filter includes a node, a first terminal, a second terminal, and energy storage circuitry coupled to the node and the first and second terminals. The node receives an input signal and a reference signal selectively. The first terminal provides an output signal determined by the input signal and the reference signal. The second terminal receives a feedback signal indicative of the output signal. The energy storage circuitry generates the output signal at the first terminal according to the input signal and the reference signal. The energy storage circuitry also receives the input signal via the node and the feedback signal via the second terminal in alternating fashion. A dominant pole of the signal filter is controlled by the frequency at which the input signal and the feedback signal alternate.

Abstract: An exemplary filter includes N (?2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N?1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N?1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract: A charge domain filter with controllable transfer function is disclosed. The charge domain filter has a plurality of switched-capacitor networks, a switching device and a current adder. The switched-capacitor networks are interleaving controlled, and each have an input terminal and an output terminal, and the input terminals of all of the switched-capacitor networks are connected together to be coupled to an input signal. The switching device is designed for transfer function control, and is operated according to a switch control signal. The switching device determines connections between the output terminals of the switched-capacitor networks and how the output terminals of the switched-capacitor networks are coupled to the current adder and thereby generates at least one current adder input. The at least one current adder input is received by the current adder, and the current adder outputs an output signal accordingly.

Abstract: A charge domain filter (CDF) and a bandwidth compensation circuit of the CDF are provided. The CDF includes an amplifier, a plurality of switch-capacitor networks (SCNs), a connector, a current adder (CA) and a bandwidth compensation circuit. A first input terminal of the amplifier receives an input signal, and an output terminal thereof is connected to input terminals of the SCNs. The connector is connected between the output terminal of the SCNs and the CA for configuring coupling status of the output terminals of the SCNs and input terminals of the CA. The bandwidth compensation circuit senses a portion of or all of the output terminals of the SCNs and the CA, and outputs the sensing result to a second input terminal of the amplifier.

Abstract: A switched capacitor circuit with switching loss compensation mechanism includes a resonant unit and a loss compensation unit. The resonant unit generates a resonant frequency and includes a capacitor switching unit for switching an output capacitor. The loss compensation unit is coupled to the resonant unit for providing loss compensation when the capacitor switching unit outputs different capacitance values.

Abstract: The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).

Abstract: A signal filter system which uses two groups of switches to couple tap current cells with integrating cells. The first group of switches couples tap current cells with at least one shared connection or bus while the other group of switches couples the shared connection or bus with the integrating cells. Multiple shared connections can be used and the tap current cells can be divided into groups with each group sharing at least one shared connection that is dedicated to that group. The system also allows for more than one tap current cell to simultaneously be coupled to a single integrating cell.

Abstract: A switchable capacitive element having an adjustable capacitance and an improved quality factor is specified. To this end, the characteristic variables of the switchable capacitive element are optimized in accordance with the equations cited in the description.

Abstract: A pseudo-differential switched-capacitor circuit, which can be applied to various signal processing circuits, employs a floating sampling technique and an integrator feedback loop for isolating a common mode voltage disturbance and restraining a charge injection effect. The pseudo-differential switched-capacitor circuit includes a differential floating sampling circuit that has a pseudo-differential architecture, and an integrator for reducing the charge injection effect within the differential floating sampling circuit.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.

Abstract: An acoustic characteristic control apparatus supplies music signal, for example, to input terminal connected to a band-pass filter and a peaking filter. In a zero-cross detection circuit, a pulse signal corresponding to a period while a signal is positive is formed. A pulse-width measuring circuit output a signal corresponding to a pulse width. Next, the output of the pulse-width measuring circuit is inputted to one comparator and another comparator. The one comparator discriminates a time when the pulse width is equal to or larger than a first setting value, and the another comparator discriminates a time when the pulse width is equal to or smaller than a second setting value. The comparator is connected to the up terminal and the down terminal of an up/down counter. The output of the up/down counter is connected to the peaking filter through the subtractor, and acoustic characteristics of the peaking filter is controlled according to the count value of the up/down counter.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: The present invention is directed to accurately set a frequency characteristic of a filter integrated in a semiconductor integrated circuit. A semiconductor integrated circuit includes a filter circuit, a cutoff frequency calibration circuit, and a Q-factor calibration circuit. The cutoff frequency calibration circuit adjusts cutoff frequency of the filter circuit to a desired value by adjusting capacitance components of the filter circuit. After adjustment of the cutoff frequency of the filter circuit by the cutoff frequency calibration circuit, the Q-factor calibration circuit adjusts the Q factor of the filter circuit to a desired value by adjusting a resistance component of the filter circuit.

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Abstract: A sampling filter of such circuitry as not requiring a high frequency REF signal even if the number of decimation is decreased. In the sampling filter, the rotate capacitor in each switched capacitor circuit including Cr (7a-7d) arranged in four parallel arrays operates in four phases of integration, discharge, reset and feedback different from each other at the same timing. Consequently, a control signal for driving the switched capacitor circuit is used commonly. As a result, the circuit scale of a DCU (104) is reduced and the frequency of the REF signal can be lowered to the frequency of an LO signal even in operation without decimation.

Abstract: An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time.

Abstract: The sampling filter apparatus 100 includes the first sampling switch 130, the second sampling switch 131, the first integrator 1500 for integrating the charge input from the first sampling switch, the second integrator 1501 for integrating the charge input from the second sampling switch, a plurality of integrators connected to both of the first integrator and the second integrator via a charging switch, respectively, the control section 140, a plurality of charging switches, and a plurality of discharge switches. A charge input from the sampling switch 130, a charge accumulated in the capacitor 1500 and a charge accumulated in a capacitor 1510 are shared by the capacitor 1500, the capacitor 1510 and the capacitor 1530, and the charge accumulated in the capacitor 1530 is output.

Abstract: A control circuit and a conversion circuit. The control circuit may be configured to generate an analog control signal in response to a digital control signal. The conversion circuit may be configured to generate a capacitance signal in response to the analog control signal.

Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.

Abstract: A programmable active frequency-selective circuit includes a first capacitor having a fixed value and a second capacitor having a value defined by a product of a parameter and a plurality of switchable capacitors, wherein the parameter is defined by a gain, a bandwidth mode, and a process resolution. The parameter may be stored in a form of a look-up table and enables a user or manufacturer to program the gain, select the bandwidth mode and tune the process. The frequency-selective circuit may include a differential input and a differential output having a first feedback path connected across a positive output terminal to a negative input terminal and a second feedback path connected across a negative output terminal and a positive input terminal.

Abstract: A charge domain filter (CDF) and a bandwidth compensation circuit of the CDF are provided. The CDF includes an amplifier, a plurality of switch-capacitor networks (SCNs), a connector, a current adder (CA) and a bandwidth compensation circuit. A first input terminal of the amplifier receives an input signal, and an output terminal thereof is connected to input terminals of the SCNs. The connector is connected between the output terminal of the SCNs and the CA for configuring coupling status of the output terminals of the SCNs and input terminals of the CA. The bandwidth compensation circuit senses a portion of or all of the output terminals of the SCNs and the CA, and outputs the sensing result to a second input terminal of the amplifier.

Abstract: A filter circuit includes a voltage-current conversion portion that converts a voltage signal input to an input terminal to a current signal, a first capacitor unit formed by a plurality of capacitors, and in which a current signal output from the voltage-current conversion portion is sequentially input to the capacitors, the unit adding and outputting electric charges of a group of capacitors to which the current signal is input, a second capacitor unit formed by a plurality of capacitors, and in which a current signal output from the first capacitor unit is sequentially input to the capacitors, the unit adding and outputting electric charges of a group of capacitors to which the current signal is input, and a plurality of connection nodes that respectively connect a given capacitor in the first capacitor unit and a capacitor in the second capacitor unit.

Abstract: An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock signal at a control gate. The second terminal of the source/drain path of a first transistor drives a sampling capacitor. The second terminal of the source/drain channel of each subsequent transistor is connected to a backgate of a previous transistor. The backgate of the last transistor is connected to a supply voltage level. The second terminals of the subsequent transistors may be connected to corresponding buffer capacitors. The backgate of the last transistor may be supplied with the input during sampling and the supply voltage level at other times.

Abstract: An active RC filter (20) includes a first resistive element (23) and a first capacitor array (10/50) which co-acts with the first resistive element (23) to determine a bandwidth characteristic of the programmable active RC filter circuit (20). The total filter capacitance is programmed by switching various first capacitors (4-0, 1, 2 . . . 7) of a first capacitor array (10) in parallel between first and second terminals of the first capacitor array in response to a control word (B0, 1, 2 . . . 7) to determine a first portion of the bandwidth characteristic, and by switching various second capacitors (7-0, 1, 2 . . . 6) of the first capacitor array between the first and second terminals of the first capacitor array in parallel with various ones of the first capacitors (4-0, 1, 2 . . . 7) of the first capacitor array (10) in response to less significant bits (B0, 1, 2 . . . 6) of the control word (B0, 1, 2 . . . 7) to determine a second portion of the bandwidth characteristic.

Abstract: The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.

Abstract: A multi-channel integrator is provided. The multi-channel integrator includes an integrator and a plurality of channels. Each of the channels includes an input selector and a unit-gain amplifier. The input selector has a common terminal, a first selecting terminal and a second selecting terminal. The input selector selectively electrically connects the common terminal to the first selecting terminal or to the second selecting terminal. The first selecting terminal of the input selector is coupled to an input terminal of the integrator. An input terminal of the unit-gain amplifier is coupled to the second selecting terminal of the input selector.

Abstract: A low-pass filter of the present invention comprises a plurality of filter units and a regulation unit. The filter units are coupled in series with each other and receive an input signal to filter the input signal for generating an output signal. The regulation unit is coupled to the filter units to regulate voltage levels of the filter units. The low-pass filter of the present invention can be integrated within the integrated circuit and reduce the prime cost.

Abstract: A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors during multiple non-overlapping time periods. The charge from one set of sampling capacitors is averaged and transferred to the filter output during one non-overlapping time and the charge from another set of sampling capacitors is averaged and transferred to the filter output during a second non-overlapping time period.

Abstract: There is provided a filter circuit that includes a flying capacitor and a capacitor that is provided in parallel with the flying capacitor, between an input terminal and an output terminal of the flying capacitor. As the capacitor that has a predetermined capacity is provided between the input terminal and the output terminal of the flying capacitor, it is possible to provide steep attenuation characteristics in the filter circuit provided with the flying capacitor.

Abstract: The present invention discloses a method, apparatus and system for obtaining the tuning capacitance of a Gm-C filter. The method includes: integrating a simulated capacitor within a given time via a current, where the simulated capacitor simulates the capacitor of the Gm-C filter which is set to an even capacitor array; and comparing the integral voltage obtained by the integration with the reference voltage, finding a simulated capacitance that makes the integral voltage equal to the reference voltage via gradual approaching by adjusting a control code, and determining the simulated capacitance as the tuning capacitance. The present invention improves the performance of a Gm-C filter without affecting the performance of the Gm-C filter.

Abstract: A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.

Abstract: An arrangement for charge integration comprises a charge-generating circuit (2) that provides a charge-dependent signal, and a coupling circuit (20) comprising a first and a second transistor (T1, T2). The first transistor (T1) can be controlled in dependence on the charge-dependent signal. The second transistor (T2) is configured to forward the charge-dependent signal in dependence on a control signal provided by the first transistor (T1). The forwarded charge-dependent signal is integrated by an integrator (30).

Abstract: A discrete time analog filter suitable for use in a receiver and other electronics devices is described herein. In one exemplary design, an apparatus may include a transconductance amplifier, a sampler, and a discrete time analog filter. The transconductance amplifier may amplify a voltage input signal and provide an analog signal. The sampler may sample the analog signal and provide analog samples at a sampling rate. The discrete time analog filter may filter the analog samples and provide filtered analog samples either at the sampling rate for a non-decimating filter or at an output rate that is lower than the sampling rate for a decimating filter. The discrete time analog filter may also filter the analog samples with either equal weights for a rectangular filter or at least two different weights for a weighted filter.

Abstract: A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors and multiple non-overlapping time periods. The charge from the sampling capacitors is averaged and transferred to the filter output during another non-overlapping time period.

Abstract: Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.