Abstract: In accordance with an embodiment, a passive integrator includes a charge storage element coupled between first and second transistors, wherein the first transistor has a current carrying electrode coupled for receiving a signal and a current carrying electrode coupled to the charge storage element. The second transistor has a current carrying electrode coupled to the charge storage element and a second current carrying electrode coupled to another charge storage element.

Abstract: A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.

Abstract: Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.

Abstract: Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency.

Abstract: Provided is a direct sampling circuit in which signal mixing between systems is avoided, even when signal systems in which time sharing is integrated are used together by time sharing. History capacitors (153, 155) are connected at a preceding step to a switched capacitor filter (160) for each system, buffer capacitors (173, 175) are connected at a subsequent step to the switched capacitor filter (160) for each system, and the history capacitors and buffer capacitors, which are connected to a rotation capacitor of the switched capacitor filter (160), are switched for each time-sharing system that is input.

Abstract: A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.

Abstract: A memcapacitor device includes a memcapacitive matrix interposed between a first electrode and a second electrode. The memcapacitive matrix includes deep level dopants having a first decay time constant and shallow level dopants having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance of the memcapacitor device depends upon an initial voltage applied across the memcapacitive matrix and a time dependent change in capacitance of the memcapacitor device depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.

Abstract: A low power, high accuracy calibration circuit for filter calibration is provided. The calibration circuit includes a chargeable voltage storage element. A first measurement and adjustment circuit determines a charge time required for the voltage of the chargeable voltage storage element to substantially match a reference voltage. The circuit adjusts the voltage storage element to make the charge time approximately equal to a predetermined filter time constant value, the adjustment circuit updating the reference voltage to make the charge time substantially equal to the predetermined filter time constant value and iteratively updating the reference voltage to refine the charge time. A second circuit is configured to have substantially the predetermined filter time constant value based on the adjustment configuration determined by the adjustment of the voltage storage element and the reference voltage of the first circuit.

Abstract: A filter is implemented as cascaded stages, and in at least one stage all resistances are implemented as double-sampled switched-capacitor circuits. In a variation, at least one resistance is implemented as a double-sampled switched-capacitor T-network. In a variation, in an integrator stage, a resistance is implemented as a transconductance, and the cutoff frequency of the integrator stage scales with a switching frequency of a DC-DC voltage converter.

Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.

Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.

Abstract: The present disclosure relates to a signal processing circuit. The signal processing circuit includes a signal selection module, an offset module, and an amplifier module. The signal selection module is configured to select one from a plurality of input signals for outputting at least one first output signal. The voltage offset module is configured to output an offset voltage. The amplifier module, coupled to the signal selection module and the voltage offset module, is configured to sample the first output signal from the signal selection module, and offset the first output signal according to the offset voltage output from the offset voltage module, and perform an amplification gain control and data buffering processes on the offset signal.

Abstract: A charge domain filter (CDF) and a method thereof are provided. The CDF includes an amplifier, a first switch-capacitor network (SCN), a second SCN, a third SCN and a fourth SCN. Input terminals of the first and the second SCNs are coupled to first and second output terminals of the amplifier, respectively. Input and output terminals of the third SCN are coupled to output terminals of the first and the second SCNs, respectively. Input and output terminals of the fourth SCN are coupled to output terminals of the second and the first SCNs, respectively. A mode control terminal of the third SCN receives a first mode signal to set an impulse response mode of the third SCN. A mode control terminal of the fourth SCN receives a second mode signal to set an impulse response mode of the fourth SCN.

Abstract: The disclosure provides a switchable filtering circuit and the related operation method, in particular related to a filtering circuit which can be used for Bluetooth system and wireless local area network system. By using a first switch, a hybrid filtering circuit and a second switch, the received mode and transmitted mode between these two systems is realized. Moreover, the frequency responses and the bandwidth adjustments can be controlled according to the plurality of switchable resistors, the plurality of switchable capacitors and the shared and switchable resistors within the hybrid filter circuit. Moreover, the effects of high operated freedom of the circuit and the circuit size reduction can be achieved.

Abstract: The present disclosure relates to an electronic regulation device of a variable capacitance of an integrated circuit having a time parameter depending on the variable capacitance. The regulation device includes a regulation loop, and is configured to generate in output a plurality of binary regulation signals.

Abstract: An electronic device includes an adjustable filter with a first filter element, and a second filter element coupled to the first filter element. The second filter element includes a field effect transistor (FET) including a source terminal, a drain terminal, and a gate terminal. The source terminal and the gate terminal are coupled to a reference voltage. A control circuit is coupled to the drain terminal and is configured to apply a control voltage thereto to vary a capacitance between the source and drain terminals to adjust the adjustable filter.

Abstract: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Abstract: A low noise analog filter with adjustable filter frequency includes an oscillatory circuit, whose resonance frequency equals the filter frequency of the filter. The oscillatory circuit has a first circuit branch. One of the frequency determining elements is a capacitance and the other an inductance. The low noise analog filter further includes an amplifier with adjustable amplification installed in one of the two circuit branches. The output of the amplifier is connected with its inverting input via the frequency determining element arranged in such circuit branch. In filter operation, the amplifier amplifies, according to the adjusted amplification, a voltage applied across the frequency determining element arranged in such circuit branch and thereby effects a corresponding change of an electrical current flowing through such frequency determining element.

Abstract: A micro electro-mechanical system (MEMS) circuit includes a MEMS differential capacitor, a read-out circuit, a control circuit, and a compensation circuit. The MEMS differential capacitor includes a first capacitor and a second capacitor. The read-out circuit is coupled to the MEMS differential capacitor for reading a difference between the first capacitor and the second capacitor in a zero-G condition, and generating an output signal according to the difference. The control circuit is coupled to the read-out circuit for receiving the output signal and generating a control signal. The compensation circuit is coupled to the control circuit for compensating the MEMS differential capacitor according to the control signal.

Abstract: An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter includes a first switch for receiving the reflected voltage, a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first switch, a capacitor coupled to the second terminal of the resistor for holding the reflected voltage, and a second switch coupled to the resistor in parallel, wherein the resistor and the capacitor develop a filter for sampling the reflected voltage which is sampled without filtering by the filter in a first period during a disable period of a switching signal and also sampled with filtering by the filter in a second period during the disable period of the switching signal.

Abstract: A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.

Abstract: A filter network having a variable cut-off frequency can be controlled in a way that allows the cut-off frequency to be changed gradually to avoid undesirable transient effects. An impedance network (such as a resistor network) that provides a plurality of impedance values is provided. Logic, and a corresponding method, are provided to change the impedance value gradually, such as on a step-wise basis, to change the cut-off frequency gradually. The size of the impedance step and the duration of the step can be preprogrammed, and may be different for different types of events that trigger the need for a frequency change. It may also be possible for those preprogrammed values to be initial values only, with the values changing under programmed control during the frequency changing process. Other values, such as the initial and target impedance values that determine the initial and target frequency, also may be programmable.

Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.

Abstract: A FIR filter component for a voltage mode driver includes a first node, a second node, and a first switching component comprising a first transistor having a first drain/source, a gate, and a second drain/source, and also a second transistor having a first drain/source, a gate, and a second drain/source. The FIR filter component also includes a first tunable resistor coupled between the first node and a first potential, and a second tunable resistor coupled between the second node and a second potential, wherein the FIR filter component is configured to generate a first output signal at the first output node.

Abstract: A system and method for improving the efficiency of an electrical circuit includes an electrical circuit including a first capacitor having a first and second terminal, and a second capacitor having a first and second terminal. A first resistor is connected to the first terminal of the first capacitor and a first terminal of the second capacitor. A second resistor is connected to a second terminal of the first capacitor and the second terminal of the second capacitor. A rheostat is connected to the first terminal of the first capacitor. A Zener diode is connected to the rheostat and the second terminal of the second capacitor. In some implementations, a power source is connected across at least one of the first terminal of the first capacitor and the first terminal of the second capacitor and the second terminal of the first capacitor and the second terminal of the second capacitor.

Abstract: A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.

Abstract: A sampling circuit and a receiver, with relatively simple configurations, and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits, a charging switch is controlled on and off using one of four-phase control signals. A rotate capacitor shares electrical charge accumulated in an IQ generating circuit via the charging switch. A dump switch is controlled on and off using a different signal from the control signal used to control the charging switch on and off, among the four-phase control signals. A buffer capacitor shares electrical charge with the rotate capacitor via the dump switch to form an output value.

Abstract: An N-path filter with each path forming a different filter. A signal insertion block is provided at the start of the circuit and, in one embodiment, multiple memory capacitors are coupled to the signal insertion block. A bank of sequential rotating capacitors are provided along with a bank of switches. By activating selected switches, any of the memory capacitors can be coupled to selected rotating capacitors. A different filter subcircuit is formed by coupling each memory capacitor to different rotating capacitors as this creates a different signal path. By timing the switching of the rotating capacitors, signals from previous outputs can be inserted into the circuit. At the output end of the circuit, the output of the different filter subcircuits is put together into an output for the whole circuit.

Abstract: A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.

Abstract: Techniques are disclosed to provide a reference signal via a switched capacitor filter for image detector arrays in accordance with one or more embodiments. For an example embodiment, a method of providing a sampled and filtered reference signal to an image detector array includes receiving a reference signal; sampling the reference signal with a first capacitor to store a sampled reference signal based on the reference signal; coupling a second capacitor to the first capacitor to share charge stored on the first and second capacitors to generate the sampled and filtered reference signal to store on the second capacitor; and decoupling the second capacitor from the first capacitor, wherein the sampled and filtered reference signal is stored on the second capacitor to provide for one or more image detectors within the image detector array.

Abstract: Techniques are disclosed for radiation sensors that generate current signal to provide flexible placement of one or more integration intervals between resets of an integration capacitor. With flexible timing, an embodiment of the present invention provides several modes of operation including: multiple stray light blanking interval to occur during the integration cycle; range gating for LIDAR applications; time-delay-integration (TDI) with multiple short integration periods between frame resets; and hyper-resolution gating that provides better resolution than is normally possible with a fixed gate width. Numerous variations will be apparent in light of this disclosure.

Abstract: A DC voltage converter, comprising: a multi-ratio capacitive converter; a linear voltage regulator in series with the multi-ratio capacitive converter; and a controller; the controller arranged to control the ratio of the multi-ratio capacitive converter dependent upon the voltage difference across the linear voltage regulator.

Abstract: Gain setting can be performed at high speed while reducing DC offset due to a filter cutoff frequency changeover without the need for input signal muting. A filter circuit having first and second filters is capable of allowing settings of first and second cutoff frequencies. First and second filter switch circuits and a charging circuit including a charging resistor and a charging switch are provided. For a first time period, the first switch circuit is controllably turned on while the second switch circuit is controllably turned off, thereby providing the first filter function. For a second time period, the first switch circuit is controllably turned off while the second switch circuit is controllably turned on, thereby providing the second filter function. For the first time period, the charging switch is controllably turned on so that the second capacitor is charged via the charging resistor.

Abstract: The disclosed invention enables the cutoff frequency of a filter to be automatically adjusted to an arbitrary setting value within the adjustment range. An automatic cutoff frequency adjusting circuit includes a voltage/current converter circuit, a charge circuit, a discharge circuit, a digital capacitance having a plurality of electrostatic capacitances, a comparator for comparing a voltage inputted to the digital capacitance with a reference voltage, and a capacitance control circuit for controlling the digital capacitance. The time until the comparator detects that the voltage inputted to the digital capacitance is higher than the reference voltage after a reset signal has become a predetermined logic level is measured, and the digital capacitance is controlled by repeating, under a predetermined condition, processing for obtaining a next setting value of the digital capacitance, based on a measurement result, a target value of the digital capacitance, and the current value of the digital capacitance.

Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.

Abstract: In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays.

Abstract: A band-pass filter made up by an operational amplifier and by an input circuit. The input circuit is formed by a capacitive filtering element, connected to the input of the operational amplifier; a coupling switch, coupled between an input node and the capacitive filtering element; a capacitive sampling element, coupled between the input of the filter and the input node; and a sampling switch, coupled between the input node and a reference-potential line. The coupling switch and the input sampling switch close in phase opposition according to a succession of undesired components sampling and sensing steps, so that the capacitive sampling element forms a sampler for sampling the undesired component in the undesired components sampling step, in the absence of the component of interest, and forms a subtractor of the undesired components from the input signal in the sensing step.

Abstract: The following embodiments relate to an analog filter having an adjustable transfer function for use in a system or circuit that processes a signal having a changing data rate. The transfer function may be adjusted by adjusting the resistance and/or capacitance of components of the analog filter. The analog filter is calibrated based on an optimum operational parameter at a certain data rate, such as a median data rate. The analog filter may be further adjusted as the data rate of the signal changes.

Abstract: A memcapacitive device includes a first electrode having a first end and a second end and a second electrode. The device has a memcapacitive matrix interposed between the first electrode and the second electrode. The memcapacitive matrix has a non-linear capacitance with respect to a voltage across the first electrode and the second electrode. The memcapacitive matrix is configured to alter a signal applied on the first end by at least one of a) changing at least one of a rise-time and a fall-time of the signal and b) delaying the transmission of the signal based on the application of a programming voltage across the first electrode and the second electrode.

Abstract: A charge domain filter (CDF) apparatus having a bandwidth compensation circuit is provided. The bandwidth compensation circuit includes a configurable power-reference cell (CPC) and/or a programmable-delay cell (PDC). The CPC receives and adjusts an output of the CDF to obtain a sensing power, and outputs the sensing power to the CDF. The PDC receives and delay an output of the CDF, and outputs a delay result to the CDF. The bandwidth compensation circuit having a flexible structure, so as to implement X-axis (frequency) compensation and/or Y-axis (power or gain) compensation of a frequency response diagram according to a design requirement.

Abstract: An oscillator includes N greater than unity gain amplifiers, N being at least two. Each of the N greater than unity gain amplifiers has a pair of differential input terminals and a pair of differential output terminals. The oscillator further includes a first pair of variable resistances, N?1 pairs of variable resistances, N?1 pairs of variable capacitances, and a variable capacitance. The pairs of variable resistances couple differential output terminals of the N greater than unity gain amplifiers. The pairs of variable capacitances couple differential input terminals of the N greater than unity gain amplifiers. Each of the N greater than unity gain amplifiers includes a linearized operational transconductance amplifier stage coupled to a corresponding pair of the differential input terminals, and a unity gain buffer with feedback interconnected between the linearized operational transconductance amplifier stage and a corresponding pair of the differential output terminals.

Abstract: In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays.

Abstract: A server rack includes a main body, an electronic scale, and an alarm. The main body is used for receiving a number of servers. The electronic scale includes a pressure sensor and a microcontroller. The main body presses on the pressure sensor so that the pressure sensor can measure the pressure from the main body to obtain a pressure signal. The microcontroller analyzes the pressure signal to calculating the total weight of the main body and the servers. The alarm stores a predetermined weight threshold, which is the total weight of the main body and the maximum servers that the main body can bear. The alarm also compares the measured total weight with the predetermined weight threshold. When the measured total weight is larger than the predetermined weight threshold, the alarm alarms.

Abstract: A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source.

Abstract: A switched capacitor circuit includes: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other.

Abstract: In a filter circuit comprising a plurality of low pass filters (LPFs) that are connected in series, each of the plurality of LPFs comprises a switched-capacitor circuit (SC), and a fully-differential amplifier (AMP) which amplifies a signal output from the SC, and outputs the amplified signal. An AMP of an LPF which inputs a signal output from a 1-bit digital-to-analog converter (DAC) comprises a discrete-time type common-mode feedback circuit, and an AMP of an LPF which outputs a signal output from the filter circuit comprises a continuous-time type common-mode feedback circuit.

Abstract: The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator; a second switched-capacitor integrator; a quantizer; a feedback circuit and a mode device. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: A filter is implemented as cascaded stages, and in at least one stage all resistances are implemented as double-sampled switched-capacitor circuits. In a variation, at least one resistance is implemented as a double-sampled switched-capacitor T-network. In a variation, in an integrator stage, a resistance is implemented as a transconductance, and the cutoff frequency of the integrator stage scales with a switching frequency of a DC-DC voltage converter.